技术领域technical field
本发明涉及显示技术领域，尤其涉及移位寄存器单元及驱动方法、栅极驱动电路及显示装置。The invention relates to the field of display technology, in particular to a shift register unit, a driving method, a gate driving circuit and a display device.
背景技术Background technique
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid CrystalDisplay，TFT-LCD)是由水平和垂直两个方向的栅线和数据线交叉定义的像素矩阵构成的，当TFT-LCD进行显示时，通过栅线上的栅极(Gate)驱动依次对每一像素行输入一定宽度的方波进行选通，再通过数据线上的源极(Source)驱动将每一行像素所需的信号依次输出。然而，当分辨率较高时，显示器的栅极驱动和源极驱动的输出均较多，驱动电路的长度也将增大，这将不利于模组驱动电路的绑定(Bonding)工艺。Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is composed of a pixel matrix defined by the intersection of gate lines and data lines in both horizontal and vertical directions. The gate (Gate) driver of each pixel row inputs a square wave of a certain width to strobe in turn, and then outputs the signal required by each row of pixels in sequence through the source (Source) driver on the data line. However, when the resolution is high, the outputs of the gate drive and the source drive of the display are more, and the length of the drive circuit will also increase, which is not conducive to the bonding process of the module drive circuit.
为了解决上述问题，现有显示器的制造常采用GOA(Gate Driveron Array，阵列基板行驱动)电路的设计，将TFT(Thin Film Transistor，薄膜场效应晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动电路的Bonding区域以及外围布线空间，从而实现显示面板的两边对称和窄边框的美观设计。In order to solve the above problems, the manufacture of existing displays often adopts the design of GOA (Gate Driver Array, array substrate row drive) circuit, and integrates the gate switch circuit of TFT (Thin Film Transistor, thin film field effect transistor) on the array substrate of the display panel. In order to form a scanning drive for the display panel, the Bonding area of the gate drive circuit and the peripheral wiring space can be saved, thereby realizing the beautiful design of the display panel with symmetrical sides and narrow borders.
目前的一种GOA设计方案如图1所示，该栅极驱动电路上的移位寄存器包括多级级联的移位寄存器单元SR0、SR1…SRn。其中，每一级移位寄存器单元通过本级信号输出端Output将扫描信号输入到与之相对应的栅极线Gn，并将扫描信号输出到下一级SRn+1的信号输入端Input和上一级SRn-1的信号复位端Rst；用于对下一级移位寄存器单元进行启动，和对下一级移位寄存器单元进行复位。然而上述栅极驱动电路的一级移位寄存器单元，例如，SRn的信号输入端Input在接收到上一级移位寄存器单元SRn-1输出的扫描信号后，在自身的时钟信号输入端CLK输入的时钟信号的作用下，输出扫描信号。因此，上述栅极驱动电路只能实现单向扫描。这样一来，具有单向扫描的显示装置，例如手机，当用户在观影或使用过程中对屏幕进行旋转时，显示画面无法随着用户的观看方式的变化而变化。这样一来，会大大降低用户的需求和体验。A current GOA design scheme is shown in FIG. 1 . The shift register on the gate drive circuit includes multi-stage cascaded shift register units SR0, SR1...SRn. Wherein, the shift register unit of each stage inputs the scan signal to the corresponding gate line Gn through the signal output terminal Output of the current stage, and outputs the scan signal to the signal input terminal Input of the next stage SRn+1 and the upper The signal reset terminal Rst of the first-stage SRn-1 is used for starting and resetting the next-stage shift register unit. However, the first-stage shift register unit of the above-mentioned gate drive circuit, for example, after the signal input terminal Input of SRn receives the scanning signal output by the upper-stage shift register unit SRn-1, it inputs Under the action of the clock signal, the scan signal is output. Therefore, the above-mentioned gate driving circuit can only realize unidirectional scanning. In this way, for a display device with unidirectional scanning, such as a mobile phone, when the user rotates the screen during viewing or use, the displayed image cannot change with the user's viewing method. In this way, the user's needs and experience will be greatly reduced.
为了解决上述问题，本领域技术人员提出了一种能够进行双向扫描的GOA电路，不仅可以从上至下对每一行栅极进行扫描，还可以从下至上对每一行栅极进行扫描。然而，具有双向扫描功能的GOA电路，相对于单向扫描的GOA电路而言，其电路结构相对复杂，包含有数目较多的晶体管。因此，会因为一些晶体管自身耦合电容中的电量没有得到充分的释放，而导致GOA电路产生噪声干扰，从而降低GOA电路的稳定性。In order to solve the above problems, those skilled in the art have proposed a GOA circuit capable of bidirectional scanning, which can not only scan each row of gates from top to bottom, but also scan each row of gates from bottom to top. However, compared with the GOA circuit with bidirectional scanning function, the GOA circuit with bidirectional scanning function has a relatively complicated circuit structure, including a larger number of transistors. Therefore, the GOA circuit will generate noise interference due to insufficient discharge of the power in the coupling capacitance of some transistors, thereby reducing the stability of the GOA circuit.
发明内容Contents of the invention
本发明的实施例提供一种移位寄存器单元及驱动方法、栅极驱动电路及显示装置，能够降低双向扫描栅极驱动电路的噪声。Embodiments of the present invention provide a shift register unit, a driving method, a gate driving circuit and a display device, which can reduce the noise of the bidirectional scanning gate driving circuit.
为达到上述目的，本发明的实施例采用如下技术方案：In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:
本发明实施例的一方面，提供一种移位寄存器单元，包括：第一扫描控制模块、第二扫描控制模块、上拉控制模块、上拉模块、下拉控制模块以及下拉模块；An aspect of the embodiments of the present invention provides a shift register unit, including: a first scan control module, a second scan control module, a pull-up control module, a pull-up module, a pull-down control module, and a pull-down module;
所述第一扫描控制模块，分别连接第一信号输入端、第一电压端以及所述上拉控制模块；用于根据所述第一信号输入端输入的信号，导通所述上拉控制模块；The first scan control module is connected to the first signal input terminal, the first voltage terminal and the pull-up control module respectively; it is used to turn on the pull-up control module according to the signal input by the first signal input terminal ;
所述第二扫描控制模块，分别连接第二信号输入端、第二电压端以及所述上拉控制模块；用于根据所述第二信号输入端输入的信号，导通所述上拉控制模块；The second scanning control module is respectively connected to the second signal input terminal, the second voltage terminal and the pull-up control module; and is used to turn on the pull-up control module according to the signal input by the second signal input terminal ;
所述上拉控制模块，分别连接所述第一扫描控制模块、所述第二扫描控制模块、第四电压端以及上拉控制节点；用于在所述第一扫描控制模块或所述第二扫描控制模块的控制下将所述上拉控制节点的电位上拉至所述第四电压端的电压；The pull-up control module is respectively connected to the first scan control module, the second scan control module, the fourth voltage terminal and the pull-up control node; Pulling up the potential of the pull-up control node to the voltage of the fourth voltage terminal under the control of the scan control module;
所述上拉模块，分别连接第一时钟信号端、所述上拉控制节点以及本级信号输出端；用于根据所述上拉控制节点的电位，将所述第一时钟信号端输入的信号提供至所述本级信号输出端；The pull-up module is respectively connected to the first clock signal terminal, the pull-up control node, and the signal output terminal of the current stage; and is used to input the signal from the first clock signal terminal according to the potential of the pull-up control node Provided to the signal output terminal of the current stage;
所述下拉控制模块，分别连接所述下拉控制节点、所述上拉控制模块、所述第三电压端、所述第四电压端以及第二时钟信号端；用于根据所述第二时钟信号端输入的信号，控制所述下拉控制节点的电位；The pull-down control module is respectively connected to the pull-down control node, the pull-up control module, the third voltage terminal, the fourth voltage terminal and the second clock signal terminal; The signal input by the terminal controls the potential of the pull-down control node;
所述下拉模块，分别连接所述下拉控制节点、所述上拉控制节点以及所述本级信号输出端，用于在所述下拉控制节点的电位控制下将所述上拉控制节点的电位以及所述本级信号输出端的输出信号下拉至所述第三电压端的电压。The pull-down module is respectively connected to the pull-down control node, the pull-up control node and the signal output terminal of the current stage, and is used to control the potential of the pull-up control node and the potential of the pull-down control node to The output signal of the signal output terminal of the current stage is pulled down to the voltage of the third voltage terminal.
本发明实施例的另一方面，提供一种栅极驱动电路，包括多级如上所述的任意一种移位寄存器单元；Another aspect of the embodiments of the present invention provides a gate drive circuit, including any one of the above-mentioned multi-stage shift register units;
除第一级移位寄存器单元外，其余每个移位寄存器单元的第一信号输入端与其相邻的上一级移位寄存器单元的本级信号输出端相连接；Except for the shift register unit of the first stage, the first signal input end of each other shift register unit is connected to the signal output end of this stage of the adjacent upper stage shift register unit;
除最后一级移位寄存器单元外，其余每个移位寄存器单元的第二信号输入端与其相邻的下一级移位寄存器单元的本级信号输出端相连接。Except for the shift register unit of the last stage, the second signal input end of each shift register unit is connected to the signal output end of the next stage adjacent to the shift register unit of the next stage.
本发明实施例的又一方面，提供一种显示装置，包括如上所述的任意一种栅极驱动电路。Still another aspect of the embodiments of the present invention provides a display device, including any one of the above-mentioned gate driving circuits.
本发明实施例的有一方面，提供一种移位寄存器单元的驱动方法，包括：In one aspect of the embodiments of the present invention, a driving method for a shift register unit is provided, including:
第一阶段，第一扫描控制模块或第二扫描模块，通过第一信号输入端或第二信号输入端输入的信号将上拉控制模块导通，所述上拉控制模块将上拉控制节点的电位上拉至第四电压端的电压；通过所述上拉模块将所述第四电压端的电压进行存储；In the first stage, the first scan control module or the second scan module turns on the pull-up control module through the signal input from the first signal input terminal or the second signal input terminal, and the pull-up control module turns on the pull-up control node pull up the potential to the voltage of the fourth voltage terminal; store the voltage of the fourth voltage terminal through the pull-up module;
第二阶段，所述上拉控制节点控制所述上拉模块将第一时钟信号端输入的信号提供至本级信号输出端；下拉控制模块将下拉控制节点的电位下拉至第三电压端的电压；In the second stage, the pull-up control node controls the pull-up module to provide the signal input from the first clock signal terminal to the signal output terminal of the current stage; the pull-down control module pulls down the potential of the pull-down control node to the voltage of the third voltage terminal;
第三阶段，所述下拉控制模块通过第二时钟信号端将所述下拉控制节点的电位上拉至所述第四电压端的电压；所述下拉控制节点通过下拉模块将所述上拉控制节点的电位和以及所述本级信号输出端的输出信号下拉至所述第三电压端的电压。In the third stage, the pull-down control module pulls up the potential of the pull-down control node to the voltage of the fourth voltage terminal through the second clock signal terminal; The potential sum and the output signal of the signal output terminal of the current stage are pulled down to the voltage of the third voltage terminal.
本发明实施例提供一种移位寄存器单元及驱动方法、栅极驱动电路及显示装置。所述移位寄存器单元包括第一扫描控制模块、第二扫描控制模块、上拉控制模块、上拉模块以及下拉控制模块。这样一来，可以分别通过与所述第一扫描控制模块相连接的第一信号输入端，以及与所述第二扫描控制模块相连接的第二信号输入端输入的信号对该栅极驱动电路进行正向或反向扫描，从而实现双向扫描。并且，当移位寄存器单元的本级信号输出端需要输出扫描信号时，上拉控制模块可以通过控制上拉控制节点的电位，使得上拉模块导通，将第一时钟信号端输入的信号作为扫描信号通过本级信号输出端输出，以对一行栅线进行扫描。此外，当移位寄存器单元的本级信号输出端不需要输出扫描信号时，所述下拉控制模块能够通过控制下拉控制节点的电位，以对上拉控制节点和本级信号输出端进行下拉，从而可以对上述双向扫描栅极驱动电路进行降噪。Embodiments of the present invention provide a shift register unit, a driving method, a gate driving circuit, and a display device. The shift register unit includes a first scan control module, a second scan control module, a pull-up control module, a pull-up module and a pull-down control module. In this way, the gate drive circuit can be connected to the first signal input terminal connected to the first scan control module and the signal input from the second signal input terminal connected to the second scan control module. Forward or reverse scanning is performed to achieve bi-directional scanning. Moreover, when the signal output terminal of the shift register unit needs to output the scan signal, the pull-up control module can control the potential of the pull-up control node to make the pull-up module turn on, and use the signal input by the first clock signal terminal as The scan signal is output through the signal output terminal of the current stage to scan a row of gate lines. In addition, when the signal output terminal of the current stage of the shift register unit does not need to output the scan signal, the pull-down control module can pull down the pull-up control node and the signal output terminal of the current stage by controlling the potential of the pull-down control node, thereby Noise reduction can be performed on the above bidirectional scanning gate drive circuit.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为现有技术提供的一种栅极驱动电路的结构示意图；FIG. 1 is a schematic structural diagram of a gate drive circuit provided in the prior art;
图2为本发明实施例提供的一种移位寄存器单元的结构示意图；FIG. 2 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention;
图3为本发明实施例提供的另一种移位寄存器单元的结构示意图；FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention;
图4为本发明实施例提供的一种移位寄存器单元工作信号时序波形图；FIG. 4 is a timing waveform diagram of a working signal of a shift register unit provided by an embodiment of the present invention;
图5为本发明实施例提供的另一种移位寄存器单元工作信号时序波形图；FIG. 5 is a timing waveform diagram of another working signal of a shift register unit provided by an embodiment of the present invention;
图6-图8为本发明实施例提供的一种移位寄存器单元正向扫描时的工作状态示意图；6-8 are schematic diagrams of working states of a shift register unit provided in an embodiment of the present invention during forward scanning;
图9为本发明实施例提供的一种栅极驱动电路的结构示意图；FIG. 9 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention;
图10为本发明实施例提供的一种栅极驱动电路的信号时序波形图；FIG. 10 is a signal timing waveform diagram of a gate drive circuit provided by an embodiment of the present invention;
图11为本发明实施例提供的另一种栅极驱动电路的信号时序波形图。FIG. 11 is a signal timing waveform diagram of another gate driving circuit provided by an embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明实施例提供一种移位寄存器单元，如图2所示，可以包括：第一扫描控制模块10、第二扫描控制模块20、上拉控制模块30、上拉模块40、下拉控制模块50以及下拉模块60。An embodiment of the present invention provides a shift register unit, as shown in FIG. 2 , which may include: a first scan control module 10, a second scan control module 20, a pull-up control module 30, a pull-up module 40, and a pull-down control module 50 and a pull-down module 60 .
上述第一扫描控制模块10，可以分别连接第一信号输入端Input1、第一电压端Vcn以及上拉控制模块30。用于根据第一信号输入端Input1输入的信号，导通所述上拉控制模块30。The above-mentioned first scan control module 10 can be connected to the first signal input terminal Input1 , the first voltage terminal Vcn and the pull-up control module 30 respectively. It is used for turning on the pull-up control module 30 according to the signal input from the first signal input terminal Input1.
上述第二扫描控制模块20，可以分别连接第二信号输入端Input2、第二电压端Vcnb以及上拉控制模块20；用于根据第二信号输入端Input2输入的信号，导通上拉控制模块30。The above-mentioned second scanning control module 20 can be respectively connected to the second signal input terminal Input2, the second voltage terminal Vcnb and the pull-up control module 20; it is used to turn on the pull-up control module 30 according to the signal input by the second signal input terminal Input2 .
上述上拉控制模块30，可以分别连接第一扫描控制模块10、第二扫描控制模块20、第四电压端VGH以及上拉控制节点PU。用于在第一扫描控制模块10或第二扫描控制模块20的控制下将上拉控制节点PU的电位上拉至第四电压端VGH的电压。The above-mentioned pull-up control module 30 can be respectively connected to the first scan control module 10 , the second scan control module 20 , the fourth voltage terminal VGH and the pull-up control node PU. It is used for pulling up the potential of the pull-up control node PU to the voltage of the fourth voltage terminal VGH under the control of the first scan control module 10 or the second scan control module 20 .
上述上拉模块40，可以分别连接第一时钟信号端CLK、上拉控制节PU点以及本级信号输出端Output。用于根据上拉控制节点PU的电位，将上述第一时钟信号端输入CLK的信号提供至本级信号输出端Output。以对与该本级信号输出端相对应的栅线进行扫描。The above-mentioned pull-up module 40 can be respectively connected to the first clock signal terminal CLK, the pull-up control node PU and the signal output terminal Output of the current stage. According to the potential of the pull-up control node PU, the signal input to the first clock signal terminal CLK is provided to the signal output terminal Output of the current stage. to scan the gate line corresponding to the signal output end of the current stage.
上述下拉控制模块50，分别连接下拉控制节点PD、上拉控制模块30、第三电压端VGL、第四电压端VGH以及第二时钟信号端CLKB。用于根据上述第二时钟信号端CLKB输入的信号，控制下拉控制节点PD的电位。The pull-down control module 50 is respectively connected to the pull-down control node PD, the pull-up control module 30 , the third voltage terminal VGL, the fourth voltage terminal VGH and the second clock signal terminal CLKB. It is used to control the potential of the pull-down control node PD according to the signal input from the second clock signal terminal CLKB.
上述下拉模块60，可以分别连接下拉控制节点PD、上拉控制节点PU以及本级信号输出端Output，用于在下拉控制节点PD的电位控制下将上拉控制节点PU的电位以及本级信号输出端Output的输出信号下拉至第三电压端VGL的电压。The above-mentioned pull-down module 60 can be respectively connected to the pull-down control node PD, the pull-up control node PU and the signal output terminal Output of the current stage, and is used to output the potential of the pull-up control node PU and the signal output of the current stage under the control of the potential of the pull-down control node PD. The output signal at the terminal Output is pulled down to the voltage of the third voltage terminal VGL.
需要说明的是，第一、本发明实施例是以将正向扫描信号STV_U和反向扫描信号STV_D分别接入到各级移位寄存器单元的第一信号输入端Input1和第二信号输入端Input2为例进行的说明。具体的，各级移位寄存器根据输入的正向扫描信号STV_U，通过各级的本级信号输出端Output按正向(从上至下)顺序地将扫描信号输出到与上述本级信号输出端Output对应的栅线上。或者，各级移位寄存器根据输入的反向扫描信号STV_D，通过各级的本级信号输出端Output按反向(从下至上)顺序地将扫描信号输出到与上述本级信号输出端Output对应的栅线上。It should be noted that, firstly, in the embodiment of the present invention, the forward scanning signal STV_U and the reverse scanning signal STV_D are respectively connected to the first signal input terminal Input1 and the second signal input terminal Input2 of the shift register units of each level as an example. Specifically, according to the input forward scanning signal STV_U, the shift registers at all levels output the scanning signals to the above-mentioned signal output terminals in the forward direction (from top to bottom) sequentially through the signal output terminals Output of each level. On the grid line corresponding to Output. Alternatively, the shift registers at each level output the scanning signals in reverse order (from bottom to top) through the signal output terminals Output of each level to the corresponding signal output terminals Output of the above-mentioned levels according to the input reverse scanning signal STV_D on the grid.
当然，正向扫描信号STV_U和反向扫描信号被STV_D还可以分别接入到各级移位寄存器单元的第二信号输入端Input2和第一信号输入端Input1。具体的扫描过程同理可得，此处不再赘述。Of course, the forward scan signal STV_U and the reverse scan signal STV_D can also be respectively connected to the second signal input terminal Input2 and the first signal input terminal Input1 of the shift register units of each level. The specific scanning process can be obtained in the same way, and will not be repeated here.
第二、本发明实施例中是以第三电压端VGL输入低电平、第四电压端VGH输入高电平为例进行的说明。Second, in the embodiment of the present invention, the third voltage terminal VGL inputs a low level and the fourth voltage terminal VGH inputs a high level as an example for description.
本发明实施例提供一种移位寄存器单元，可以包括第一扫描控制模块、第二扫描控制模块、上拉控制模块、上拉模块以及下拉控制模块。这样一来，可以分别通过与所述第一扫描控制模块相连接的第一信号输入端，以及与所述第二扫描控制模块相连接的第二信号输入端输入的信号对该栅极驱动电路进行正向或反向扫描，从而实现双向扫描。并且，当移位寄存器单元的本级信号输出端需要输出扫描信号时，上拉控制模块可以通过控制上拉控制节点的电位，使得上拉模块导通，将第一时钟信号端输入的信号作为扫描信号通过本级信号输出端输出，以对一行栅线进行扫描。此外，当移位寄存器单元的本级信号输出端不需要输出扫描信号时，所述下拉控制模块能够通过控制下拉控制节点的电位，以对上拉控制节点和本级信号输出端进行下拉，从而可以对上述双向扫描栅极驱动电路进行降噪。An embodiment of the present invention provides a shift register unit, which may include a first scan control module, a second scan control module, a pull-up control module, a pull-up module, and a pull-down control module. In this way, the gate drive circuit can be connected to the first signal input terminal connected to the first scan control module and the signal input from the second signal input terminal connected to the second scan control module. Forward or reverse scanning is performed to achieve bi-directional scanning. Moreover, when the signal output terminal of the shift register unit needs to output the scan signal, the pull-up control module can control the potential of the pull-up control node to make the pull-up module turn on, and use the signal input by the first clock signal terminal as The scan signal is output through the signal output terminal of the current stage to scan a row of gate lines. In addition, when the signal output terminal of the current stage of the shift register unit does not need to output the scan signal, the pull-down control module can pull down the pull-up control node and the signal output terminal of the current stage by controlling the potential of the pull-down control node, thereby Noise reduction can be performed on the above bidirectional scanning gate drive circuit.
以下，将结合图3对上述移位寄存器单元的具体结构进行详细的举例说明。Hereinafter, the specific structure of the above-mentioned shift register unit will be illustrated in detail with reference to FIG. 3 .
需要说明的是，移位寄存器单元的上述各个模块中包括多个晶体管，以下实施例中是以移位寄存器单元中的晶体管均采用N型晶体管为例进行的说明。It should be noted that each of the above-mentioned modules of the shift register unit includes a plurality of transistors. In the following embodiments, the transistors in the shift register unit all use N-type transistors as an example for illustration.
实施例一Embodiment one
上述第一扫描控制模块10可以包括：第一晶体管M1和第二晶体管M2。The above-mentioned first scan control module 10 may include: a first transistor M1 and a second transistor M2.
其中，第一晶体管M1的第一极连接和栅极连接第一电压端Vcn，第二极与第二晶体管M2的栅极相连接。Wherein, the first electrode and the gate of the first transistor M1 are connected to the first voltage terminal Vcn, and the second electrode is connected to the gate of the second transistor M2.
第二晶体管M2的第一极连接所述第一信号输入端Input1，栅极连接第一晶体管M1的第二极，第二极与上拉控制模块30相连接。The first pole of the second transistor M2 is connected to the first signal input terminal Input1 , the gate is connected to the second pole of the first transistor M1 , and the second pole is connected to the pull-up control module 30 .
这样一来，如图4所示，在第一电压端Vcn输入高电平的情况下，所述第一扫描控制模块10导通，当第一信号输入端Input1输入正向扫描信号STV_U时，各级移位寄存器单元开始正向扫描工作。In this way, as shown in FIG. 4 , when the first voltage terminal Vcn inputs a high level, the first scanning control module 10 is turned on, and when the first signal input terminal Input1 inputs the forward scanning signal STV_U, The shift register units at all levels start to scan forward.
上述第二扫描控制模块20可以包括：第三晶体管M3和第四晶体管M4。The above-mentioned second scan control module 20 may include: a third transistor M3 and a fourth transistor M4.
其中，第三晶体管M3的第一极和栅极连接第二电压端Vcnb，第二极与第四晶体管M4的栅极相连接。Wherein, the first electrode and the gate of the third transistor M3 are connected to the second voltage terminal Vcnb, and the second electrode is connected to the gate of the fourth transistor M4.
第四晶体管M4的第一极连接第二信号输入端Input2，栅极连接上述第三晶体管M3的第二极，第二极与上拉控制模块30相连接。The first pole of the fourth transistor M4 is connected to the second signal input terminal Input2 , the gate is connected to the second pole of the third transistor M3 , and the second pole is connected to the pull-up control module 30 .
这样一来，如图5所示，在第二电压端Vcnb输入高电平的情况下，所述第二扫描控制模块20导通，当第二信号输入端Input2输入反向扫描信号STV_D时，使得各级移位寄存器单元开始反向扫描工作。In this way, as shown in FIG. 5 , when the second voltage terminal Vcnb inputs a high level, the second scanning control module 20 is turned on, and when the second signal input terminal Input2 inputs the reverse scanning signal STV_D, Make the shift register units of all levels start reverse scanning work.
上拉控制模块30可以包括：第七晶体管M7。The pull-up control module 30 may include: a seventh transistor M7.
第七晶体管M7，其第一极连接上拉控制节点PU，第二极连接第四电压端VGH，栅极与第二晶体管M2和第四晶体管M4的第二极相连接。The seventh transistor M7 has a first pole connected to the pull-up control node PU, a second pole connected to the fourth voltage terminal VGH, and a gate connected to second poles of the second transistor M2 and the fourth transistor M4.
上拉模块40可以包括：第八晶体管M8、第九晶体管M9以及第一电容C1。The pull-up module 40 may include: an eighth transistor M8, a ninth transistor M9 and a first capacitor C1.
第八晶体管M8的第一极连接第一时钟信号端CLK，栅极连接上拉控制节点PU，第二极与本级信号输出端Output相连接。The first pole of the eighth transistor M8 is connected to the first clock signal terminal CLK, the gate is connected to the pull-up control node PU, and the second pole is connected to the signal output terminal Output of the current stage.
第一电容C1的一端连接上拉控制节点PU，另一端与第八晶体管M8的第二极相连接。One end of the first capacitor C1 is connected to the pull-up control node PU, and the other end is connected to the second pole of the eighth transistor M8.
下拉控制模块50可以包括：第六晶体管M6、第九晶体管M9、以及第十一晶体管M11。The pull-down control module 50 may include: a sixth transistor M6, a ninth transistor M9, and an eleventh transistor M11.
其中，第六晶体管M6，其第一极连接下拉控制节点PD，第二极连接第三电压端VGL，栅极与第二晶体管M2和第四晶体管M4的第二极相连接。Wherein, the sixth transistor M6 has its first pole connected to the pull-down control node PD, its second pole connected to the third voltage terminal VGL, and its gate connected to the second transistor M2 and the second transistor M4's second poles.
第九晶体管M9的第一极连接第三电压端VGL，栅极连接第八晶体管M8的第二极，第二极与下拉控制节点PD相连接。The first pole of the ninth transistor M9 is connected to the third voltage terminal VGL, the gate is connected to the second pole of the eighth transistor M8, and the second pole is connected to the pull-down control node PD.
第十一晶体管M11的第一极连接第四电压端VGH，第二极与下拉控制节点PD相连接，栅极与第二时钟信号端CLKB相连接。The first pole of the eleventh transistor M11 is connected to the fourth voltage terminal VGH, the second pole is connected to the pull-down control node PD, and the gate is connected to the second clock signal terminal CLKB.
下拉模块60可以包括：第五晶体管M5、第十晶体管M10以及第二电容C2。The pull-down module 60 may include: a fifth transistor M5, a tenth transistor M10 and a second capacitor C2.
其中，第五晶体管M5的第一极连接上拉控制节点PU，栅极连接下拉控制节点PD，第二极与第三电压端VGL相连接。Wherein, the first pole of the fifth transistor M5 is connected to the pull-up control node PU, the gate is connected to the pull-down control node PD, and the second pole is connected to the third voltage terminal VGL.
第十晶体管M10的第一极连接第三电压端VGL，栅极连接下拉控制节点PD，第二极与第八晶体管M8的第二极和第九晶体管M9的栅极相连接。The first pole of the tenth transistor M10 is connected to the third voltage terminal VGL, the gate is connected to the pull-down control node PD, and the second pole is connected to the second pole of the eighth transistor M8 and the gate of the ninth transistor M9.
第二电容C2的一端连接第十晶体管M10的栅极，第二极与第十晶体管M10的第一极相连接。One terminal of the second capacitor C2 is connected to the gate of the tenth transistor M10, and the second terminal is connected to the first terminal of the tenth transistor M10.
需要说明的是，上述晶体管的第一极可以是源级，第二极可以是漏极。It should be noted that, the first pole of the above-mentioned transistor may be a source, and the second pole may be a drain.
以下，根据正向扫描的时序工作图，如图4所示，结合图3所示的移位寄存器单元，对该移位寄存器单元的工作过程进行详细的描述。In the following, according to the timing diagram of forward scanning, as shown in FIG. 4 , the working process of the shift register unit will be described in detail in combination with the shift register unit shown in FIG. 3 .
实施例二Embodiment two
第一阶段T1，Vcn＝1；CLKB＝1；CLK＝0；PU＝1；PD＝0；Input1＝1；Output＝0。需要说明的是，以下实施例中，0表示低电平VGL；1表示高电平VGH。In the first stage T1, Vcn=1; CLKB=1; CLK=0; PU=1; PD=0; Input1=1; Output=0. It should be noted that, in the following embodiments, 0 represents a low level VGL; 1 represents a high level VGH.
如图6所示，第一电压端Vcn输入高电平，将第一晶体管M1和第二晶体管M2导通。在此情况下，第一信号输入端Input1输入的正向扫描信号STV_U为高电平，从而使得第七晶体管M7、第六晶体管M6导通，由于第七晶体管M7的第二极连接第四电压端VGH，从而将上拉控制节点PU的电位拉高至高电平，并对第一电容C1进行充电。第八晶体管M8导通，将第一时钟信号端CLK输入的低电平传输至本级信号输出端Output，使得本级信号输出端Output输出低电平，不会对与其相对应的栅线进行扫描。As shown in FIG. 6 , the first voltage terminal Vcn inputs a high level to turn on the first transistor M1 and the second transistor M2 . In this case, the positive scanning signal STV_U input from the first signal input terminal Input1 is at a high level, thereby making the seventh transistor M7 and the sixth transistor M6 conduct, because the second pole of the seventh transistor M7 is connected to the fourth voltage terminal VGH, thereby pulling up the potential of the pull-up control node PU to a high level, and charging the first capacitor C1. The eighth transistor M8 is turned on, and transmits the low level input from the first clock signal terminal CLK to the signal output terminal Output of the current stage, so that the signal output terminal Output of the current stage outputs a low level, and the corresponding gate line will not be scanning.
由于第六晶体管M6导通，因此即使第二时钟信号端CLKB1输入高电平，将第十一晶体管M11导通，下拉控制节点PD的电位仍然会被第六晶体管M6拉低至低电平。这样一来，第五晶体管M5截止，不会将上拉控制节点PU的电位拉低。以保证第一电容C1处于充电状态。此外，第九晶体管M9和第十晶体管M10处于截止状态。Since the sixth transistor M6 is turned on, even if the second clock signal terminal CLKB1 inputs a high level to turn on the eleventh transistor M11, the potential of the pull-down control node PD will still be pulled down to a low level by the sixth transistor M6. In this way, the fifth transistor M5 is turned off and will not pull down the potential of the pull-up control node PU. To ensure that the first capacitor C1 is in a charged state. In addition, the ninth transistor M9 and the tenth transistor M10 are in an off state.
综上所述，第一阶段T1为该移位寄存器单元中第一电容C1的预充电阶段。To sum up, the first stage T1 is the pre-charging stage of the first capacitor C1 in the shift register unit.
第二阶段T2，Vcn＝1；CLKB＝0；CLK＝1；PU＝1；PD＝0；Input1＝0；Output＝1。In the second stage T2, Vcn=1; CLKB=0; CLK=1; PU=1; PD=0; Input1=0; Output=1.
如图7所示，第一电压端Vcn输入高电平，第一晶体管M1和第二晶体管M2继续保持导通状态。在此情况下，第一信号输入端Input1输入的正向扫描信号STV_U为低电平，从而使得第七晶体管M7、第六晶体管M6处于截止状态，在第一电容C1的自举作用下，经PU的电位进一步拉高。第八晶体管M8仍然处于导通状态，将第一时钟信号端CLK输入的高电平传输至本级信号输出端Output，使得本级信号输出端Output输出高电平，并对与其相对应的栅线进行扫描。As shown in FIG. 7 , the first voltage terminal Vcn inputs a high level, and the first transistor M1 and the second transistor M2 continue to be turned on. In this case, the forward scanning signal STV_U input by the first signal input terminal Input1 is at a low level, so that the seventh transistor M7 and the sixth transistor M6 are in the cut-off state, and under the bootstrap action of the first capacitor C1, through The potential of PU is further pulled up. The eighth transistor M8 is still in the conduction state, and transmits the high level input by the first clock signal terminal CLK to the signal output terminal Output of the current stage, so that the signal output terminal Output of the current stage outputs a high level, and the corresponding gate line to scan.
此外，第九晶体管M9导通，将第三电压端VGL的电压输入值第十晶体管M10的栅极，由于第三电压端VGL的电压为低电平，因此，第十晶体管M10截止。第二时钟信号端CLKB1输入低电平，第十一晶体管M11截止。In addition, the ninth transistor M9 is turned on, and the voltage of the third voltage terminal VGL is input to the gate of the tenth transistor M10. Since the voltage of the third voltage terminal VGL is at a low level, the tenth transistor M10 is turned off. The second clock signal terminal CLKB1 inputs a low level, and the eleventh transistor M11 is turned off.
综上所述，第二阶段T2为该移位寄存器单元打开的阶段。In summary, the second stage T2 is a stage in which the shift register unit is turned on.
第二阶段T3，Vcn＝1；CLKB＝1；CLK＝0；PU＝0；PD＝1；Input1＝0；Output＝0。In the second stage T3, Vcn=1; CLKB=1; CLK=0; PU=0; PD=1; Input1=0; Output=0.
如图8所示，第一电压端Vcn输入高电平，第一晶体管M1和第二晶体管M2继续保持导通状态。在此情况下，第一信号输入端Input1输入的正向扫描信号STV_U为低电平，从而使得第七晶体管M7、第六晶体管M6处于截止状态。As shown in FIG. 8 , the first voltage terminal Vcn inputs a high level, and the first transistor M1 and the second transistor M2 continue to be turned on. In this case, the forward scanning signal STV_U input from the first signal input terminal Input1 is at a low level, so that the seventh transistor M7 and the sixth transistor M6 are in a cut-off state.
第二时钟信号端CLKB1输入高电平，第十一晶体管M11导通，将下拉控制节点PD的电位拉升至高电平。由于第六晶体管M6处于截止状态，因此不会将下拉控制节点PD的电位拉低。在此情况下，第五晶体管M5导通，上拉控制节点PU的电位被拉至低电平，第八晶体管M8处于截止状态，本级信号输出端Output无输出。这样一来，在下一帧扫描信号输入之前上述第五晶体管M5均处于导通的状态，从而有效避免了非工作状态下的上拉控制节点PU噪声的产生。The second clock signal terminal CLKB1 inputs a high level, the eleventh transistor M11 is turned on, and the potential of the pull-down control node PD is pulled up to a high level. Since the sixth transistor M6 is in a cut-off state, the potential of the pull-down control node PD will not be pulled down. In this case, the fifth transistor M5 is turned on, the potential of the pull-up control node PU is pulled to a low level, the eighth transistor M8 is in a cut-off state, and the signal output terminal Output of the current stage has no output. In this way, the above-mentioned fifth transistor M5 is in a conducting state before the scanning signal of the next frame is input, thereby effectively avoiding the generation of noise of the pull-up control node PU in a non-working state.
与此同时，第十晶体管M10导通，可以将本级信号输出端Output的电位拉低至点电平，从而减小了非工作状态下的本级信号输出端Output噪声的产生。At the same time, the tenth transistor M10 is turned on, which can pull down the potential of the signal output terminal Output of the current stage to a point level, thereby reducing the generation of noise at the signal output terminal Output of the current stage in a non-working state.
综上所述，第三阶段T3可以为该移位寄存器单元的复位降噪阶段。To sum up, the third stage T3 may be a reset noise reduction stage of the shift register unit.
上述是以正向扫描为例进行的说明，反向扫描同理可得，这里不再赘述。The above is described by taking the forward scanning as an example, and the reverse scanning can be obtained in the same way, and will not be repeated here.
需要说明的是，上述实施例中的晶体管均是以N型晶体管为例进行的说明，当均采用P型晶体管时。具体的工作过程可以参照上述N型晶体管构成的移位寄存器单元的工作原理，其中需要相应调整驱动信号的时序，此处不再赘述。It should be noted that, the transistors in the above embodiments are all described by taking N-type transistors as an example, and when P-type transistors are all used. For the specific working process, refer to the working principle of the above-mentioned shift register unit composed of N-type transistors, in which the timing of the driving signal needs to be adjusted accordingly, which will not be repeated here.
本发明实施例提供一种栅极驱动电路，如图9所示，包括多级如上所述的移位寄存器单元(SR0、SR1…SRn)。An embodiment of the present invention provides a gate driving circuit, as shown in FIG. 9 , comprising multiple stages of shift register units (SR0, SR1 . . . SRn) as described above.
第一级移位寄存器单元SR0外，其余每个移位寄存器单元的第一信号输入端Input1与其相邻的上一级移位寄存器单元的本级信号输出端Output相连接。Except for the shift register unit SR0 of the first stage, the first signal input terminal Input1 of each other shift register unit is connected to the signal output terminal Output of the adjacent upper stage shift register unit.
除最后一级移位寄存器单元SRn外，其余每个移位寄存器单元的第二信号输入端Input2与其相邻的下一级移位寄存器单元的本级信号输出端Output相连接。Except for the shift register unit SRn of the last stage, the second signal input terminal Input2 of each other shift register unit is connected to the signal output terminal Output of the next stage of the adjacent shift register unit.
具体的，当栅极驱动电路进行正向扫描时，各个信号输入的时序图如图10所示，该GOA电路的各行扫描信号为G1、G2、G3、G4、…Gn-1、Gn；当栅极驱动电路进行反向扫描时，各个信号输入的时序图如图11所示，该GOA电路的各行扫描信号为Gn、Gn-1、Gn-2、Gn-3…G2、G1。Specifically, when the gate drive circuit performs forward scanning, the timing diagram of each signal input is shown in Figure 10, and the scanning signals of each row of the GOA circuit are G1, G2, G3, G4, ... Gn-1, Gn; When the gate drive circuit performs reverse scanning, the timing diagram of each signal input is shown in Figure 11. The scanning signals of each row of the GOA circuit are Gn, Gn-1, Gn-2, Gn-3...G2, G1.
本发明实施例提供一种栅极驱动电路，包括移位寄存器单元。该移位寄存器单元包括第一扫描控制模块、第二扫描控制模块、上拉控制模块、上拉模块以及下拉控制模块。这样一来，可以分别通过与所述第一扫描控制模块相连接的第一信号输入端，以及与所述第二扫描控制模块相连接的第二信号输入端输入的信号对该栅极驱动电路进行正向或反向扫描，从而实现双向扫描。并且，当移位寄存器单元的本级信号输出端需要输出扫描信号时，上拉控制模块可以通过控制上拉控制节点的电位，使得上拉模块导通，将第一时钟信号端输入的信号作为扫描信号通过本级信号输出端输出，以对一行栅线进行扫描。此外，当移位寄存器单元的本级信号输出端不需要输出扫描信号时，所述下拉控制模块能够通过控制下拉控制节点的电位，以对上拉控制节点和本级信号输出端进行下拉，从而可以对上述双向扫描栅极驱动电路进行降噪。An embodiment of the present invention provides a gate driving circuit, including a shift register unit. The shift register unit includes a first scan control module, a second scan control module, a pull-up control module, a pull-up module and a pull-down control module. In this way, the gate drive circuit can be connected to the first signal input terminal connected to the first scan control module and the signal input from the second signal input terminal connected to the second scan control module. Forward or reverse scanning is performed to achieve bi-directional scanning. Moreover, when the signal output terminal of the shift register unit needs to output the scan signal, the pull-up control module can control the potential of the pull-up control node to make the pull-up module turn on, and use the signal input by the first clock signal terminal as The scan signal is output through the signal output terminal of the current stage to scan a row of gate lines. In addition, when the signal output terminal of the current stage of the shift register unit does not need to output the scan signal, the pull-down control module can pull down the pull-up control node and the signal output terminal of the current stage by controlling the potential of the pull-down control node, thereby Noise reduction can be performed on the above bidirectional scanning gate drive circuit.
本发明实施例提供一种显示装置，包括如上所述的任意一种栅极驱动电路。具有与本发明前述实施例提供的栅极驱动电路相同的有益效果，由于栅极驱动电路在前述实施例中已经进行了详细说明，此处不再赘述。An embodiment of the present invention provides a display device, including any one of the above-mentioned gate driving circuits. It has the same beneficial effects as the gate driving circuit provided by the foregoing embodiments of the present invention, and since the gate driving circuit has been described in detail in the foregoing embodiments, it will not be repeated here.
该显示装置具体可以为液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的液晶显示产品或者部件。The display device may specifically be any liquid crystal display product or component with a display function, such as a liquid crystal display, a liquid crystal TV, a digital photo frame, a mobile phone, and a tablet computer.
本发明实施例提供一种移位寄存器单元的驱动方法，可以包括：An embodiment of the present invention provides a driving method for a shift register unit, which may include:
第一阶段，第一扫描控制模块10或第二扫描模块20，通过第一信号输入端Input1或第二信号输入端Input2输入的信号将上拉控制模块30导通，所述上拉控制模块30将上拉控制节点PU的电位上拉至第四电压端VGH的电压；通过上拉模块30将第四电压端VGH的电压进行存储。第一阶段为该移位寄存器单元的预充电阶段。In the first stage, the first scan control module 10 or the second scan module 20 turns on the pull-up control module 30 through the signal input from the first signal input terminal Input1 or the second signal input terminal Input2, and the pull-up control module 30 The potential of the pull-up control node PU is pulled up to the voltage of the fourth voltage terminal VGH; the voltage of the fourth voltage terminal VGH is stored through the pull-up module 30 . The first phase is the pre-charging phase of the shift register unit.
第二阶段，上拉控制节点PU控制上拉模块40将第一时钟信号端CLK输入的信号提供至本级信号输出端Output；下拉控制模块50将下拉控制节点PD的电位下拉至第三电压端VGL的电压。第二阶段T2为该移位寄存器单元打开的阶段。In the second stage, the pull-up control node PU controls the pull-up module 40 to provide the signal input by the first clock signal terminal CLK to the signal output terminal Output of the current stage; the pull-down control module 50 pulls down the potential of the pull-down control node PD to the third voltage terminal VGL voltage. The second stage T2 is a stage in which the shift register unit is turned on.
第三阶段，下拉控制模块50通过第二时钟信号端CLKB将下拉控制节点PD的电位上拉至第四电压端VGH的电压；下拉控制节点PD通过下拉模块60将上拉控制节点PD的电位和以及本级信号输出端Output的输出信号下拉至第三电压端VGL的电压。第三阶段T3可以为该移位寄存器单元的复位降噪阶段。In the third stage, the pull-down control module 50 pulls up the potential of the pull-down control node PD to the voltage of the fourth voltage terminal VGH through the second clock signal terminal CLKB; And the output signal of the signal output terminal Output of the current stage is pulled down to the voltage of the third voltage terminal VGL. The third stage T3 may be a reset noise reduction stage of the shift register unit.
上述驱动方法可以分别通过与所述第一扫描控制模块相连接的第一信号输入端，以及与所述第二扫描控制模块相连接的第二信号输入端输入的信号对该栅极驱动电路进行正向或反向扫描，从而实现双向扫描。并且，当移位寄存器单元的本级信号输出端需要输出扫描信号时，上拉控制模块可以通过控制上拉控制节点的电位，使得上拉模块导通，将第一时钟信号端输入的信号作为扫描信号通过本级信号输出端输出，以对一行栅线进行扫描。此外，当移位寄存器单元的本级信号输出端不需要输出扫描信号时，所述下拉控制模块能够通过控制下拉控制节点的电位，以对上拉控制节点和本级信号输出端进行下拉，从而可以对上述双向扫描栅极驱动电路进行降噪。In the above driving method, the gate drive circuit can be controlled by signals input from the first signal input terminal connected to the first scan control module and the second signal input terminal connected to the second scan control module. Forward or reverse scanning, thus realizing bi-directional scanning. Moreover, when the signal output terminal of the shift register unit needs to output the scan signal, the pull-up control module can control the potential of the pull-up control node to make the pull-up module turn on, and use the signal input by the first clock signal terminal as The scan signal is output through the signal output terminal of the current stage to scan a row of gate lines. In addition, when the signal output terminal of the current stage of the shift register unit does not need to output the scan signal, the pull-down control module can pull down the pull-up control node and the signal output terminal of the current stage by controlling the potential of the pull-down control node, thereby Noise reduction can be performed on the above bidirectional scanning gate drive circuit.
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the It includes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
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| CN201410429757.2ACN104240765B (en) | 2014-08-28 | 2014-08-28 | Shift register cell and driving method, gate driving circuit and display device |
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| CN201410429757.2ACN104240765B (en) | 2014-08-28 | 2014-08-28 | Shift register cell and driving method, gate driving circuit and display device |
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| CN104240765Atrue CN104240765A (en) | 2014-12-24 |
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| CN201410429757.2AActiveCN104240765B (en) | 2014-08-28 | 2014-08-28 | Shift register cell and driving method, gate driving circuit and display device |
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