技术领域technical field
本发明涉及微电子技术领域，特别涉及一种应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路。The invention relates to the technical field of microelectronics, in particular to a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy acquisition.
背景技术Background technique
无线能量获取技术的关键电路模块包括传感器，接口电路和功率负载电路。而接口电路最重要的部分之一就是AC/DC整流电路。传感器捕获的能量以交流信号的形式输出，无法为功率负载供电，各种不同结构的AC/DC整流电路被用来把交流信号转换为稳定的直流输出。因为AC/DC的效率对整个无线能量获取电路至关重要，所以如何提高电压转换效率，功率转换效率一直是大家研究的方向，同时为了尽可能多地捕获到环境中的能量，如何降低最小的输入电压，提高输入电压的范围也一直是大家研究的方向。The key circuit modules of wireless energy harvesting technology include sensors, interface circuits and power load circuits. One of the most important parts of the interface circuit is the AC/DC rectifier circuit. The energy captured by the sensor is output in the form of an AC signal, which cannot supply power to the power load. Various AC/DC rectifier circuits with different structures are used to convert the AC signal into a stable DC output. Because the efficiency of AC/DC is crucial to the entire wireless energy harvesting circuit, how to improve the voltage conversion efficiency and power conversion efficiency has always been the direction of research. At the same time, in order to capture as much energy as possible in the environment, how to reduce the minimum Input voltage, increasing the range of input voltage has always been the direction of everyone's research.
现有技术方案一：带有栅叉耦合连接方式的桥式整流结构。Solution 1 of the prior art: a bridge rectifier structure with grid fork coupling connection.
利用改进的全桥结构进行AC/DC整流。如图1所示是通用的全桥结构整流电路。M51和M52采用栅叉耦合的连接方式，COMP501和COMP502为比较器，其输出分别控制M53和M54管的栅压，以此实现有源二极管结构。在输入信号Vin的负半周，M51打开，COMP502输出高电平控制M54打开，形成回路给电容C51充电；在输入信号Vin的正半周，M52打开，COMP501输出高电平控制M53打开，形成回路给电容C51充电，电容C51上面产生稳定的直流电压。AC/DC rectification is performed using an improved full-bridge structure. As shown in Figure 1, it is a general-purpose full-bridge rectifier circuit. M51 and M52 are connected by gate fork coupling, and COMP501 and COMP502 are comparators whose outputs respectively control the grid voltage of M53 and M54 , so as to realize the active diode structure. In the negative half cycle of input signal Vin, M51 is turned on, COMP502 outputs high level to control M54 to open, forming a loop to charge capacitor C51 ; in the positive half cycle of input signal Vin, M52 is turned on, COMP501 outputs high level to control M53 Open to form a loop to charge the capacitorC51 , and a stable DC voltage is generated on the capacitorC51 .
这种结构的不足之处是无法实现倍压功能，比较器所需的电源电压高，所以能够正常工作的最低输入电压高，为了降低导通压降，两个栅叉耦合连接方式的MOS管M51和M52尺寸设计通常很大，消耗了大量面积，同时采用了两个比较器，产生了一定的功耗，降低了整流的效率。The disadvantage of this structure is that the voltage doubling function cannot be realized. The power supply voltage required by the comparator is high, so the minimum input voltage that can work normally is high. M51 and M52 are usually large in size and consume a lot of area. Two comparators are used at the same time, which generates a certain amount of power consumption and reduces the efficiency of rectification.
现有技术方案二：NVC负压转换器加上有源二极管两级整流结构。Solution 2 of the prior art: NVC negative voltage converter plus active diode two-stage rectification structure.
利用NVC将交流信号的负半周翻转到正半周，再利用一个有源二极管和负载电容进行AC/DC整流。如图2所示是通用的NVC负压转换器加上单有源二极管两级整流结构。M61、M62、M63和M64构成一个负压转换器，将输入交流信号的负半周翻转到正半周，由于负压转换器中MOS管的接法不具备二极管的截止反相电流的功能，所以后面加上一个比较器COMP601控制的功率管M65，输入给电容C61充电，并且M65作为有源二极管防止电流从电容C61回流。Use NVC to reverse the negative half cycle of the AC signal to the positive half cycle, and then use an active diode and load capacitor for AC/DC rectification. As shown in Figure 2, it is a common NVC negative voltage converter plus a single active diode two-stage rectification structure. M61 , M62 , M63 and M64 form a negative voltage converter, which reverses the negative half cycle of the input AC signal to the positive half cycle, because the connection method of the MOS tube in the negative voltage converter does not have the cut-off reverse current of the diode function, so a power transistor M65 controlled by a comparator COMP601 is added behind, the input charges the capacitor C61 , and M65 acts as an active diode to prevent the current from flowing back from the capacitor C61 .
这种结构的不足之处也是无法实现倍压功能，而且输入到输出有三个MOS管的导通压降，电压转换效率受到影响。而且为了减小NVC的导通压降，通常M61、M62、M63和M64的尺寸很大，这消耗了大量的面积。The disadvantage of this structure is that the voltage doubling function cannot be realized, and there are three conduction voltage drops of MOS transistors from input to output, and the voltage conversion efficiency is affected. Moreover, in order to reduce the turn-on voltage drop of the NVC, the sizes of M61 , M62 , M63 and M64 are generally large, which consumes a lot of area.
发明内容Contents of the invention
本发明的目的在于提供一种应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路，能够在降低最小输入电压的同时提高功率转换效率和电压转换效率，且能够实现整流电路的倍压功能。The purpose of the present invention is to provide a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting, which can improve power conversion efficiency and voltage conversion efficiency while reducing the minimum input voltage, and can realize rectification circuit doubler function.
为了达到上述目的，本发明实施例提供一种应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路，包括：源极输入比较电路、衬底驱动比较电路和偏置电路；其中，In order to achieve the above purpose, an embodiment of the present invention provides a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting, including: a source input comparison circuit, a substrate drive comparison circuit and a bias circuit; in,
所述偏置电路分别为所述源极输入比较电路和所述衬底驱动比较电路提供偏置电压；The bias circuit provides bias voltages for the source input comparison circuit and the substrate drive comparison circuit respectively;
所述源极输入比较电路的同向输入端与第一NMOS管的源极连接并接地，所述源极输入比较电路的反向输入端与所述第一NMOS管的漏极连接，所述源极输入比较电路的输出端与所述第一NMOS管的栅极连接，所述第一NMOS管的衬底接地；The non-inverting input terminal of the source input comparison circuit is connected to the source of the first NMOS transistor and grounded, the inverting input terminal of the source input comparison circuit is connected to the drain of the first NMOS transistor, and the The output terminal of the source input comparison circuit is connected to the gate of the first NMOS transistor, and the substrate of the first NMOS transistor is grounded;
所述衬底驱动比较电路的同向输入端与第一PMOS管的漏极和衬底连接，所述衬底驱动比较电路的反向输入端与所述第一PMOS管的源极连接；所述衬底驱动比较电路的输出端与所述第一PMOS管的栅极连接；The non-inverting input terminal of the substrate driving comparison circuit is connected to the drain of the first PMOS transistor and the substrate, and the inverting input terminal of the substrate driving comparison circuit is connected to the source of the first PMOS transistor; The output terminal of the substrate driving comparison circuit is connected to the gate of the first PMOS transistor;
一交流电压的正极串联一采样电容C1后与所述源极输入比较电路的反向输入端和所述衬底驱动比较电路的反向输入端分别连接，所述交流电压的负极接地；所述衬底驱动比较电路的同向输入端连接一储能电容C2后接地，输出所述储能电容C2两端的整流电压。The positive pole of an AC voltage is connected in series with a sampling capacitorC1 and is respectively connected to the reverse input terminal of the source input comparison circuit and the reverse input terminal of the substrate drive comparison circuit, and the negative pole of the AC voltage is grounded; The non-inverting input end of the substrate driving comparison circuit is connected to an energy storage capacitorC2 and then grounded, and the rectified voltage at both ends of the energy storage capacitorC2 is output.
进一步的，所述偏置电路包括：第二PMOS管M6、第三PMOS管M7、第四PMOS管M8、第五PMOS管M11、第六PMOS管M12、第二NMOS管M9、第三NMOS管M10、第四NMOS管M13以及电阻R1；其中，Further, the bias circuit includes: a second PMOS transistor M6, a third PMOS transistor M7, a fourth PMOS transistor M8, a fifth PMOS transistor M11, a sixth PMOS transistor M12, a second NMOS transistor M9, a third NMOS transistor M10, a fourth NMOS transistor M13 and a resistor R1 ; wherein,
所述第二PMOS管M6的源极和衬底均与所述整流电压Vout连接，所述第二PMOS管M6的栅极与所述第三PMOS管M7的栅极以及所述第四PMOS管M8栅极和漏极连接，所述第三PMOS管M7的源极和衬底均与所述整流电压Vout连接；所述第四PMOS管M8的源极和衬底均与所述整流电压Vout连接，所述第四PMOS管M8的源极和漏极之间输出第一偏置电压VBP；Both the source and the substrate of the second PMOS transistor M6 are connected to the rectified voltage Vout, the gate of the second PMOS transistor M6 is connected to the gate of the third PMOS transistor M7 and the fourth PMOS transistor M8 gate is connected to the drain, the source and substrate of the third PMOS transistor M7 are connected to the rectified voltage Vout; the source and substrate of the fourth PMOS transistor M8 are connected to the rectified voltage Vout connected, the first bias voltage VBP is output between the source and the drain of the fourth PMOS transistor M8;
所述第四PMOS管M8的漏极与所述第三NMOS管M10的漏极连接，所述第三NMOS管M10的源极和衬底接地，所述第三NMOS管M10的栅极与所述第三PMOS管M7的漏极、所述第二NMOS管M9的漏极以及所述第六PMOS管M12的漏极连接形成第二节点B，所述第二NMOS管M9的源极和衬底接地，所述第六PMOS管M12的源极、栅极和衬底均与所述整流电压Vout连接；The drain of the fourth PMOS transistor M8 is connected to the drain of the third NMOS transistor M10, the source and substrate of the third NMOS transistor M10 are grounded, and the gate of the third NMOS transistor M10 is connected to the third NMOS transistor M10. The drain of the third PMOS transistor M7, the drain of the second NMOS transistor M9 and the drain of the sixth PMOS transistor M12 are connected to form a second node B, and the source of the second NMOS transistor M9 and the substrate The bottom is grounded, and the source, gate and substrate of the sixth PMOS transistor M12 are all connected to the rectified voltage Vout;
所述第二NMOS管M9的栅极与所述第四NMOS管M13的栅极、所述第四NMOS管M13的漏极、所述第二PMOS管M6的漏极以及所述第五PMOS管M11的漏极连接形成第一节点A，所述第五PMOS管M11的源极、栅极和衬底均与所述整流电压Vout连接，所述第四NMOS管M13的衬底接地，所述第四NMOS管M13的源极串联所述电阻R1后接地，所述第三NMOS管M10的栅极输出第二偏置电压VBN。The gate of the second NMOS transistor M9, the gate of the fourth NMOS transistor M13, the drain of the fourth NMOS transistor M13, the drain of the second PMOS transistor M6, and the fifth PMOS transistor The drain of M11 is connected to form the first node A, the source, gate and substrate of the fifth PMOS transistor M11 are all connected to the rectified voltage Vout, the substrate of the fourth NMOS transistor M13 is grounded, and The source of the fourth NMOS transistor M13 is connected in series with the resistorR1 and grounded, and the gate of the third NMOS transistor M10 outputs a second bias voltage VBN.
进一步的，所述源极输入比较电路包括：源极输入比较器和正反馈环路；其中，Further, the source input comparison circuit includes: a source input comparator and a positive feedback loop; wherein,
所述正反馈环路输入端与所述源极输入比较器的输出端连接，用于减小所述源极输入比较器的上升下降延时，所述正反馈环路的输出端与所述第一NMOS管M1的栅极连接。The input terminal of the positive feedback loop is connected to the output terminal of the source input comparator for reducing the rise and fall delay of the source input comparator, and the output terminal of the positive feedback loop is connected to the output terminal of the source input comparator. The gate of the first NMOS transistorM1 is connected.
进一步的，所述衬底驱动比较电路包括衬底驱动比较器和正反馈环路；其中，Further, the substrate driving comparison circuit includes a substrate driving comparator and a positive feedback loop; wherein,
所述正反馈环路输入端与所述衬底驱动比较器的输出端连接，用于减小所述衬底驱动比较器的上升下降延时，所述正反馈环路的输出端与所述第一PMOS管M2的栅极连接。The input terminal of the positive feedback loop is connected to the output terminal of the substrate driving comparator for reducing the rising and falling delay of the substrate driving comparator, and the output terminal of the positive feedback loop is connected to the output terminal of the substrate driving comparator. The gate of the first PMOS transistorM2 is connected.
进一步的，所述正反馈环路包括：第一反相器INV1、第二反相器INV2、第三反相器INV3、第四反相器INV4、第五反相器INV5、第六反相器INV6、与非门NAND、或非门NOR、第十四PMOS管M28以及第十二NMOS管M29；其中，Further, the positive feedback loop includes: a first inverter INV1 , a second inverter INV2 , a third inverter INV3 , a fourth inverter INV4 , and a fifth inverter INV5 , the sixth inverter INV6 , the NAND gate NAND, the NOR gate NOR, the fourteenth PMOS transistor M28 and the twelfth NMOS transistor M29; wherein,
输入信号分别与所述与非门NAND的第一输入端和所述或非门NOR的第一输入端连接，所述与非门NAND的输出端依次串联第一反相器INV1和第二反相器INV2后一方面与所述第十四PMOS管M28的栅极连接，另一方面串联所述第六反相器INV6后与所述或非门NOR的第二输入端连接；所述或非门NOR的输出端依次串联第四反相器INV4和第五反相器INV5后一方面与所述第十二NMOS管M29的栅极连接，另一方面串联所述第三反相器INV3后与所述与非门NAND的第二输入端连接；The input signal is respectively connected to the first input end of the NAND gate NAND and the first input end of the NOR gate NOR, and the output end of the NAND gate NAND is connected in series with the first inverter INV1 and the second inverter INV 1 in sequence. On the one hand, the inverter INV2 is connected to the gate of the fourteenth PMOS transistor M28, and on the other hand, the sixth inverter INV6 is connected in series to the second input terminal of the NOR gate NOR; The output terminal of the NOR gate NOR is connected in series with the fourth inverter INV4 and the fifth inverter INV5 in sequence, and on the one hand, it is connected to the gate of the twelfth NMOS transistor M29; The three inverters INV3 are then connected to the second input end of the NAND gate NAND;
所述第十四PMOS管M28的源极和衬底均与所述整流电压Vout连接，所述第十二NMOS管M29的源极和衬底均接地，所述第十四PMOS管M28的漏极和所述第十二NMOS管M29的漏极连接并输出比较电压Vcomp。Both the source and the substrate of the fourteenth PMOS transistor M28 are connected to the rectified voltage Vout, the source and the substrate of the twelfth NMOS transistor M29 are both grounded, and the drain of the fourteenth PMOS transistor M28 and the drain of the twelfth NMOS transistor M29 to output a comparison voltage Vcomp.
进一步的，所述源极输入比较器包括：第七PMOS管M14、第八PMOS管M15、第九PMOS管M18、第十PMOS管M20、第五NMOS管M16、第六NMOS管M17、第七NMOS管M19以及第八NMOS管M21；其中，Further, the source input comparator includes: seventh PMOS transistor M14, eighth PMOS transistor M15, ninth PMOS transistor M18, tenth PMOS transistor M20, fifth NMOS transistor M16, sixth NMOS transistor M17, seventh The NMOS transistor M19 and the eighth NMOS transistor M21; wherein,
所述第五NMOS管M16的源极为所述源极输入比较电路的反向输入端，所述第六NMOS管M17的源极为所述源极输入比较电路的同相输入端；所述第五NMOS管M16的衬底接地，所述第六NMOS管M17的源极和衬底均接地，所述第五NMOS管M16的漏极和栅极连接后一方面与所述第六NMOS管M17的栅极连接，另一方面与所述第七PMOS管M14的漏极连接，所述第七PMOS管M14的源极和衬底均与所述整流电压Vout连接，所述第七PMOS管M14的栅极与所述第八PMOS管M15的栅极连接并接所述第一偏置电压VBP；所述第九PMOS管M18的栅极和所述第十PMOS管M20栅极均接所述第一偏置电压VBP；The source of the fifth NMOS transistor M16 is the inverting input terminal of the source input comparison circuit, the source of the sixth NMOS transistor M17 is the non-inverting input terminal of the source input comparison circuit; the fifth NMOS The substrate of the transistor M16 is grounded, the source and the substrate of the sixth NMOS transistor M17 are both grounded, and the drain and gate of the fifth NMOS transistor M16 are connected to the gate of the sixth NMOS transistor M17 on the one hand. and on the other hand connected to the drain of the seventh PMOS transistor M14, the source and substrate of the seventh PMOS transistor M14 are connected to the rectified voltage Vout, the gate of the seventh PMOS transistor M14 The pole is connected to the gate of the eighth PMOS transistor M15 and connected to the first bias voltage VBP; the gate of the ninth PMOS transistor M18 and the gate of the tenth PMOS transistor M20 are both connected to the first bias voltage VBP. Bias voltage VBP;
所述第八PMOS管M15的源极和衬底均与所述整流电压Vout连接，所述第九PMOS管M18的源极和衬底均与所述整流电压Vout连接，所述第十PMOS管M20的源极和衬底均与所述整流电压Vout连接；所述第八PMOS管M15的漏极与所述第六NMOS管M17的漏极以及所述第七NMOS管M19的栅极连接；所述第九PMOS管M18的漏极与所述第七NMOS管M19的漏极以及所述第八NMOS管M21的栅极连接；所述第七NMOS管M19的源极和衬底均接地，所述第八NMOS管M21的源极和衬底均接地，所述第十PMOS管M20的漏极和所述第八NMOS管M21的漏极连接并输出第一电压作为所述正反馈环路的输入信号。Both the source and the substrate of the eighth PMOS transistor M15 are connected to the rectified voltage Vout, the source and the substrate of the ninth PMOS transistor M18 are connected to the rectified voltage Vout, and the tenth PMOS transistor M18 is connected to the rectified voltage Vout. Both the source and the substrate of M20 are connected to the rectified voltage Vout; the drain of the eighth PMOS transistor M15 is connected to the drain of the sixth NMOS transistor M17 and the gate of the seventh NMOS transistor M19; The drain of the ninth PMOS transistor M18 is connected to the drain of the seventh NMOS transistor M19 and the gate of the eighth NMOS transistor M21; the source and the substrate of the seventh NMOS transistor M19 are grounded, Both the source and the substrate of the eighth NMOS transistor M21 are grounded, the drain of the tenth PMOS transistor M20 is connected to the drain of the eighth NMOS transistor M21 and outputs a first voltage as the positive feedback loop input signal.
进一步的，所述衬底驱动比较器包括：第十一PMOS管M22、第十二PMOS管M23、第十三PMOS管M26、第九NMOS管M24、第十NMOS管M25以及第十一NMOS管M27；其中，Further, the substrate driving comparator includes: an eleventh PMOS transistor M22, a twelfth PMOS transistor M23, a thirteenth PMOS transistor M26, a ninth NMOS transistor M24, a tenth NMOS transistor M25, and an eleventh NMOS transistor M27; where,
所述第十一PMOS管M22的衬底为所述衬底驱动比较电路的反向输入端，所述第十二PMOS管M23的衬底为所述衬底驱动比较电路的同相输入端；所述第十一PMOS管M22的源极和衬底连接并与所述第十二PMOS管M23的源极连接，所述第十一PMOS管M22的漏极和栅极连接后一方面与所述第十二PMOS管M23的栅极连接，另一方面与所述第九NMOS管M24的漏极连接，所述第十二PMOS管M23的衬底与所述整流电压Vout连接，所述第十二PMOS管M23的漏极与所述第十三PMOS管M26的栅极和所述第十NMOS管M25的漏极连接，所述第十三PMOS管M26的源极和衬底均与所述整流电压Vout连接，所述第十NMOS管M25的源极和衬底均接地；The substrate of the eleventh PMOS transistor M22 is the inverting input terminal of the substrate driving comparison circuit, and the substrate of the twelfth PMOS transistor M23 is the non-inverting input terminal of the substrate driving comparison circuit; The source of the eleventh PMOS transistor M22 is connected to the substrate and is connected to the source of the twelfth PMOS transistor M23, and the drain and gate of the eleventh PMOS transistor M22 are connected to the latter on the one hand. The gate of the twelfth PMOS transistor M23 is connected to the drain of the ninth NMOS transistor M24 on the other hand, the substrate of the twelfth PMOS transistor M23 is connected to the rectified voltage Vout, and the tenth The drain of the second PMOS transistor M23 is connected to the gate of the thirteenth PMOS transistor M26 and the drain of the tenth NMOS transistor M25, and the source and substrate of the thirteenth PMOS transistor M26 are connected to the gate of the thirteenth PMOS transistor M26. The rectified voltage Vout is connected, and the source and substrate of the tenth NMOS transistor M25 are grounded;
所述第九NMOS管M24的栅极和所述第十NMOS管M25的栅极连接并接所述第二偏置电压VBN，所述第十一NMOS管M27的栅极与所述第二偏置电压VBN连接，所述第十一NMOS管M27的源极和衬底均接地，所述第十一NMOS管M27的漏极和所述第十三PMOS管M26的漏极连接并输出第二电压作为所述正反馈环路的输入信号。The gate of the ninth NMOS transistor M24 is connected to the gate of the tenth NMOS transistor M25 and connected to the second bias voltage VBN, and the gate of the eleventh NMOS transistor M27 is connected to the second bias voltage VBN. The source and substrate of the eleventh NMOS transistor M27 are connected to the ground, the drain of the eleventh NMOS transistor M27 is connected to the drain of the thirteenth PMOS transistor M26 and outputs the second voltage as the input signal of the positive feedback loop.
本发明的上述技术方案至少具有如下有益效果：The technical solution of the present invention has at least the following beneficial effects:
本发明实施例的应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路中，采用电荷泵结构，输入到输出可以倍压，提高了其驱动后级负载的能力；同时功率管采用基于比较器的有源二级管，且源极输入的共栅比较器和衬底驱动的比较器的运用降低了工作的最小输入电压，提高了输入电压的范围；两个比较器的偏置电路保证各支路的电流不随电源电压的变化而变化，比较器始终被偏置在亚阈值区，降低了控制电路的功耗。In the wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy acquisition in the embodiment of the present invention, a charge pump structure is adopted, and the voltage can be doubled from input to output, which improves its ability to drive the subsequent load; at the same time, the power The tube adopts the active diode based on the comparator, and the use of the source input common gate comparator and the substrate driven comparator reduces the minimum input voltage of the work and improves the range of the input voltage; the two comparators The bias circuit ensures that the current of each branch does not change with the change of the power supply voltage, and the comparator is always biased in the sub-threshold region, which reduces the power consumption of the control circuit.
附图说明Description of drawings
图1表示现有技术中带有栅叉耦合连接方式的桥式整流器的电路图；Fig. 1 shows the circuit diagram of the bridge rectifier with grid fork coupling connection mode in the prior art;
图2表示现有技术中NVC负压转换器加上单有源二极管两级整流器的电路图；Fig. 2 represents the circuit diagram of NVC negative voltage converter plus single active diode two-stage rectifier in the prior art;
图3表示本发明实施例的应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路的主体电路图；Fig. 3 shows the main circuit diagram of a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting according to an embodiment of the present invention;
图4表示本发明实施例的应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路中的偏置电路的电路图；4 shows a circuit diagram of a bias circuit in a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting according to an embodiment of the present invention;
图5表示本发明实施例的应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路中的正反馈环路的电路图；5 shows a circuit diagram of a positive feedback loop in a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting according to an embodiment of the present invention;
图6表示本发明实施例的应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路中的源级输入比较器的电路图；6 shows a circuit diagram of a source-level input comparator in a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting according to an embodiment of the present invention;
图7表示本发明实施例的应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路中的衬底驱动比较器的电路图；7 shows a circuit diagram of a substrate-driven comparator in a wide input range high-efficiency voltage doubler AC/DC rectifier circuit applied to piezoelectric energy harvesting according to an embodiment of the present invention;
图8表示本发明实施例的倍压AC/DC整流器最小启动电压和启动后的最小输入电压仿真图；Fig. 8 shows the minimum start-up voltage of the voltage doubler AC/DC rectifier and the simulation diagram of the minimum input voltage after start-up according to the embodiment of the present invention;
图9表示本发明实施例的倍压AC/DC整流器不同输入电压下的电压转换效率图；Fig. 9 shows the voltage conversion efficiency diagram under different input voltages of the voltage doubler AC/DC rectifier according to the embodiment of the present invention;
图10表示本发明实施例的倍压AC/DC整流器不同输入电压下的功率转换效率图。FIG. 10 shows the power conversion efficiency graph of the voltage doubler AC/DC rectifier according to the embodiment of the present invention under different input voltages.
具体实施方式Detailed ways
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.
本发明针对现有技术中AD/DC整流器无法实现倍压功能，且工作的最低输入电压较高的问题，提供一种应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路中，采用电荷泵结构，输入到输出可以倍压，提高了其驱动后级负载的能力；同时功率管采用基于比较器的有源二级管，且源极输入的共栅比较器和衬底驱动的比较器的运用降低了工作的最小输入电压，提高了输入电压的范围；两个比较器的偏置电路保证各支路的电流不随电源电压的变化而变化，比较器始终被偏置在亚阈值区，降低了控制电路的功耗。Aiming at the problem that the AD/DC rectifier in the prior art cannot realize the voltage doubling function, and the minimum input voltage of the work is relatively high, the present invention provides a wide input range high-efficiency voltage doubling AC/DC rectifier circuit applied to piezoelectric energy acquisition Among them, the charge pump structure is adopted, and the voltage can be doubled from input to output, which improves its ability to drive the post-stage load; at the same time, the power tube adopts an active diode based on a comparator, and the source input common gate comparator and substrate The application of the driven comparator reduces the minimum input voltage and increases the range of input voltage; the bias circuit of the two comparators ensures that the current of each branch does not change with the change of the power supply voltage, and the comparator is always biased at The sub-threshold region reduces the power consumption of the control circuit.
如图3所示，本发明实施例提供一种应用于压电能量获取的宽输入范围高效率倍压AC/DC整流电路，包括：源极输入比较电路COMP1、衬底驱动比较电路COMP2和偏置电路；其中，As shown in Figure 3, the embodiment of the present invention provides a wide input range high-efficiency voltage doubler AC/DC rectifier circuit for piezoelectric energy harvesting, including: source input comparison circuit COMP1, substrate drive comparison circuit COMP2 and bias set the circuit; among them,
所述偏置电路分别为所述源极输入比较电路COMP1和所述衬底驱动比较电路COMP2提供偏置电压；The bias circuit provides bias voltages for the source input comparison circuit COMP1 and the substrate drive comparison circuit COMP2 respectively;
所述源极输入比较电路COMP1的同向输入端与第一NMOS管M1的源极连接并接地，所述源极输入比较电路COMP1的反向输入端与所述第一NMOS管M1的漏极连接，所述源极输入比较电路COMP1的输出端与所述第一NMOS管M1的栅极连接，所述第一NMOS管M1的衬底接地；The non-inverting input terminal of the source input comparison circuit COMP1 is connected to the source of the first NMOS transistorM1 and grounded, and the inverting input terminal of the source input comparison circuit COMP1 is connected to the source of the first NMOS transistorM1. The drain is connected, the output terminal of the source input comparison circuit COMP1 is connected to the gate of the first NMOS transistorM1 , and the substrate of the first NMOS transistorM1 is grounded;
所述衬底驱动比较电路COMP2的同向输入端与第一PMOS管M2的漏极和衬底连接，所述衬底驱动比较电路COMP2的反向输入端与所述第一PMOS管M2的源极连接；所述衬底驱动比较电路的输出端COMP2与所述第一PMOS管M2的栅极连接；The non-inverting input terminal of the substrate drive comparison circuit COMP2 is connected to the drain of the first PMOS transistorM2 and the substrate, and the inverting input terminal of the substrate drive comparison circuit COMP2 is connected to the first PMOS transistorM2 The source is connected; the output terminal COMP2 of the substrate drive comparison circuit is connected to the gate of the first PMOS transistorM2 ;
一交流电压Vin的正极串联一采样电容C1后与所述源极输入比较电路1的反向输入端和所述衬底驱动比较电路COMP2的反向输入端分别连接，所述交流电压Vin的负极接地；所述衬底驱动比较电路COMP2的同向输入端连接一储能电容C2后接地，输出所述储能电容C2两端的整流电压Vout。The anode of an AC voltage Vin is connected in series with a sampling capacitorC1 to the inverting input terminal of the source input comparison circuit 1 and the inverting input terminal of the substrate drive comparison circuit COMP2 respectively, and the AC voltage Vin is The negative pole is grounded; the non-inverting input terminal of the substrate driving comparator circuit COMP2 is connected to an energy storage capacitorC2 and then grounded to output the rectified voltage Vout at both ends of the energy storage capacitorC2 .
本发明上述实施例中，基于比较电路COMP1的MOS管M1、基于比较电路COMP2的MOS管M2可以看成两个理想的二极管，它们和采样电容C1、储能电容C2构成了单级的电荷泵结构AC/DC。具体的，输入交流电压Vin处于负半周时，比较电路COMP1同相端和反向端的输入信号分别是地和负值，所以比较电路COMP1输出为高，打开功率管M1，同理，比较电路COMP2输出为高，关断功率管M2，此时输入Vin对采样电容C1充电至Vin(max)-Vdd，其中Vin(max)为输入信号最大幅值，Vdd为M1的导通压降；输入交流电压Vin处于正半周时，比较电路COMP2同相端和反向端的输入信号分别是地和正值，所以比较电路COMP2输出为低，打开功率管M2，同理，比较电路COMP1输出为低，关断功率管M1，此时输入Vin和采样电容C1上面的电压叠加对储能电容C2充电至Vin(max)-Vdd+Vin(max)-Vdd＝2Vin(max)-2Vdd，对于理想的比较器控制的MOS管，Vdd很小，所以C2上面的直流电压Vout≈2Vin(max)，实现倍压功能。In the above embodiments of the present invention, the MOS transistor M1 based on the comparison circuit COMP1 and the MOS transistor M2 based on the comparison circuit COMP2 can be regarded as two ideal diodes, and they form a single-stage charge pump with the sampling capacitor C1 and the energy storage capacitor C2 Structure AC/DC. Specifically, when the input AC voltage Vin is in the negative half cycle, the input signals of the non-inverting terminal and the negative terminal of the comparison circuit COMP1 are ground and negative values respectively, so the output of the comparison circuit COMP1 is high, and the power transistor M1 is turned on. Similarly, the output of the comparison circuit COMP2 is is high, turn off the power tube M2, at this time, input Vin to charge the sampling capacitor C1 to Vin(max)-Vdd, where Vin(max) is the maximum amplitude of the input signal, and Vdd is the conduction voltage drop of M1; the input AC voltage When Vin is in the positive half cycle, the input signals of the non-inverting terminal and the negative terminal of the comparison circuit COMP2 are ground and positive values respectively, so the output of the comparison circuit COMP2 is low, and the power transistor M2 is turned on. Similarly, the output of the comparison circuit COMP1 is low, and the power is turned off. Tube M1, at this time, the input Vin and the voltage above the sampling capacitor C1 are superimposed to charge the energy storage capacitor C2 to Vin(max)-Vdd+Vin(max)-Vdd=2Vin(max)-2Vdd, for an ideal comparator control MOS tube, Vdd is very small, so the DC voltage Vout on C2 ≈ 2Vin(max), realizing the voltage doubling function.
本发明上述实施例中，如图4所示，所述偏置电路包括：第二PMOS管M6、第三PMOS管M7、第四PMOS管M8、第五PMOS管M11、第六PMOS管M12、第二NMOS管M9、第三NMOS管M10、第四NMOS管M13以及电阻R1；其中，In the above embodiment of the present invention, as shown in FIG. 4 , the bias circuit includes: a second PMOS transistor M6, a third PMOS transistor M7, a fourth PMOS transistor M8, a fifth PMOS transistor M11, a sixth PMOS transistor M12, The second NMOS transistor M9, the third NMOS transistor M10, the fourth NMOS transistor M13 and the resistorR1 ; wherein,
所述第二PMOS管M6的源极和衬底均与所述整流电压Vout连接，所述第二PMOS管M6的栅极与所述第三PMOS管M7的栅极以及所述第四PMOS管M8栅极和漏极连接，所述第三PMOS管M7的源极和衬底均与所述整流电压Vout连接；所述第四PMOS管M8的源极和衬底均与所述整流电压Vout连接，所述第四PMOS管M8的源极和漏极之间输出第一偏置电压VBP；Both the source and the substrate of the second PMOS transistor M6 are connected to the rectified voltage Vout, the gate of the second PMOS transistor M6 is connected to the gate of the third PMOS transistor M7 and the fourth PMOS transistor M8 gate is connected to the drain, the source and substrate of the third PMOS transistor M7 are connected to the rectified voltage Vout; the source and substrate of the fourth PMOS transistor M8 are connected to the rectified voltage Vout connected, the first bias voltage VBP is output between the source and the drain of the fourth PMOS transistor M8;
所述第四PMOS管M8的漏极与所述第三NMOS管M10的漏极连接，所述第三NMOS管M10的源极和衬底接地，所述第三NMOS管M10的栅极与所述第三PMOS管M7的漏极、所述第二NMOS管M9的漏极以及所述第六PMOS管M12的漏极连接形成第二节点B，所述第二NMOS管M9的源极和衬底接地，所述第六PMOS管M12的源极、栅极和衬底均与所述整流电压Vout连接；The drain of the fourth PMOS transistor M8 is connected to the drain of the third NMOS transistor M10, the source and substrate of the third NMOS transistor M10 are grounded, and the gate of the third NMOS transistor M10 is connected to the third NMOS transistor M10. The drain of the third PMOS transistor M7, the drain of the second NMOS transistor M9 and the drain of the sixth PMOS transistor M12 are connected to form a second node B, and the source of the second NMOS transistor M9 and the substrate The bottom is grounded, and the source, gate and substrate of the sixth PMOS transistor M12 are all connected to the rectified voltage Vout;
所述第二NMOS管M9的栅极与所述第四NMOS管M13的栅极、所述第四NMOS管M13的漏极、所述第二PMOS管M6的漏极以及所述第五PMOS管M11的漏极连接形成第一节点A，所述第五PMOS管M11的源极、栅极和衬底均与所述整流电压Vout连接，所述第四NMOS管M13的衬底接地，所述第四NMOS管M13的源极串联所述电阻R1后接地，所述第三NMOS管M10的栅极输出第二偏置电压VBN。The gate of the second NMOS transistor M9, the gate of the fourth NMOS transistor M13, the drain of the fourth NMOS transistor M13, the drain of the second PMOS transistor M6, and the fifth PMOS transistor The drain of M11 is connected to form the first node A, the source, gate and substrate of the fifth PMOS transistor M11 are all connected to the rectified voltage Vout, the substrate of the fourth NMOS transistor M13 is grounded, and The source of the fourth NMOS transistor M13 is connected in series with the resistorR1 and grounded, and the gate of the third NMOS transistor M10 outputs a second bias voltage VBN.
本发明具体实施例中，M6、M7、M8、M9和M10构成负反馈电路，将各个支路的电流稳定在一个定值，不随电源电压的变化而变化。M11和M12为启动电路，在启动阶段分别利用M11、M12的体漏二极管电流给第一节点A和第二节点B充电，帮助电路启动。In the specific embodiment of the present invention, M6, M7, M8, M9 and M10 form a negative feedback circuit, which stabilizes the current of each branch at a fixed value, which does not change with the change of the power supply voltage. M11 and M12 are start-up circuits. In the start-up phase, the body-drain diode currents of M11 and M12 are used to charge the first node A and the second node B to help the circuit start up.
具体的，M6、M7和M8形成电流镜，它们的宽长比被设置为一样，所以其漏电流相等。M6-M10形成了一个负反馈环路，保证流经电阻R1的电流不变，假如R1的电流发生变化，负反馈环会抵消这种变化，从而保证各个支路的电流保持不变，因此输出第一偏置电压VBP，VBN的值总是保持稳定不变。负反馈环形成过程：若整流电压Vout增大导致流经R1的电流增大，则A点电压即M9栅压升高，所以B点电压即M10栅压下降，进而M8漏电压上升，即M6栅压上升，M6漏电流下降，则A点电压下降。该负反馈环路保证各个支路电流不随整流电压Vout变化而变化。M11和M12为启动电路，在启动阶段分别利用M11、M12的体漏二极管电流给A点和B点充电，帮助电路启动。偏置电路在R1上面添加了一个MOS管M13，这可以有效减小R1两端的压降且为了降低功耗，每一个支路的偏置电流值为十几nA，添加M13之后，采用更小的R1就可以实现较小的电流值，减小了电路的面积。Specifically, M6, M7 and M8 form a current mirror, and their aspect ratios are set to be the same, so their leakage currents are equal. M6-M10 forms a negative feedback loop to ensure that the current flowing through the resistorR1 remains unchanged. If the current ofR1 changes, the negative feedback loop will offset this change, thereby ensuring that the current of each branch remains unchanged. Therefore, the value of outputting the first bias voltage VBP, VBN is always kept stable. Negative feedback loop formation process: If the rectified voltage Vout increases and the current flowing throughR1 increases, the voltage at point A, that is, the gate voltage of M9, increases, so the voltage at point B, that is, the gate voltage of M10, decreases, and then the drain voltage of M8 increases, that is The gate voltage of M6 rises, the leakage current of M6 drops, and the voltage of point A drops. The negative feedback loop ensures that the current of each branch does not change with the change of the rectified voltage Vout. M11 and M12 are start-up circuits. In the start-up phase, the body-drain diode currents of M11 and M12 are used to charge point A and point B respectively to help the circuit start. The bias circuit adds a MOS transistor M13 on R1 , which can effectively reduce the voltage drop across R1 and in order to reduce power consumption, the bias current value of each branch is more than ten nA. After adding M13, use A smallerR1 can achieve a smaller current value, reducing the area of the circuit.
具体的，本发明上述实施例中，如图6所示，所述源极输入比较电路COMP1包括：源极输入比较器和正反馈环路Feedback Block；其中，Specifically, in the above-mentioned embodiment of the present invention, as shown in FIG. 6, the source input comparison circuit COMP1 includes: a source input comparator and a positive feedback loop Feedback Block; wherein,
所述正反馈环路Feedback Block输入端与所述源极输入比较器的输出端连接，用于减小所述源极输入比较器的上升下降延时，所述正反馈环路FeedbackBlock的输出端与所述第一NMOS管M1的栅极连接。The input terminal of the positive feedback loop Feedback Block is connected to the output terminal of the source input comparator for reducing the rising and falling delay of the source input comparator, and the output terminal of the positive feedback loop FeedbackBlock It is connected with the gate of the first NMOS transistorM1 .
进一步的，如图7所示，所述衬底驱动比较电路包括衬底驱动比较器和正反馈环路Feedback Block；其中，Further, as shown in FIG. 7, the substrate drive comparison circuit includes a substrate drive comparator and a positive feedback loop Feedback Block; wherein,
所述正反馈环路Feedback Block输入端与所述衬底驱动比较器的输出端连接，用于减小所述衬底驱动比较器的上升下降延时，所述正反馈环路FeedbackBlock的输出端与所述第一PMOS管M2的栅极连接。The input terminal of the positive feedback loop Feedback Block is connected to the output terminal of the substrate driving comparator for reducing the rising and falling delay of the substrate driving comparator, and the output terminal of the positive feedback loop Feedback Block It is connected with the gate of the first PMOS transistorM2 .
具体的，如图5所示，所述正反馈环路Feedback Block包括：第一反相器INV1、第二反相器INV2、第三反相器INV3、第四反相器INV4、第五反相器INV5、第六反相器INV6、与非门NAND、或非门NOR、第十四PMOS管M28以及第十二NMOS管M29；其中，Specifically, as shown in FIG. 5 , the positive feedback loop Feedback Block includes: a first inverter INV1 , a second inverter INV2 , a third inverter INV3 , and a fourth inverter INV4 , the fifth inverter INV5 , the sixth inverter INV6 , the NAND gate NAND, the NOR gate NOR, the fourteenth PMOS transistor M28 and the twelfth NMOS transistor M29; wherein,
输入信号分别与所述与非门NAND的第一输入端和所述或非门NOR的第一输入端连接，所述与非门NAND的输出端依次串联第一反相器INV1和第二反相器INV2后一方面与所述第十四PMOS管M28的栅极连接，另一方面串联所述第六反相器INV6后与所述或非门NOR的第二输入端连接；所述或非门NOR的输出端依次串联第四反相器INV4和第五反相器INV5后一方面与所述第十二NMOS管M29的栅极连接，另一方面串联所述第三反相器INV3后与所述与非门NAND的第二输入端连接；The input signal is respectively connected to the first input end of the NAND gate NAND and the first input end of the NOR gate NOR, and the output end of the NAND gate NAND is connected in series with the first inverter INV1 and the second inverter INV 1 in sequence. On the one hand, the inverter INV2 is connected to the gate of the fourteenth PMOS transistor M28, and on the other hand, the sixth inverter INV6 is connected in series to the second input terminal of the NOR gate NOR; The output terminal of the NOR gate NOR is connected in series with the fourth inverter INV4 and the fifth inverter INV5 in sequence, and on the one hand, it is connected to the gate of the twelfth NMOS transistor M29; The three inverters INV3 are then connected to the second input end of the NAND gate NAND;
所述第十四PMOS管M28的源极和衬底均与所述整流电压Vout连接，所述第十二NMOS管M29的源极和衬底均接地，所述第十四PMOS管M28的漏极和所述第十二NMOS管M29的漏极连接并输出比较电压Vcomp。Both the source and the substrate of the fourteenth PMOS transistor M28 are connected to the rectified voltage Vout, the source and the substrate of the twelfth NMOS transistor M29 are both grounded, and the drain of the fourteenth PMOS transistor M28 and the drain of the twelfth NMOS transistor M29 to output a comparison voltage Vcomp.
本发明上述实施例中，V2为该电路的输入信号，Vcomp为输出端，输入信号V2经过上面支路与非门和两级反相器之后在C点的信号被反相之后反馈到下面支路或非门的输入端，同样，下面支路D点处的信号被反馈到上面支路或非门的输入端，由此构成了正反馈环路，加快了信号V2的翻转速度。In the above-mentioned embodiment of the present invention, V2 is the input signal of the circuit, Vcomp is the output terminal, and the input signal V2 is fed back to the lower branch after the signal at point C is inverted after passing through the upper branch NAND gate and the two-stage inverter. Similarly, the signal at point D of the lower branch is fed back to the input of the upper branch NOR gate, thereby forming a positive feedback loop and speeding up the inversion speed of the signal V2.
若V2为高电平，则或非门NOR输出低电平，D点输出低，D处信号反馈到与非门MAND输入，则C点输出也为低电平，这完全打开了M28，关断M29，反馈输出被拉至电源电压Vout。若V1为低电平，同理，完全关断M28，打开M29，输出被拉至地。该电路通过反馈使M28和M29栅极上面的信号完全相同而且只有0和Vout两种状态，这大大提高了摆幅，降低了信号上升下降的延时。If V2 is high level, the NOR gate output is low level, the output at point D is low, and the signal at D is fed back to the input of the NAND gate MAND, then the output at point C is also low level, which completely opens M28 and turns off Turn off M29, the feedback output is pulled to the power supply voltage Vout. If V1 is at low level, similarly, M28 is completely turned off, M29 is turned on, and the output is pulled to ground. The circuit uses feedback to make the signals on the gates of M28 and M29 exactly the same and only have two states of 0 and Vout, which greatly improves the swing amplitude and reduces the delay of signal rise and fall.
本发明上述实施例中，如图6所示，所述源极输入比较器包括：第七PMOS管M14、第八PMOS管M15、第九PMOS管M18、第十PMOS管M20、第五NMOS管M16、第六NMOS管M17、第七NMOS管M19以及第八NMOS管M21；其中，In the above embodiment of the present invention, as shown in FIG. 6, the source input comparator includes: a seventh PMOS transistor M14, an eighth PMOS transistor M15, a ninth PMOS transistor M18, a tenth PMOS transistor M20, a fifth NMOS transistor M16, the sixth NMOS transistor M17, the seventh NMOS transistor M19, and the eighth NMOS transistor M21; wherein,
所述第五NMOS管M16的源极为所述源极输入比较电路的反向输入端，所述第六NMOS管M17的源极为所述源极输入比较电路的同相输入端；所述第五NMOS管M16的衬底接地，所述第六NMOS管M17的源极和衬底均接地，所述第五NMOS管M16的漏极和栅极连接后一方面与所述第六NMOS管M17的栅极连接，另一方面与所述第七PMOS管M14的漏极连接，所述第七PMOS管M14的源极和衬底均与所述整流电压Vout连接，所述第七PMOS管M14的栅极与所述第八PMOS管M15的栅极连接并接所述第一偏置电压VBP；所述第九PMOS管M18的栅极和所述第十PMOS管M20栅极均接所述第一偏置电压VBP；The source of the fifth NMOS transistor M16 is the inverting input terminal of the source input comparison circuit, the source of the sixth NMOS transistor M17 is the non-inverting input terminal of the source input comparison circuit; the fifth NMOS The substrate of the transistor M16 is grounded, the source and the substrate of the sixth NMOS transistor M17 are both grounded, and the drain and gate of the fifth NMOS transistor M16 are connected to the gate of the sixth NMOS transistor M17 on the one hand. and on the other hand connected to the drain of the seventh PMOS transistor M14, the source and substrate of the seventh PMOS transistor M14 are connected to the rectified voltage Vout, the gate of the seventh PMOS transistor M14 The pole is connected to the gate of the eighth PMOS transistor M15 and connected to the first bias voltage VBP; the gate of the ninth PMOS transistor M18 and the gate of the tenth PMOS transistor M20 are both connected to the first bias voltage VBP. Bias voltage VBP;
所述第八PMOS管M15的源极和衬底均与所述整流电压Vout连接，所述第九PMOS管M18的源极和衬底均与所述整流电压Vout连接，所述第十PMOS管M20的源极和衬底均与所述整流电压Vout连接；所述第八PMOS管M15的漏极与所述第六NMOS管M17的漏极以及所述第七NMOS管M19的栅极连接；所述第九PMOS管M18的漏极与所述第七NMOS管M19的漏极以及所述第八NMOS管M21的栅极连接；所述第七NMOS管M19的源极和衬底均接地，所述第八NMOS管M21的源极和衬底均接地，所述第十PMOS管M20的漏极和所述第八NMOS管M21的漏极连接并输出第一电压作为所述正反馈环路的输入信号。Both the source and the substrate of the eighth PMOS transistor M15 are connected to the rectified voltage Vout, the source and the substrate of the ninth PMOS transistor M18 are connected to the rectified voltage Vout, and the tenth PMOS transistor M18 is connected to the rectified voltage Vout. Both the source and the substrate of M20 are connected to the rectified voltage Vout; the drain of the eighth PMOS transistor M15 is connected to the drain of the sixth NMOS transistor M17 and the gate of the seventh NMOS transistor M19; The drain of the ninth PMOS transistor M18 is connected to the drain of the seventh NMOS transistor M19 and the gate of the eighth NMOS transistor M21; the source and the substrate of the seventh NMOS transistor M19 are grounded, Both the source and the substrate of the eighth NMOS transistor M21 are grounded, the drain of the tenth PMOS transistor M20 is connected to the drain of the eighth NMOS transistor M21 and outputs a first voltage as the positive feedback loop input signal.
本发明具体实施例中，M16和M17为输入管，输入信号从反向输入端M16和同相输入端M17的源级输入，M14和M15为偏置电流源负载，偏置电路提供稳定的栅压VBP将M16和M17偏置在亚阈值区。M18和M19、M20和M21为两级电流源反相器，增大输出的驱动能力，优化输出波形。In a specific embodiment of the present invention, M16 and M17 are input tubes, the input signal is input from the source level of the inverting input terminal M16 and the non-inverting input terminal M17, M14 and M15 are bias current source loads, and the bias circuit provides a stable grid voltage VBP biases M16 and M17 in the subthreshold region. M18 and M19, M20 and M21 are two-stage current source inverters, which increase the driving capability of the output and optimize the output waveform.
具体的，M16和M17为输入管，M14和M15连接方式为一对电流镜，作为偏置电流源，为了降低功耗，偏置电路提供稳定的栅压VBP将M16和M17偏置在亚阈值区。M17的源级接地，M16的源级接功率管M1的漏极V1，即将V1和地信号进行比较。若V1从0开始上升，因为M14和M15电流镜提供的偏置电流稳定不变，所以M16的栅极和漏极也就是M17的栅极电压增大，进而M17的漏极也就是E点处电压下降，经过M18和M19、M20和M21构成的两级电流源反相器之后输出低电平；若V1从0开始下降，同理，输出高电平。Specifically, M16 and M17 are input tubes, M14 and M15 are connected as a pair of current mirrors, as a bias current source, in order to reduce power consumption, the bias circuit provides a stable gate voltage VBP to bias M16 and M17 at the sub-threshold district. The source of M17 is grounded, and the source of M16 is connected to the drain V1 of the power transistor M1, that is, to compare V1 with the ground signal. If V1 starts to rise from 0, because the bias current provided by the M14 and M15 current mirrors is stable, the gate and drain of M16, that is, the gate voltage of M17, increases, and then the drain of M17 is at point E. When the voltage drops, it will output a low level after passing through the two-stage current source inverter composed of M18 and M19, M20 and M21; if V1 starts to drop from 0, it will output a high level in the same way.
本发明上述实施例中，如图7所示，所述衬底驱动比较器包括：第十一PMOS管M22、第十二PMOS管M23、第十三PMOS管M26、第九NMOS管M24、第十NMOS管M25以及第十一NMOS管M27；其中，In the above embodiment of the present invention, as shown in FIG. 7, the substrate driving comparator includes: an eleventh PMOS transistor M22, a twelfth PMOS transistor M23, a thirteenth PMOS transistor M26, a ninth NMOS transistor M24, a Ten NMOS tubes M25 and eleventh NMOS tubes M27; wherein,
所述第十一PMOS管M22的衬底为所述衬底驱动比较电路的反向输入端，所述第十二PMOS管M23的衬底为所述衬底驱动比较电路的同相输入端；所述第十一PMOS管M22的源极和衬底连接并与所述第十二PMOS管M23的源极连接，所述第十一PMOS管M22的漏极和栅极连接后一方面与所述第十二PMOS管M23的栅极连接，另一方面与所述第九NMOS管M24的漏极连接，所述第十二PMOS管M23的衬底与所述整流电压Vout连接，所述第十二PMOS管M23的漏极与所述第十三PMOS管M26的栅极和所述第十NMOS管M25的漏极连接，所述第十三PMOS管M26的源极和衬底均与所述整流电压Vout连接，所述第十NMOS管M25的源极和衬底均接地；The substrate of the eleventh PMOS transistor M22 is the inverting input terminal of the substrate driving comparison circuit, and the substrate of the twelfth PMOS transistor M23 is the non-inverting input terminal of the substrate driving comparison circuit; The source of the eleventh PMOS transistor M22 is connected to the substrate and is connected to the source of the twelfth PMOS transistor M23, and the drain and gate of the eleventh PMOS transistor M22 are connected to the latter on the one hand. The gate of the twelfth PMOS transistor M23 is connected to the drain of the ninth NMOS transistor M24 on the other hand, the substrate of the twelfth PMOS transistor M23 is connected to the rectified voltage Vout, and the tenth The drain of the second PMOS transistor M23 is connected to the gate of the thirteenth PMOS transistor M26 and the drain of the tenth NMOS transistor M25, and the source and substrate of the thirteenth PMOS transistor M26 are connected to the gate of the thirteenth PMOS transistor M26. The rectified voltage Vout is connected, and the source and substrate of the tenth NMOS transistor M25 are grounded;
所述第九NMOS管M24的栅极和所述第十NMOS管M25的栅极连接并接所述第二偏置电压VBN，所述第十一NMOS管M27的栅极与所述第二偏置电压VBN连接，所述第十一NMOS管M27的源极和衬底均接地，所述第十一NMOS管M27的漏极和所述第十三PMOS管M26的漏极连接并输出第二电压作为所述正反馈环路的输入信号。The gate of the ninth NMOS transistor M24 is connected to the gate of the tenth NMOS transistor M25 and connected to the second bias voltage VBN, and the gate of the eleventh NMOS transistor M27 is connected to the second bias voltage VBN. The source and substrate of the eleventh NMOS transistor M27 are connected to the ground, the drain of the eleventh NMOS transistor M27 is connected to the drain of the thirteenth PMOS transistor M26 and outputs the second voltage as the input signal of the positive feedback loop.
本发明上述实施例中，M22和M23为比较器的输入管，输入信号从反向输入端M22和同相输入端M23的衬底输入，M24和M25为偏置电流源负载，偏置电路提供稳定的栅压VBN将M24和M25偏置在亚阈值区。两个输入管的源级和采样电容C1的一端相连。M20、M21为一级电流源反相器，增大输出的驱动能力。In the above embodiments of the present invention, M22 and M23 are the input tubes of the comparator, the input signal is input from the substrate of the inverting input terminal M22 and the non-inverting input terminal M23, M24 and M25 are bias current source loads, and the bias circuit provides stable A gate voltage of VBN biases M24 and M25 in the subthreshold region. The source stages of the two input tubes are connected to one end of the sampling capacitor C1. M20 and M21 are primary current source inverters, which increase the driving capability of the output.
M22和M23为比较器的输入管，输入信号从M22和M23的衬底输入，M24和M25为电流镜连接方式，作为偏置电流源，为了降低功耗，偏置电路提供稳定的栅压VBN将M24和M25偏置在亚阈值区。对于输入管M22和M23，采用了衬底驱动技术，其阈值电压和衬底电压的关系为：M22 and M23 are the input tubes of the comparator, the input signal is input from the substrate of M22 and M23, M24 and M25 are connected by current mirror, as a bias current source, in order to reduce power consumption, the bias circuit provides a stable grid voltage VBN Bias M24 and M25 in the subthreshold region. For the input transistors M22 and M23, the substrate driving technology is adopted, and the relationship between the threshold voltage and the substrate voltage is:
其中γ、ΦF、VBS分别为体效应系数，衬底表面势和源衬电压，可以看出VBS会影响阈值电压Vth，从而影响漏电流。若给定栅源电压VGS，在亚阈值区，漏电流和VSB的关系为：Among them, γ, ΦF , and VBS are the body effect coefficient, the substrate surface potential, and the source-to-substrate voltage, respectively. It can be seen that VBS will affect the threshold voltage Vth, thereby affecting the leakage current. If the gate-source voltage VGS is given, in the subthreshold region, the relationship between the leakage current and VSB is:
也就是说源衬电压VBS可以控制漏电流，而且VBS很小就可以调制沟道电流，这避免了阈值电压对最小输入信号的限制。输入管M22和M23的衬底分别和V1和Vout相连，若V1从Vout的值开始减小，因为M24和M25电流镜提供的偏置电流稳定不变，所以M22的栅极和漏极也就是M23的栅极电压增大，进而M23的漏极也就是F点处电压下降，经过M26和M27构成的电流源反相器之后输出高电平；若V1从Vout的值开始增大，同理，输出低电平。该比较器输入管的源级连接M1管漏极，采用V1点电压供电，此处电压为交流信号，当交流信号幅度比较小不足以提供该比较器的电源电压时，比较器是关闭的，而恰好此时不需要比较功能，这可以降低比较器的功耗。That is to say, the source-to-substrate voltage VBS can control the leakage current, and the channel current can be modulated when the VBS is very small, which avoids the limitation of the threshold voltage on the minimum input signal. The substrates of input transistors M22 and M23 are respectively connected to V1 and Vout. If V1 starts to decrease from the value of Vout, because the bias current provided by the M24 and M25 current mirrors is stable, so the gate and drain of M22 are The gate voltage of M23 increases, and then the drain of M23, which is the voltage at point F, drops, and outputs a high level after passing through the current source inverter composed of M26 and M27; if V1 starts to increase from the value of Vout, the same reason , the output is low. The source of the input tube of the comparator is connected to the drain of the M1 tube, and the voltage at point V1 is used for power supply. The voltage here is an AC signal. When the amplitude of the AC signal is too small to provide the power supply voltage of the comparator, the comparator is turned off. And it happens that the comparison function is not needed at this time, which can reduce the power consumption of the comparator.
本发明实施例的AC/DC整流器采用了电荷泵结构，输入到输出可以倍压，提高了其驱动后级负载的能力；本发明实施例中控制功率MOS管栅极电压的比较器分别采用了源级输入和衬底驱动技术，可以降低最小输入电压，提高输入电压的范围；本发明实施例中比较器的偏置电路采用了负反馈的结构，保证各支路电流不随电源电压的变化而变化，同时两个比较器均被偏置在亚阈值区，这可以降低控制电路的功耗；本发明实施例中衬底驱动的比较器使用采样电容处的交流信号供电，在不需要比较器工作的时候周期性的关闭，减小功耗，提高效率；本发明实施例的比较器输出端接了一级正反馈环路电路，提高比较器的速度，增大输出摆幅，提高整个AC/DC整流的效率；本发明实施例中包括源级输入比较电路、偏置电路、正反馈电路在内的控制电路都是由本AC/DC整流器的DC输出供电，不需要外界电源供电。The AC/DC rectifier of the embodiment of the present invention adopts a charge pump structure, which can double the voltage from input to output, which improves its ability to drive the load of the latter stage; Source-level input and substrate drive technology can reduce the minimum input voltage and increase the range of input voltage; the bias circuit of the comparator in the embodiment of the present invention adopts a negative feedback structure to ensure that the current of each branch does not change with the change of the power supply voltage. change, and both comparators are biased in the sub-threshold region, which can reduce the power consumption of the control circuit; When working, it is periodically closed to reduce power consumption and improve efficiency; the output terminal of the comparator in the embodiment of the present invention is connected with a first-stage positive feedback loop circuit to improve the speed of the comparator, increase the output swing, and improve the overall AC /DC rectification efficiency; in the embodiment of the present invention, the control circuit including the source-level input comparison circuit, bias circuit, and positive feedback circuit is powered by the DC output of the AC/DC rectifier without external power supply.
本发明倍压AC/DC整流器的主要仿真结果如下：The main simulation results of the voltage doubler AC/DC rectifier of the present invention are as follows:
如图8所示是本AC/DC整流器的输出电压瞬态仿真，可以看出最小启动电压为200mV，电路启动之后输入电压可以降到140mV，此时电压转换效率达到80％，功率转换效率达到78％；如图9所示是本AC/DC整流器不同输入电压下的电压转换效率图，最大电压转换效率可以达到97.85％；如图10所示是本AC/DC整流器不同输入电压下的功率转换效率图，最大功率转换效率可以达到94.4％。As shown in Figure 8, the output voltage transient simulation of this AC/DC rectifier, it can be seen that the minimum starting voltage is 200mV, and the input voltage can be reduced to 140mV after the circuit is started. At this time, the voltage conversion efficiency reaches 80%, and the power conversion efficiency reaches 78%; as shown in Figure 9 is the voltage conversion efficiency diagram of the AC/DC rectifier under different input voltages, the maximum voltage conversion efficiency can reach 97.85%; as shown in Figure 10 is the power of the AC/DC rectifier under different input voltages Conversion efficiency diagram, the maximum power conversion efficiency can reach 94.4%.
如表1所示，给出了本发明实施例提供的AC/DC整流电路不同输入电压下对应输出电压，可以看出其倍压的功能。As shown in Table 1, the corresponding output voltages of the AC/DC rectifier circuit provided by the embodiment of the present invention under different input voltages are given, and its voltage doubling function can be seen.
表1，AC/DC整流电路不同输入电压下对应输出电压Table 1, AC/DC rectifier circuit corresponding output voltage under different input voltages
通过以上的设计和仿真结果测试，本发明实施例提供的AC/DC整流电路实现了宽输入范围、高电压转换效率、高功率转换效率和倍压的功能和特性。Through the above design and simulation result test, the AC/DC rectifier circuit provided by the embodiment of the present invention realizes the functions and characteristics of wide input range, high voltage conversion efficiency, high power conversion efficiency and voltage doubling.
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, these improvements and modifications It should also be regarded as the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN201410468355.3ACN104201915B (en) | 2014-09-15 | 2014-09-15 | Wide-input range, efficient and voltage-multiplying AC/DC (alternating current/direct current) rectifying circuit applied to piezoelectric energy gaining |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410468355.3ACN104201915B (en) | 2014-09-15 | 2014-09-15 | Wide-input range, efficient and voltage-multiplying AC/DC (alternating current/direct current) rectifying circuit applied to piezoelectric energy gaining |
| Publication Number | Publication Date |
|---|---|
| CN104201915Atrue CN104201915A (en) | 2014-12-10 |
| CN104201915B CN104201915B (en) | 2017-03-22 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410468355.3AExpired - Fee RelatedCN104201915B (en) | 2014-09-15 | 2014-09-15 | Wide-input range, efficient and voltage-multiplying AC/DC (alternating current/direct current) rectifying circuit applied to piezoelectric energy gaining |
| Country | Link |
|---|---|
| CN (1) | CN104201915B (en) |
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| CN105007046A (en)* | 2015-07-21 | 2015-10-28 | 清华大学 | Extra-low voltage continuous time auto-zero nava power consumption transconductance amplifier |
| CN105006983A (en)* | 2015-08-04 | 2015-10-28 | 重庆大学 | Rectifier circuit for piezoelectric energy collectors |
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| CN111431421A (en)* | 2020-04-21 | 2020-07-17 | 深圳技术大学 | A high-efficiency implantable full-wave rectifier circuit |
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| CN1841226A (en)* | 2005-03-31 | 2006-10-04 | 佳能株式会社 | Power supply device and image forming apparatus having the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050285728A1 (en)* | 2004-06-29 | 2005-12-29 | Tyndall Patrick A | Power conversion from piezoelectric source |
| CN1841226A (en)* | 2005-03-31 | 2006-10-04 | 佳能株式会社 | Power supply device and image forming apparatus having the same |
| CN1963844A (en)* | 2006-11-30 | 2007-05-16 | 上海坤锐电子科技有限公司 | Self-offset high efficiency rectification circuit used for RF electron tag |
| CN103269173A (en)* | 2013-05-21 | 2013-08-28 | 杭州电子科技大学 | An Active Voltage Doubler Rectifier Circuit |
| CN103280996A (en)* | 2013-06-28 | 2013-09-04 | 上海坤锐电子科技有限公司 | Rectifying circuit of multi-charge-pump structure |
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| CN105007046B (en)* | 2015-07-21 | 2018-11-13 | 清华大学 | Extremely low voltage continuous time from zeroing nanowatt power consumption trsanscondutance amplifier |
| CN105007046A (en)* | 2015-07-21 | 2015-10-28 | 清华大学 | Extra-low voltage continuous time auto-zero nava power consumption transconductance amplifier |
| CN105006983A (en)* | 2015-08-04 | 2015-10-28 | 重庆大学 | Rectifier circuit for piezoelectric energy collectors |
| CN105006983B (en)* | 2015-08-04 | 2019-04-02 | 重庆大学 | A kind of rectification circuit for piezoelectric energy collector |
| CN105897012A (en)* | 2016-05-12 | 2016-08-24 | 西安电子科技大学 | Double-period conversion circuit for energy acquisition |
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| CN106209064A (en)* | 2016-07-07 | 2016-12-07 | 西安电子科技大学 | Low-power consumption dynamic threshold comparator interface circuit and commutator, wireless senser |
| CN106209064B (en)* | 2016-07-07 | 2019-05-07 | 西安电子科技大学 | Low-power dynamic threshold comparator interface circuit and rectifier, wireless sensor |
| CN106100293B (en)* | 2016-08-24 | 2018-10-09 | 西安电子科技大学 | current detection circuit and piezoelectric rectifier applied to piezoelectric rectifier |
| CN106100293A (en)* | 2016-08-24 | 2016-11-09 | 西安电子科技大学 | It is applied to current detection circuit and the piezoelectric rectifier of piezoelectric rectifier |
| CN107425742A (en)* | 2017-08-02 | 2017-12-01 | 宁波大学 | A kind of rectification circuit for energy harvesting |
| CN107612390A (en)* | 2017-10-13 | 2018-01-19 | 郑州云海信息技术有限公司 | An Active Rectifier Circuit |
| CN110545047A (en)* | 2019-10-17 | 2019-12-06 | 无锡麟力科技有限公司 | Small-power on-chip rectifier bridge circuit |
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| CN111200361A (en)* | 2020-03-03 | 2020-05-26 | 桂林电子科技大学 | A self-powered dual-input dual-output energy harvesting circuit with maximum power tracking |
| CN111431421A (en)* | 2020-04-21 | 2020-07-17 | 深圳技术大学 | A high-efficiency implantable full-wave rectifier circuit |
| CN116111990A (en)* | 2022-10-27 | 2023-05-12 | 北京智芯半导体科技有限公司 | Comparators used in full bridge rectifiers, full bridge rectifiers and electronics |
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| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee | Granted publication date:20170322 |