Background technology
Existing inserted 2 T pMOS flash array is comprised of the 2T pMOS flash cell of repeated arrangement, and the basic structure of flash cell as shown in Figure 1.2T PMOS flash cell is by selecting grid PMOS transistor (grid line SG-1 controls its grid potential) and control gate PMOS transistor (word line WL-1 controls its grid potential) series connection to form.Select grid PMOS transistor main technologic parameters as follows: " electrical thickness of gate oxide 8nm～11nm, channel length 100nm～300nm ".Control gate PMOS transistor main technologic parameters is as follows: electrical thickness of gate oxide 8nm～11nm (synchronize and form with the gate oxide of selecting gate transistor, so thickness is identical), ono dielectric layer (silicon dioxide-silicon nitride-silicon dioxide film) electrical thickness 10nm～20nm, multi-crystal silicon floating bar thickness 20nm～100nm (doping content 1020/ cm-3channel length 100nm～300nm above).Wherein, internal node knot (Internal-Node Junction, IN) is shared by two PMOS transistors.When SL-1 connects noble potential, when BL-1 connects electronegative potential, IN is equivalent to the transistorized drain electrode of control gate, is also the source electrode of selecting gate transistor simultaneously.
Existing inserted 2 T pMOS flash array adopts NOR type framework (as shown in Figure 2).BL in figure is the abbreviation of Bit Line, is commonly referred to " bit line ", is used for controlling the current potential of transistor drain terminal.WL is the abbreviation of Word Line, is commonly referred to " word line ", is used for controlling the extreme current potential of transistor gate.SL is the abbreviation of Source Line, is commonly referred to " source line ", is used for controlling the current potential of transistor source.Under NOR type circuit framework, can arrange by the different bias voltages of SG/BL/WL/SL, realize reading any one flash cell.Take scheme in the internal storage location 1 of circles mark be example, we are opened and are selected grid pMOS by SG-1, by WL-1 to suitable grid voltage of control gate pMOS, whether during by read operation, between BL-1 and SL-1, exist electric current to judge " 0 "/" 1 ", the bias voltage setting of concrete read operation is referring to table 1.
Table 1.2T pMOS flash memory read operation bias voltage arranges table
Wherein, VCC represents supply voltage.
The erase/program operations of existing inserted 2 T pMOS flash array is the same with read operation, the flash cell that need to choose particular address (scope) by the different bias voltage settings of SG/BL/WL/SL operates, and concrete bias voltage setting is referring to table 2 and table 3.
Table 2.2T pMOS flash memory erase operation bias voltage arranges table
Table 3.2T pMOS flash memory programming operation bias voltage arranges table
Existing inserted 2 T PMOS flash array is comprised of the flash cell of 2T cascaded structure.Wiping, in the process of programming and read operation, must be by selecting gate transistor (SG) laterally select (conventionally define BL direction for longitudinally).
With reference to table 1-3, can see that device wiping or during programming operation, can apply respectively the high pressure of forward or negative sense on SG.In order to tolerate above-mentioned high pressure, the transistorized electrical thickness of gate oxide of selection grid PMOS can not be excessively thin, therefore has to adopt tunnel oxide as gate oxide.Due to the restriction of 2T cascaded structure, the gate oxide of blocked up selection gate transistor can cause selected flash cell when carrying out read operation, and the voltage of SG must be enough low (such as-2V) just can obtain enough large reading current.Angle from circuit design, pressure reduction excessive (as VCC+2V) when too low SG bias voltage can cause read operation between " SG choosing " and " unchecked SG ", thereby discharge and recharge while making to switch SG address in read operation, overlong time, dynamic current are excessive, to read power consumption too high.
In addition,, owing to transmitting high pressure to SG when wiping with programming operation, the peripheral circuit that SG is relevant (such as decoding circuit, driving circuit) must use the withstand voltage high tension apparatus that exceeds 10V.And for reading circuit, the threshold voltage of high tension apparatus is too high, drive current is too small, switching speed is excessively slow, these shortcomings all can and read power consumption to flash memory reading speed and cause adverse effect.
Above-mentioned embedded flash memory (Embedded Flash Memory), the form with IP is integrated into system level chip conventionally, such as SIM-card (client identification module card) chip of mobile phone, Intelligent Bank the core of the card sheet etc.Due to this characteristic, therefore be called " embedded ", the product (Stand-alone Flash Memory, free-standing flash memory) forming to be different from independent flash memory; PMOS (FET)-P-type mos field effect transistor, MOS=MOSFET, it is the basic composition device of modern VLSI (very large scale integrated circuit), PMOS has four control ends, respectively gate terminal (Gate), drain terminal (Drain), source (Source) and substrate terminal (Bulk), by the control of Electric potentials of this four end, can realize transistorized opening and closing (conducting of corresponding current and cut-off); Select gate transistor-Select Gate Transistor, conventionally and control gate transistor series, common form " 2T flash cell ", by selecting gate transistor, the flash cell that can select or cancel selected fixed address operates, the embedded PMOS flash memory relating to for this special project, selecting gate transistor is PMOS; Control gate transistor-Control Gate Transistor, the i.e. unit of storage " 0/1 " on ordinary meaning.By concrete operations, make this transistor present different electrology characteristic (such as different threshold voltages), thus representative " 0 " or " 1 "; Floating boom-Floating Gate, is conventionally embedded between the transistorized control gate of control gate and silicon substrate and forms similar sandwich structure.
Summary of the invention
The object of the present invention is to provide a kind of flash memory and read method thereof, 3T PMOS flash memory of the present invention can improve the reading efficiency of flash memory on the whole, effectively reduce and read power consumption, overcome existing 2T PMOS flash memory pipe when read operation, discharge and recharge overlong time, dynamic current excessive, read the too high shortcoming of power consumption.
For solving the problems of the technologies described above, embodiments of the present invention disclose a kind of flash memory, and the array of this flash memory comprises at least one sector, and each sector comprises N-type trap and is arranged in a plurality of flash cells that this N-type trap connects into rectangular array, wherein,
Each flash cell comprises one and selects grid PMOS transistor, control gate PMOS transistor and one to read to select grid PMOS transistor, select grid PMOS transistor, control gate PMOS transistor and read and select grid PMOS transistor to be connected with the second electrode array by the first electrode;
Read and select the transistorized electrical thickness of gate oxide of grid PMOS to be less than the transistorized electrical thickness of gate oxide of selection grid PMOS, read and select the transistorized channel length of grid PMOS to be less than the transistorized channel length of selection grid PMOS, read and select the absolute value of the transistorized threshold voltage of grid PMOS lower than the absolute value of selecting the transistorized threshold voltage of grid PMOS;
The first electrode is that source electrode and the second electrode are drain electrode, or the first electrode is that drain electrode and the second electrode are source electrode.
Embodiments of the present invention also disclose a kind of read method of flash memory, the method is used for the read operation of flash memory as described above, and in the rectangular array that the flash cell of this flash memory connects into, transistorized the second electrode of selection grid PMOS that is positioned at same row is joined together to form the first control line, the transistorized grid of selection grid PMOS that is positioned at same a line is joined together to form the second control line, reading in each sector selects transistorized the first electrode of grid PMOS to be joined together to form one article of the 3rd control line, being positioned at reading of same a line selects the transistorized grid of grid PMOS to be joined together to form the 4th control line, the transistorized grid of control gate PMOS that is positioned at same a line is joined together to form the 5th control line,
This read method comprises the following steps:
When carrying out read operation, the current potential that the N-type trap of each sector is set is supply voltage, the current potential of each the second control line is-2～-0.5V, the current potential of the first control line of the selected flash cell reading is supply voltage, and the current potential of the 3rd control line, the 4th control line and the 5th control line is 0.
Compared with prior art, the key distinction and effect thereof are embodiment of the present invention:
3T PMOS flash memory of the present invention has and is exclusively used in reading of reading and selects grid PMOS transistor, can be when read operation, fixingly select the transistorized bias voltage setting of grid PMOS, and by reading, select the grid voltage of gate transistor to convert to carry out address and choose.Because reading, this select gate transistor only for read operation, high-pressure limit when its structure setting is not subject to programming operation and erase operation, its electrical thickness of gate oxide and channel length etc. can be set to be less than selection gate transistor, and relevant reading circuit can be comprised of pure low-voltage device, improve on the whole the reading efficiency of flash memory, effectively reduce and read power consumption, while overcoming existing 2TPMOS flash memory read operation, discharge and recharge overlong time, dynamic current excessive, read the too high shortcoming of power consumption.
Flash memory of the present invention can provide large as far as possible reading current and fast as far as possible reading speed when carrying out read operation, and greatly reduces and read power consumption.
Embodiment
In the following description, in order to make reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs and the many variations based on following embodiment and modification, also can realize each claim of the application technical scheme required for protection.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
In the embodiments of the present invention, in order to be consistent with this area common-use words, and conveniently understand the present invention, the first control line is called to bit line (BL), the second control line is called selects grid line (SG), the 3rd control line is called source line (SL), and the 4th control line is called to read selects grid line (READ-SG), and the 5th control line is called word line (WL).
First embodiment of the invention relates to a kind of flash memory.Particularly, the array of this flash memory comprises at least one sector, each sector comprises N-type trap (DNW) and is arranged in a plurality of flash cells that this N-type trap connects into rectangular array, wherein, each flash cell comprises one and selects grid PMOS transistor, control gate PMOS transistor and one to read to select grid PMOS transistor, select grid PMOS transistor, control gate PMOS transistor and read and select grid PMOS transistor to be connected with the second electrode array by the first electrode.Read and select the transistorized electrical thickness of gate oxide of grid PMOS to be less than the transistorized electrical thickness of gate oxide of selection grid PMOS, read and select the transistorized channel length of grid PMOS to be less than the transistorized channel length of selection grid PMOS, read and select the absolute value of the transistorized threshold voltage of grid PMOS lower than the absolute value of selecting the transistorized threshold voltage of grid PMOS.And the first electrode is that source electrode and the second electrode are drain electrode, or the first electrode is that drain electrode and the second electrode are source electrode.
In the present invention, select grid PMOS transistor, control gate PMOS transistor and read and select grid PMOS transistor to be connected and to refer in each flash cell with the second electrode array by the first electrode, three transistor series, and one of them transistorized first electrode (or second electrode) and transistorized the second electrode of another one (or the first electrode is connected).Such as, in certain flash cell of the present invention, select the transistorized source electrode of grid PMOS to be connected with the transistorized drain electrode of control gate PMOS, the transistorized source electrode of control gate PMOS with read the transistorized drain electrode of selection grid PMOS and be connected; Or the transistorized source electrode of control gate PMOS is connected with selecting the transistorized drain electrode of grid PMOS, selects the transistorized source electrode of grid PMOS and read the transistorized drain electrode of selection grid PMOS and be connected etc.In addition, read and select grid PMOS transistor to refer to by grid voltage to convert to control the transistor that flash memory reading address is chosen, be exclusively used in the read operation of flash memory.And control gate PMOS transistor is the PMOS transistor with floating boom.
As shown in Figure 3, in a preference of the present invention, in flash cell, select transistorized the first electrode of grid PMOS to be connected with transistorized the second electrode of control gate PMOS, transistorized the first electrode of control gate PMOS is connected with the second electrode that reads selection gate transistor.Wherein, the first electrode is that source electrode and the second electrode are drain electrode.Reading and selecting the transistorized electrical thickness of gate oxide of grid PMOS is 4～10nm, and channel length is 100～200nm, and threshold voltage is-0.6～-0.3V, and saturation current is 150～300 μ A/ μ m.Selecting the transistorized electrical thickness of gate oxide of grid PMOS is 8～11nm, and channel length is 100～300nm, and threshold voltage is-1.5～-0.8V, and saturation current is 80～100uA/um.
In addition, be appreciated that in other embodiments of the present invention, if just read considering of power consumption for reduction, read and select gate transistor can be positioned at selection gate transistor and the transistorized centre of control gate, also can not be positioned between the two.In actual fabrication process, for all other restrictions with consider, such as: (a) reading, select gate transistor to be placed on to select in the middle of gate transistor and control gate transistor, at this moment be difficult to control the threshold voltage of selecting gate transistor, because the threshold value of selection gate transistor is injected and the transistorized threshold value of control gate is injected all and can be selected the channel region of grid to spread toward reading; (b) reading, select gate transistor to be placed on the left side of selecting gate transistor, at this moment be difficult to reduce the electrical thickness of gate oxide (otherwise there will be integrity problem) of selecting gate transistor, because read under the state of " choosing BL not choose SG " when programming, select gate transistor must bear the electric field force effect of GIDL (gated-induce drain leakage, grid induction drain leakage current) field effect; (c) in sum, the angle realizing from practical application, preferably, reads and selects the best putting position of gate transistor be and select gate transistor to lay respectively at the transistorized both sides of control gate.
In addition, be appreciated that merely from improving the angle that reads power consumption, read select gate transistor gate oxidation electrical layer thickness more Bao Yuehao, channel length more short better, threshold voltage is the smaller the better.Such as, under the technique of 55nm embedded flash memory platform, can consider to adopt the PMOS of 1.2V supply voltage to select grid PMOS transistor as reading.Than select grid PMOS transistor, read to select the transistorized electrical thickness of gate oxide of grid PMOS from 80nm reduce to above 1～2nm, threshold voltage from-reduce to above-0.5V of 0.8V left and right, saturation current from 100 μ A/ μ m be increased to 280 μ A/ μ m left and right, channel length shortens to 1/3.
Certainly, actual process processing procedure will be realized and utilize Low-Voltage Logic Devices (Core Logic Device) to serve as to read selection gate transistor, must make larger change, and the cost of time and money is high.
Therefore,, in another preference of the present invention, the cellular construction of 3T PMOS flash memory of the present invention is to take the cellular construction of existing NOR type inserted 2 T PMOS flash memory to be basis, adds therein to read and selects grid PMOS transistor to realize.This structure is centered by control gate PMOS transistor, to selecting grid PMOS transistor to carry out image copying, formed to read, selects grid PMOS transistor, as shown in Figure 4.In order optimizing to read, to select the transistorized performance of grid PMOS, to read and select grid PMOS transistor selecting on the basis of grid PMOS transistor device parameter, by channel length shortened 25～50nm, threshold voltage has reduced-0.5～-0.3V.This 3T PMOS flash memory unit structure is completely compatible with existing 2T PMOS flash cell processing procedure on technique realizes, and does not increase any processing step; Because the height of three devices on structure/height is similar, the homogeneity of production and the reliability of device have obtained good guarantee simultaneously.
In addition, be appreciated that, in the present invention, read and select grid PMOS transistor to have multiple implementation, be not limited to the structure of above-mentioned " class 2T pMOS flash memory is selected gate transistor " based on 2T PMOS, can on the basis of 1T NMOS or PMOS, add and read selection gate transistor, also can on the basis of 2T NMOS, carry out; Can be flash memory, can be also E2PROM (band EEPROM (Electrically Erasable Programmable Read Only Memo)) or OTP/MTP (disposable programmable memory/time-after-time programmable memory).
3T PMOS flash memory in this preference is without the original erasing-programming/reading conditions of change, only need to control reading of newly adding and select grid PMOS transistor, the all operations of original 2T PMOS flash memory be can realize, and new quality or integrity problem do not introduced.The flash memory generating to be to reduce the selecting bias voltage of grid to switch scope when flash array reads, thereby promotes the speed that discharges and recharges in read operation process, reduce dynamic reading current.In addition, the 3T PMOS flash cell of this preference and existing 2T pMOS flash cell are completely compatible in technique, in operating conditions, in circuit design, can carry out various combinations according to the specific requirement of SOC product, thereby provide the scope of application and shorter Market Entry Time widely for final products.
In another preference, between the floating boom of the embedded PMOS flash memory in the present invention and control gate, adopting between the isolation of oxide-nitride thing-oxide (Oxide-Nitride-Oxide) insulation film, floating boom and silicon substrate adopts oxide (Oxide) insulation film to isolate, floating boom itself is the polysilicon of N-type or the doping of P type, can be used to stored charge (being electronics in this case) thereby the transistorized electrology characteristic of change control gate.
3T PMOS flash memory of the present invention has and is exclusively used in reading of reading and selects grid PMOS transistor, can be when read operation, the transistorized bias voltage setting of fixing selection grid PMOS, by reading, select the transistorized grid voltage of grid PMOS to convert to carry out address to choose, because reading, this select grid PMOS transistor only for read operation, its structure setting is not subject to the high-pressure limit of programming operation and erase operation, can be by its electrical thickness of gate oxide, the parameter such as channel length and threshold voltage is set to be less than selection grid PMOS transistor, and relevant reading circuit can be comprised of pure low-voltage device, improve on the whole the reading efficiency of flash memory, effectively reduce and read power consumption, overcome existing 2T PMOS transistor and when read operation, discharge and recharge overlong time, dynamic current is too high, read the too high shortcoming of power consumption.
Second embodiment of the invention relates to a kind of read method of flash memory.The method is used for the read operation of flash memory as described in embodiment 1.In the rectangular array that the flash cell of above-mentioned flash memory connects into, transistorized the second electrode of selection grid PMOS that is positioned at same row is joined together to form the first control line, the transistorized grid of selection grid PMOS that is positioned at same a line is joined together to form the second control line, reading in each sector selects transistorized the first electrode of grid PMOS to be joined together to form one article of the 3rd control line, being positioned at reading of same a line selects the transistorized grid of grid PMOS to be joined together to form the 4th control line, the transistorized grid of control gate PMOS that is positioned at same a line is joined together to form the 5th control line.
This read method comprises the following steps:
When carrying out read operation, the current potential that the N-type trap of each sector is set is supply voltage, the current potential of each the second control line is-2～-0.5V, the current potential of the first control line of the selected flash cell reading is supply voltage, and the current potential of the 3rd control line, the 4th control line and the 5th control line is 0; The current potential that the first control line, the 3rd control line, the 4th control line and the 5th control line of the not selected flash cell reading are set is 0, wherein, the not selected flash cell reading and the selected flash cell reading have same the second control line and the first different control lines; It is supply voltage that the first control line of the not selected flash cell reading and the current potential of the 4th control line are set, the current potential of the 3rd control line and the 5th control line is 0, wherein, the not selected flash cell reading and the selected flash cell reading have same the first control line and the second different control lines; The current potential that the first control line, the 3rd control line and the 5th control line of the not selected flash cell reading are set is 0, the current potential of the 4th control line is supply voltage, wherein, the not selected flash cell reading has the first different control lines and the second different control lines from the selected flash cell reading.
Flash memory of the present invention can provide large as far as possible reading current and fast as far as possible reading speed when carrying out read operation, and greatly reduces and read power consumption.
In addition, when above-mentioned flash memory execution is wiped with programming operation, read and select grid PMOS transistor only to play the effect of transmission gate, for example, in a preference of the present invention, its grid potential is set to supply voltage VCC, as shown in table 4 and table 5:
Table 4.3T pMOS flash memory erase operation bias voltage arranges table
Table 5.3T pMOS flash memory programming operation bias voltage arranges table
Obviously, if 3T PMOS flash memory unit structure does not adopt " selection gate transistor " similar structures to form " read and select gate transistor ", the concrete bias voltage setting of erasing-programming/read operation must select gate transistor characteristic to optimize and revise according to new reading.But basic thought does not change,, when the operations with high pressure such as erasing-programming, read and select gate transistor only as voltage transmission purposes, avoid any additional impact; When read operation, read and select gate transistor as horizontal selection purposes, large as far as possible reading current and fast as far as possible reading speed are provided.
In addition, even adopted the flash cell of other erasing-programming physical mechanisms, no matter NMOS or PMOS, can be by adding a special-purpose method that reads selection gate transistor, come separated " read operation " and " erasing-programming high pressure " the different requirements for selection gate transistor, thereby reach the object of " the low power consumption that reads " or " ultrafast reading speed ".
It should be noted that, in the claim and instructions of this patent, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element that " comprises " and limit by statement, and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and described, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.