技术领域technical field
本发明涉及微电子技术领域中的运算放大器设计技术领域，特别设计一种低压全差分运算放大器电路。The invention relates to the technical field of operational amplifier design in the technical field of microelectronics, and particularly designs a low-voltage fully differential operational amplifier circuit.
背景技术Background technique
运算放大器(简称运放)是许多模拟系统和混合信号系统的一个完整部分。大量的不同复杂程度的运放被用来实现各种功能：从直流偏置的产生到高速放大或滤波。伴随着每一代互补金属氧化物半导体(CMOS)工艺，由于电源电压和晶体管沟道长度的减小，运放的设计越来越复杂。电源电压的减小，动态范围将减小，采用差分操作可以增大信号摆幅。动态范围的下限也将受到关注，为了让动态范围随着电源的下降成比例的减小，噪声和非线性特性必须保持恒定。但是随着电源电压的减小，非线性一般会增加，通常为了让VDS减小，MOS场效应管的W/L值很大，这样噪声趋于保持恒定或减小。Operational amplifiers (op amps for short) are an integral part of many analog and mixed-signal systems. A large number of operational amplifiers of varying complexity are used to perform various functions: from DC bias generation to high-speed amplification or filtering. With each generation of complementary metal-oxide-semiconductor (CMOS) technology, the design of op amps has become more complex due to reductions in supply voltages and transistor channel lengths. As the power supply voltage decreases, the dynamic range will decrease, and the signal swing can be increased by using differential operation. The lower limit of the dynamic range will also be of concern, in order for the dynamic range to decrease proportionally as the supply drops, the noise and non-linearities must remain constant. However, as the power supply voltage decreases, the nonlinearity generally increases. Usually, in order to reduce the VDS , the W/L value of the MOS field effect transistor is very large, so that the noise tends to remain constant or decrease.
传统两级全差分运算放大器：Traditional two-stage fully differential op amp:
利用传统两级运算放大器实现高速高增益的性能。附图1所示的是没有示出偏置电路的采用电源电压为5V的共源共栅结构和共源极放大器级联的两级全差分运算放大器。M0～M8组成共源共栅放大器提高增益。其中M5～M8构成共源共栅电流源M9～M12构成两个共源极放大器提高摆幅。M13～M17是采用电阻电容采样的共模反馈电路中的共模放大器。以稳定直流工作点。Utilizes traditional two-stage operational amplifiers to achieve high-speed, high-gain performance. Figure 1 shows a cascaded two-stage fully differential operational amplifier with a power supply voltage of 5V and cascaded common source amplifiers without a bias circuit. M0-M8 form a cascode amplifier to increase the gain. Among them, M5-M8 form a cascode current source, and M9-M12 form two common-source amplifiers to increase the swing. M13-M17 are common-mode amplifiers in the common-mode feedback circuit using resistance and capacitance sampling. To stabilize the DC operating point.
这种技术的不足之处是电源电压为5V，同时为了实现高增益采用晶体管数较多的套筒式共源共栅结构，导致功耗较大，同时压摆率也很大。在现代低电源电压低功耗产品应用时不可取。The disadvantage of this technology is that the power supply voltage is 5V, and at the same time, in order to achieve high gain, a sleeve-type cascode structure with a large number of transistors is used, resulting in large power consumption and high slew rate. Not advisable in modern low supply voltage low power consumption products.
发明内容Contents of the invention
本发明要解决的技术问题是提供一种低压全差分运算放大器电路，用以解决现有全差分运算放大器在低电源应用时，由于共模反馈电路的影响，导致的差分增益不高的问题。The technical problem to be solved by the present invention is to provide a low-voltage fully differential operational amplifier circuit to solve the problem of low differential gain due to the influence of the common-mode feedback circuit when the existing fully differential operational amplifier is used in low power supply.
为了解决上述技术问题，本发明实施例提供一种低压全差分运算放大器电路，包括：偏置电路11、与所述偏置电路11连接的两级全差分运算放大器12以及与所述两级全差分运算放大器12连接的共模反馈电路13；其中，In order to solve the above technical problems, an embodiment of the present invention provides a low-voltage fully differential operational amplifier circuit, including: a bias circuit 11, a two-stage fully differential operational amplifier 12 connected to the bias circuit 11, and a two-stage fully differential operational amplifier 12 connected to the two-stage fully differential operational amplifier. The common mode feedback circuit 13 that differential operational amplifier 12 is connected; Wherein,
所述偏置电路11为所述两级全差分运算放大器12提供偏置电压；The bias circuit 11 provides a bias voltage for the two-stage fully differential operational amplifier 12;
所述共模反馈电路13用于稳定共模输出电压。The common-mode feedback circuit 13 is used to stabilize the common-mode output voltage.
进一步地，所述两级全差分运算放大器包括第一级差分放大器以及与所述第一级差分放大器连接的第二级运算放大器。Further, the two-stage fully differential operational amplifier includes a first-stage differential amplifier and a second-stage operational amplifier connected to the first-stage differential amplifier.
进一步地，所述第一级差分放大器包括：第一N型MOS管MN1、第二N型MOS管MN2、第一P型MOS管MP1、第二P型MOS管MP2以及第三P型MOS管MP3；其中，Further, the first-stage differential amplifier includes: a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, and a third P-type MOS transistor MP3; where,
所述第一N型MOS管MN1和所述第二N型MOS管MN2的源极均接地，所述第一N型MOS管MN1的栅极和所述第二N型MOS管MN2的栅极相连；Both the sources of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are grounded, the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN2 connected;
所述第一N型MOS管MN1的漏极与所述第一P型MOS管MP1的漏极连接，并在连接处输出第一级正向输出电压；The drain of the first N-type MOS transistor MN1 is connected to the drain of the first P-type MOS transistor MP1, and a first-stage positive output voltage is output at the connection;
所述第二N型MOS管MN2的漏极与所述第二P型MOS管MP2的漏极连接，并在连接处输出第一级负向输出电压；The drain of the second N-type MOS transistor MN2 is connected to the drain of the second P-type MOS transistor MP2, and a first-stage negative output voltage is output at the connection;
所述第一P型MOS管MP1的栅极接正向输入Vin+，所述第一P型MOS管MP1的源极接所述第三P型MOS管MP3的漏极；The gate of the first P-type MOS transistor MP1 is connected to the positive input Vin +, and the source of the first P-type MOS transistor MP1 is connected to the drain of the third P-type MOS transistor MP3;
所述第二P型MOS管MP2的栅极接负向输入Vin-，所述第二N型MOS管MN2的源极接所述第三P型MOS管MP3的漏极；The gate of the second P-type MOS transistor MP2 is connected to the negative input Vin −, the source of the second N-type MOS transistor MN2 is connected to the drain of the third P-type MOS transistor MP3;
所述第三P型MOS管MP3的源极接电源VDD，栅极接偏置电压Vb1。The source of the third P-type MOS transistor MP3 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 .
进一步地，所述第二级运算放大器包括：第三N型MOS管MN3、第四N型MOS管MN4、第四P型MOS管MP4以及第五P型MOS管MP5；其中，Further, the second-stage operational amplifier includes: a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fourth P-type MOS transistor MP4, and a fifth P-type MOS transistor MP5; wherein,
所述第三N型MOS管MN3的栅极接第一级负向输出电压，源极接地，漏极与所述第四P型MOS管MP4的漏极连接，并在连接处输出第二级负向输出电压VO-；The gate of the third N-type MOS transistor MN3 is connected to the negative output voltage of the first stage, the source is grounded, the drain is connected to the drain of the fourth P-type MOS transistor MP4, and the second-stage output voltage is output at the connection. Negative output voltage VO -;
所述第四P型MOS管MP4的漏极还连接第一电容C1的一端，所述第一电容C1的另一端接地；The drain of the fourth P-type MOS transistor MP4 is also connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded;
所述第四P型MOS管MP4的源极接电源VDD，栅极接偏置电压Vb1；The source of the fourth P-type MOS transistor MP4 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 ;
所述第四N型MOS管MN4的栅极接第一级正向输出电压，源极接地，漏极与所述第五P型MOS管MP5的漏极连接，并在连接处输出第二级正向输出电压VO+；The gate of the fourth N-type MOS transistor MN4 is connected to the positive output voltage of the first stage, the source is grounded, and the drain is connected to the drain of the fifth P-type MOS transistor MP5, and the second stage is output at the connection. Positive output voltage VO +;
所述第五P型MOS管MP5的漏极还连接第二电容C2的一端，所述第二电容C2的另一端接地；The drain of the fifth P-type MOS transistor MP5 is also connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded;
所述第五P型MOS管MP5的源极接电源VDD，栅极接偏置电压Vb1。The source of the fifth P-type MOS transistor MP5 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 .
进一步地，所述第一P型MOS管MP1的漏极和所述第四N型MOS管MN4的漏极以及所述第二P型MOS管MP2的漏极和所述第三N型MOS管MN3的漏极之间分别串联一个补偿电阻RC和一个补偿电容CC。Further, the drain of the first P-type MOS transistor MP1 and the drain of the fourth N-type MOS transistor MN4 and the drain of the second P-type MOS transistor MP2 and the third N-type MOS transistor A compensation resistor RC and a compensation capacitor CC are respectively connected in series between the drains of MN3 .
进一步地，所述共模反馈电路包括：共模电压检测电路以及与所述共模电压检测电路连接的误差放大器。Further, the common-mode feedback circuit includes: a common-mode voltage detection circuit and an error amplifier connected to the common-mode voltage detection circuit.
进一步地，所述共模电压检测电路包括：第一电阻R1、第二电阻R2、第三电容C3和第四电容C4；其中，Further, the common-mode voltage detection circuit includes: a first resistor R1, a second resistor R2, a third capacitor C3, and a fourth capacitor C4; wherein,
所述第一电阻R1和所述第二电阻R2并联，所述第三电容C3和所述第四电容C4并联，所述第一电阻R1和所述第三电容C3之间连接所述第二级正向输出电压VO+，所述第二电阻R2和所述第四电容C4之间连接所述第二级负向输出电压VO-，并且所述第一电阻R1和所述第二电阻R2的连接点与所述第三电容C3和第四电容C4的连接点之间短接。The first resistor R1 is connected in parallel with the second resistor R2, the third capacitor C3 is connected in parallel with the fourth capacitor C4, and the second capacitor C3 is connected between the first resistor R1 and the third capacitor C3. stage positive output voltage VO +, the second stage negative output voltage VO - is connected between the second resistor R2 and the fourth capacitor C4, and the first resistor R1 and the second The connection point of the resistor R2 is short-circuited with the connection points of the third capacitor C3 and the fourth capacitor C4.
进一步地，所述误差放大器包括：第六P型MOS管MP6、第七P型MOS管MP7、第八P型MOS管MP8、第九P型MOS管MP9和第五N型MOS管MN5；其中，Further, the error amplifier includes: a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, and a fifth N-type MOS transistor MN5; wherein ,
所述第八P型MOS管MP8的栅极连接所述第一电阻R1和所述第二电阻R2的连接点与所述第三电容C3和第四电容C4的连接点之间短接的输出，所述第八P型MOS管MP8的源极接所述第九P型MOS管MP9的漏极，所述第八P型MOS管MP8的漏极连接所述第五N型MOS管MN5的漏极；The gate of the eighth P-type MOS transistor MP8 is connected to the short-circuit output between the connection point of the first resistor R1 and the second resistor R2 and the connection point of the third capacitor C3 and the fourth capacitor C4 , the source of the eighth P-type MOS transistor MP8 is connected to the drain of the ninth P-type MOS transistor MP9, and the drain of the eighth P-type MOS transistor MP8 is connected to the fifth N-type MOS transistor MN5 Drain;
所述第五N型MOS管MN5的栅极和漏极短接并反馈连接到所述第一N型MOS管MN1和所述第二N型MOS管MN2的栅极，所述第五N型MOS管MN5的源极接地；The gate and drain of the fifth N-type MOS transistor MN5 are short-circuited and connected in feedback to the gates of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2, and the fifth N-type MOS transistor MN5 The source of the MOS transistor MN5 is grounded;
所述第六P型MOS管MP6和所述第七P型MOS管MP7的源极均连接所述第九P型MOS管MP9的漏极，所述第六P型MOS管MP6的栅极和第七P型MOS管MP7的栅极短接并接入参考电压Vcm；The sources of the sixth P-type MOS transistor MP6 and the seventh P-type MOS transistor MP7 are connected to the drain of the ninth P-type MOS transistor MP9, and the gate of the sixth P-type MOS transistor MP6 and The gate of the seventh P-type MOS transistor MP7 is short-circuited and connected to the reference voltage Vcm ;
所述第六P型MOS管MP6的漏极接所述第一N型MOS管MN1的漏极；The drain of the sixth P-type MOS transistor MP6 is connected to the drain of the first N-type MOS transistor MN1;
所述第七P型MOS管MP7的漏极接所述第二N型MOS管MN2的漏极；The drain of the seventh P-type MOS transistor MP7 is connected to the drain of the second N-type MOS transistor MN2;
所述第九P型MOS管MP9的源极接电源VDD，栅极接偏置电压Vb1。The source of the ninth P-type MOS transistor MP9 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 .
进一步地，所述第六P型MOS管MP6的宽长比和所述第七P型MOS管MP7的宽长比是所述第八P型MOS管MP8的宽长比的二分之一。Further, the width-to-length ratio of the sixth P-type MOS transistor MP6 and the width-to-length ratio of the seventh P-type MOS transistor MP7 are half of the width-to-length ratio of the eighth P-type MOS transistor MP8.
进一步地，所述偏置电路包括：参考电流源IREF、第六N型MOS管MN6、第七N型MOS管MN7和第十P型MOS管MP10；其中，Further, the bias circuit includes: a reference current source IREF , a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, and a tenth P-type MOS transistor MP10; wherein,
所述参考电流源IREF接所述第六N型MOS管MN6的漏极，所述第六N型MOS管MN6的栅极和漏极短接并且连接所述第七N型MOS管MN7的栅极；The reference current source IREF is connected to the drain of the sixth N-type MOS transistor MN6, the gate and drain of the sixth N-type MOS transistor MN6 are short-circuited and connected to the drain of the seventh N-type MOS transistor MN7 grid;
所述第六N型MOS管MN6和第七N型MOS管MN7的源极均接地；The sources of the sixth N-type MOS transistor MN6 and the seventh N-type MOS transistor MN7 are both grounded;
所述第七N型MOS管MN7的漏极连接所述第十P型MOS管MP10的漏极；The drain of the seventh N-type MOS transistor MN7 is connected to the drain of the tenth P-type MOS transistor MP10;
所述第十P型MOS管MP10的栅极和漏极短接，且漏极输出偏置电压Vb1，所述第十P型MOS管MP10的源极连接电源VDD。The gate and drain of the tenth P-type MOS transistor MP10 are short-circuited, and the drain outputs a bias voltage Vb1 , and the source of the tenth P-type MOS transistor MP10 is connected to the power supply VDD .
本发明的上述技术方案的有益效果如下：The beneficial effects of above-mentioned technical scheme of the present invention are as follows:
上述方案中，通过共模反馈电路的输出反馈回两级全差分运算放大器的电流源稳定了共模输出电压，解决了由于电路不对称引起的电流失配的问题，在保证系统稳定的情况下实现了低电源电压、高增益和低功耗。In the above scheme, the output of the common-mode feedback circuit is fed back to the current source of the two-stage fully differential operational amplifier to stabilize the common-mode output voltage and solve the problem of current mismatch caused by circuit asymmetry. Low supply voltage, high gain, and low power consumption are achieved.
附图说明Description of drawings
图1为传统的两级全差分运算放大器的电路结构框架图；Fig. 1 is the circuit structure frame diagram of traditional two-stage fully differential operational amplifier;
图2为本发明的低压全差分运算放大器电路的结构框架图；Fig. 2 is the structural frame diagram of low-voltage fully differential operational amplifier circuit of the present invention;
图3为本发明的两级全差分运算放大器的电路结构框架图；Fig. 3 is the circuit structure frame diagram of two-stage fully differential operational amplifier of the present invention;
图4为本发明的低压全差分运算放大器的共模反馈电路结构框架图；Fig. 4 is the frame diagram of the common mode feedback circuit structure of the low-voltage fully differential operational amplifier of the present invention;
图5为本发明的低压全差分运算放大器的偏置电路结构框架图；Fig. 5 is the frame diagram of the bias circuit structure of the low-voltage fully differential operational amplifier of the present invention;
图6为本发明的低压全差分运算放大器在TT工艺角下的幅频和相频曲线；Fig. 6 is the amplitude-frequency and phase-frequency curves of the low-voltage fully differential operational amplifier of the present invention under the TT process angle;
图7为本发明的低压全差分运算放大器的阶跃响应特性；Fig. 7 is the step response characteristic of the low-voltage fully differential operational amplifier of the present invention;
图8为本发明的共模反馈电路的幅频和相频特性；Fig. 8 is the amplitude-frequency and phase-frequency characteristics of the common mode feedback circuit of the present invention;
图9为本发明的低压全差分运算放大器的输出动态范围；Fig. 9 is the output dynamic range of the low-voltage fully differential operational amplifier of the present invention;
图10为本发明的低压全差分运算放大器的共模抑制比；Fig. 10 is the common-mode rejection ratio of the low-voltage fully differential operational amplifier of the present invention;
图11为本发明的低压全差分运算放大器的电源抑制比。FIG. 11 is the power supply rejection ratio of the low-voltage fully differential operational amplifier of the present invention.
具体实施方式Detailed ways
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.
本发明针对现有的全差分运算放大器在低电源应用时，由于共模反馈电路的影响，导致的差分增益不高的问题，提供一种低压全差分运算放大器电路。The invention provides a low-voltage fully differential operational amplifier circuit aiming at the problem that the differential gain is not high due to the influence of the common mode feedback circuit when the existing fully differential operational amplifier is applied in low power supply.
如图2所示，本发明实施例的所述低压全差分运算放大器电路，包括：偏置电路11、与所述偏置电路11连接的两级全差分运算放大器12以及与所述两级全差分运算放大器12连接的共模反馈电路13；其中，As shown in Figure 2, the low-voltage fully differential operational amplifier circuit of the embodiment of the present invention includes: a bias circuit 11, a two-stage fully differential operational amplifier 12 connected to the bias circuit 11, and a two-stage fully differential operational amplifier 12 connected to the two-stage fully differential operational amplifier The common mode feedback circuit 13 that differential operational amplifier 12 is connected; Wherein,
所述偏置电路11为所述两级全差分运算放大器12提供偏置电压Vb1；The bias circuit 11 provides a bias voltage Vb1 for the two-stage fully differential operational amplifier 12;
所述共模反馈电路13用于稳定共模输出电压。The common-mode feedback circuit 13 is used to stabilize the common-mode output voltage.
本发明上述实施例，通过共模反馈电路13的输出反馈回两级全差分运算放大器12的电流源稳定了共模输出电压，解决了由于电路不对称引起的电流失配的问题。In the above embodiments of the present invention, the output of the common-mode feedback circuit 13 is fed back to the current source of the two-stage fully differential operational amplifier 12 to stabilize the common-mode output voltage and solve the problem of current mismatch caused by circuit asymmetry.
应当说明的是，本发明另一实施例中，所述两级全差分运算放大器12包括第一级差分放大器(又称差模放大器)以及与所述第一级差分放大器连接的第二级运算放大器。It should be noted that, in another embodiment of the present invention, the two-stage fully differential operational amplifier 12 includes a first-stage differential amplifier (also known as a differential mode amplifier) and a second-stage operational amplifier connected to the first-stage differential amplifier. amplifier.
如图2和图3所示，本发明又一实施例中，所述第一级差分放大器包括：第一N型MOS管MN1、第二N型MOS管MN2、第一P型MOS管MP1、第二P型MOS管MP2以及第三P型MOS管MP3；其中，As shown in Fig. 2 and Fig. 3, in yet another embodiment of the present invention, the first-stage differential amplifier includes: a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a first P-type MOS transistor MP1, The second P-type MOS transistor MP2 and the third P-type MOS transistor MP3; wherein,
所述第一N型MOS管MN1和所述第二N型MOS管MN2的源极均接地，所述第一N型MOS管MN1的栅极和所述第二N型MOS管MN2的栅极相连；Both the sources of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are grounded, the gate of the first N-type MOS transistor MN1 and the gate of the second N-type MOS transistor MN2 connected;
所述第一N型MOS管MN1的漏极与所述第一P型MOS管MP1的漏极连接，并在连接处输出第一级正向输出电压；The drain of the first N-type MOS transistor MN1 is connected to the drain of the first P-type MOS transistor MP1, and a first-stage positive output voltage is output at the connection;
所述第二N型MOS管MN2的漏极与所述第二P型MOS管MP2的漏极连接，并在连接处输出第一级负向输出电压；The drain of the second N-type MOS transistor MN2 is connected to the drain of the second P-type MOS transistor MP2, and a first-stage negative output voltage is output at the connection;
所述第一P型MOS管MP1的栅极接正向输入Vin+，所述第一P型MOS管MP1的源极接所述第三P型MOS管MP3的漏极；The gate of the first P-type MOS transistor MP1 is connected to the positive input Vin +, and the source of the first P-type MOS transistor MP1 is connected to the drain of the third P-type MOS transistor MP3;
所述第二P型MOS管MP2的栅极接负向输入Vin-，所述第二N型MOS管MN2的源极接所述第三P型MOS管MP3的漏极；The gate of the second P-type MOS transistor MP2 is connected to the negative input Vin −, the source of the second N-type MOS transistor MN2 is connected to the drain of the third P-type MOS transistor MP3;
所述第三P型MOS管(MP3)的源极接电源VDD，栅极接偏置电压Vb1。The source of the third P-type MOS transistor (MP3) is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 .
具体地，所述第二级运算放大器包括：第三N型MOS管MN3、第四N型MOS管MN4、第四P型MOS管MP4以及第五P型MOS管MP5；其中，Specifically, the second-stage operational amplifier includes: a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fourth P-type MOS transistor MP4, and a fifth P-type MOS transistor MP5; wherein,
所述第三N型MOS管MN3的栅极接第一级负向输出电压，源极接地，漏极与所述第四P型MOS管MP4的漏极连接，并在连接处输出第二级负向输出电压VO-；The gate of the third N-type MOS transistor MN3 is connected to the negative output voltage of the first stage, the source is grounded, the drain is connected to the drain of the fourth P-type MOS transistor MP4, and the second-stage output voltage is output at the connection. Negative output voltage VO -;
所述第四P型MOS管MP4的漏极还连接第一电容C1的一端，所述第一电容C1的另一端接地；The drain of the fourth P-type MOS transistor MP4 is also connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded;
所述第四P型MOS管MP4的源极接电源VDD，栅极接偏置电压Vb1；The source of the fourth P-type MOS transistor MP4 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 ;
所述第四N型MOS管MN4的栅极接第一级正向输出电压，源极接地，漏极与所述第五P型MOS管MP5的漏极连接，并在连接处输出第二级正向输出电压VO+；The gate of the fourth N-type MOS transistor MN4 is connected to the positive output voltage of the first stage, the source is grounded, and the drain is connected to the drain of the fifth P-type MOS transistor MP5, and the second stage is output at the connection. Positive output voltage VO +;
所述第五P型MOS管MP5的漏极还连接第二电容C2的一端，所述第二电容C2的另一端接地；The drain of the fifth P-type MOS transistor MP5 is also connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded;
所述第五P型MOS管MP5的源极接电源VDD，栅极接偏置电压Vb1。The source of the fifth P-type MOS transistor MP5 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 .
为了提高单位增益带宽且提高稳定性避免系统振荡，本发明又一实施例中，在第一级差分放大器和第二级运算放大器之间设置有一个电阻和电容串联组成的补偿电路，具体设置如3所示，在所述第一P型MOS管MP1的漏极和所述第四N型MOS管MN4的漏极以及所述第二P型MOS管MP2的漏极和所述第三N型MOS管MN3的漏极之间分别串联一个补偿电阻RC和一个补偿电容CC。In order to improve the unity gain bandwidth and improve the stability to avoid system oscillation, in another embodiment of the present invention, a compensation circuit composed of a resistor and a capacitor connected in series is provided between the first-stage differential amplifier and the second-stage operational amplifier. The specific settings are as follows: 3, the drain of the first P-type MOS transistor MP1 and the drain of the fourth N-type MOS transistor MN4 and the drain of the second P-type MOS transistor MP2 and the third N-type A compensation resistor RC and a compensation capacitor CC are respectively connected in series between the drains of the MOS transistor MN3 .
应当说明的是，上述实施例中所述电源VDD为1V的电源电压，所述第二级负向输出电压VO-和所述第二级正向输出电压VO+为两级全差分运算放大器输出的共模电压。It should be noted that, in the above embodiment, the power supply VDD is a power supply voltage of 1V, and the second-stage negative output voltage VO - and the second-stage positive output voltage VO + are two-stage fully differential Common-mode voltage at the output of the op amp.
上述实施例中，所述两级全差分运算放大器中各晶体管的W/L比(即宽长比)的确定方法如下：In the above-mentioned embodiment, the determination method of the W/L ratio (i.e. width-to-length ratio) of each transistor in the two-stage fully differential operational amplifier is as follows:
首先根据1V的电源电压和相应摆幅的要求确定两级全差分运算放大器中各晶体管的过驱动电压，然后通过电流和功耗的要求分配流过电流源MOS管的电流，从而确定各晶体管的W/L比，具体根据如下公式：First, determine the overdrive voltage of each transistor in the two-stage fully differential operational amplifier according to the power supply voltage of 1V and the corresponding swing requirements, and then distribute the current flowing through the current source MOS tube according to the requirements of current and power consumption, so as to determine the overdrive voltage of each transistor W/L ratio, specifically according to the following formula:
公式一：
公式二：
由上述可知，低压下要有足够高的摆幅，MOS管的过驱电压(VGS和VT)必须很小，同时MOS管的宽长比必须足够大以保证足够高的电流来增大增益。It can be seen from the above that to have a sufficiently high swing under low voltage, the overdrive voltage (VGS and VT ) of the MOS tube must be small, and the width-to-length ratio of the MOS tube must be large enough to ensure a high enough current to increase gain.
公式三：rO＝1/λIDFormula 3: rO ＝1/λID
公式四：λ∝1/LFormula 4: λ∝1/L
由公式三和公式四可得到L，同时由公式一和公式二可得到具体的宽和长。L can be obtained from Formula 3 and Formula 4, and the specific width and length can be obtained from Formula 1 and Formula 2.
同时，可得出第一级差分放大器的增益为：At the same time, the gain of the first-stage differential amplifier can be obtained as:
第二级运算放大器的增益为：The gain of the second op amp is:
两级全差分运算放大器的增益为：
本发明上述方案，根据应用的需要，通过合理增大两级全差分运算放大器中的器件的宽长比使其过驱动电压降低，可以在低电源电压下获得较大的输出摆幅，通过此种两级全差分运算放大器电路的设计实现了低电源电压下的高增益。According to the needs of the application, the above scheme of the present invention reduces the overdrive voltage by reasonably increasing the width-to-length ratio of the devices in the two-stage fully differential operational amplifier, so that a larger output swing can be obtained at a low power supply voltage. Through this A two-stage fully differential operational amplifier circuit design achieves high gain at low supply voltage.
继续如图2和图4所示，本发明又一实施例中，所述共模反馈电路13包括：共模电压检测电路以及与所述共模电压检测电路连接的误差放大器。As shown in FIG. 2 and FIG. 4 , in yet another embodiment of the present invention, the common-mode feedback circuit 13 includes: a common-mode voltage detection circuit and an error amplifier connected to the common-mode voltage detection circuit.
具体地，所述共模电压检测电路包括：第一电阻R1、第二电阻R2、第三电容C3和第四电容C4；其中，Specifically, the common-mode voltage detection circuit includes: a first resistor R1, a second resistor R2, a third capacitor C3, and a fourth capacitor C4; wherein,
所述第一电阻R1和所述第二电阻R2并联，所述第三电容C3和所述第四电容C4并联，所述第一电阻R1和所述第三电容C3之间连接所述第二级正向输出电压VO+，所述第二电阻R2和所述第四电容C4之间连接所述第二级负向输出电压VO-，并且所述第一电阻R1和所述第二电阻R2的连接点与所述第三电容C3和第四电容C4的连接点之间短接。The first resistor R1 is connected in parallel with the second resistor R2, the third capacitor C3 is connected in parallel with the fourth capacitor C4, and the second capacitor C3 is connected between the first resistor R1 and the third capacitor C3. stage positive output voltage VO +, the second stage negative output voltage VO - is connected between the second resistor R2 and the fourth capacitor C4, and the first resistor R1 and the second The connection point of the resistor R2 is short-circuited with the connection points of the third capacitor C3 and the fourth capacitor C4.
具体地，所述误差放大器包括：第六P型MOS管MP6、第七P型MOS管MP7、第八P型MOS管MP8、第九P型MOS管MP9和第五N型MOS管MN5；其中，Specifically, the error amplifier includes: a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, and a fifth N-type MOS transistor MN5; ,
所述第八P型MOS管MP8的栅极连接所述第一电阻R1和所述第二电阻R2的连接点与所述第三电容C3和第四电容C4的连接点之间短接的输出，所述第八P型MOS管MP8的源极接所述第九P型MOS管MP9的漏极，所述第八P型MOS管MP8的漏极连接所述第五N型MOS管MN5的漏极；The gate of the eighth P-type MOS transistor MP8 is connected to the short-circuit output between the connection point of the first resistor R1 and the second resistor R2 and the connection point of the third capacitor C3 and the fourth capacitor C4 , the source of the eighth P-type MOS transistor MP8 is connected to the drain of the ninth P-type MOS transistor MP9, and the drain of the eighth P-type MOS transistor MP8 is connected to the fifth N-type MOS transistor MN5 Drain;
所述第五N型MOS管MN5的栅极和漏极短接并反馈连接到所述第一N型MOS管MN1和所述第二N型MOS管MN2的栅极，所述第五N型MOS管MN5的源极接地；The gate and drain of the fifth N-type MOS transistor MN5 are short-circuited and connected in feedback to the gates of the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2, and the fifth N-type MOS transistor MN5 The source of the MOS transistor MN5 is grounded;
所述第六P型MOS管MP6和所述第七P型MOS管MP7的源极均连接所述第九P型MOS管MP9的漏极，所述第六P型MOS管MP6的栅极和第七P型MOS管MP7的栅极短接并接入参考电压Vcm；The sources of the sixth P-type MOS transistor MP6 and the seventh P-type MOS transistor MP7 are connected to the drain of the ninth P-type MOS transistor MP9, and the gate of the sixth P-type MOS transistor MP6 and The gate of the seventh P-type MOS transistor MP7 is short-circuited and connected to the reference voltage Vcm ;
所述第六P型MOS管MP6的漏极接所述第一N型MOS管MN1的漏极；The drain of the sixth P-type MOS transistor MP6 is connected to the drain of the first N-type MOS transistor MN1;
所述第七P型MOS管MP7的漏极接所述第二N型MOS管MN2的漏极；The drain of the seventh P-type MOS transistor MP7 is connected to the drain of the second N-type MOS transistor MN2;
所述第九P型MOS管MP9的源极接电源VDD，栅极接偏置电压Vb1。The source of the ninth P-type MOS transistor MP9 is connected to the power supply VDD , and the gate is connected to the bias voltage Vb1 .
应当说明的是，所述第六P型MOS管MP6、第七P型MOS管MP7和第九P型MOS管MP9共同组成了共模放大器。It should be noted that the sixth P-type MOS transistor MP6 , the seventh P-type MOS transistor MP7 and the ninth P-type MOS transistor MP9 together form a common-mode amplifier.
本发明上述方案中的误差放大器用来实现放大输出共模电平与参考电压Vcm的差值。The error amplifier in the above solution of the present invention is used to amplify the difference between the output common mode level and the reference voltage Vcm .
应当说明的是，所述第六P型MOS管MP6的宽长比和所述第七P型MOS管MP7的宽长比是所述第八P型MOS管MP8的宽长比的二分之一。It should be noted that the width-to-length ratio of the sixth P-type MOS transistor MP6 and the width-to-length ratio of the seventh P-type MOS transistor MP7 are half of the width-to-length ratio of the eighth P-type MOS transistor MP8 one.
本发明上述实施例，通过利用电阻电容采样的共模反馈电路稳定共模输出电压，减小了电路体积和功耗，同时提高了电路的输出摆幅。In the above-mentioned embodiments of the present invention, the common-mode output voltage is stabilized by using the common-mode feedback circuit of resistance-capacitance sampling, which reduces the circuit size and power consumption, and improves the output swing of the circuit at the same time.
如图3所示，本发明又一实施例中，所述偏置电路包括：参考电流源IREF、第六N型MOS管MN6、第七N型MOS管MN7和第十P型MOS管MP10；其中，As shown in FIG. 3, in another embodiment of the present invention, the bias circuit includes: a reference current source IREF , a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, and a tenth P-type MOS transistor MP10 ;in,
所述参考电流源IREF接所述第六N型MOS管MN6的漏极，所述第六N型MOS管MN6的栅极和漏极短接并且连接所述第七N型MOS管MN7的栅极；The reference current source IREF is connected to the drain of the sixth N-type MOS transistor MN6, the gate and drain of the sixth N-type MOS transistor MN6 are short-circuited and connected to the drain of the seventh N-type MOS transistor MN7 grid;
所述第六N型MOS管MN6和第七N型MOS管MN7的源极均接地；The sources of the sixth N-type MOS transistor MN6 and the seventh N-type MOS transistor MN7 are both grounded;
所述第七N型MOS管MN7的漏极连接所述第十P型MOS管MP10的漏极；The drain of the seventh N-type MOS transistor MN7 is connected to the drain of the tenth P-type MOS transistor MP10;
所述第十P型MOS管MP10的栅极和漏极短接，且漏极输出偏置电压Vb1，所述第十P型MOS管MP10的源极连接电源VDD。The gate and drain of the tenth P-type MOS transistor MP10 are short-circuited, and the drain outputs a bias voltage Vb1 , and the source of the tenth P-type MOS transistor MP10 is connected to the power supply VDD .
应当说明的是，所述参考电流源IREF可以通过设计一个与电源电压无关的，并且经过温度补偿的专门电路产生，也可以为经温度补偿的带隙基准电压电路产生(具体地，产生参考电流源IREF的电路设计为本领域技术人员所述熟知的，在此不再详细说明)，合理设置电源流的值可以使偏置电压Vb1偏置在固定的电压从而使得尾电流MOS管处于饱和区，为低压全差分运算放大器的工作提供保证。It should be noted that the reference current source IREF can be generated by designing a special circuit that has nothing to do with the power supply voltage and has undergone temperature compensation, and can also be generated by a temperature-compensated bandgap reference voltage circuit (specifically, generate a reference The circuit design of the current source IREF is well known to those skilled in the art, and will not be described in detail here), and the value of the power supply current can be set reasonably to bias the bias voltage Vb1 at a fixed voltage so that the tail current MOS tube In the saturation region, it guarantees the operation of the low-voltage fully differential operational amplifier.
应当说明的是，所述共模反馈电路中的共模放大器和差模放大器共用了电流源及输出负载，简化了电路设计的同时，减小了功耗。It should be noted that the common-mode amplifier and differential-mode amplifier in the common-mode feedback circuit share the current source and output load, which simplifies circuit design and reduces power consumption.
参照图2，对本发明的主要工作原理进行说明如下：With reference to Fig. 2, the main working principle of the present invention is described as follows:
通过两级全差分运算放大器的第一级来提高增益，第二级提高摆幅，为了稳定性的需要，在一二级之间接一个密勒电阻和电容调整零点，使其在左半平面，保证系统稳定；由于在高增益的放大器中，我们要求P型电流源和N性电流源相平衡是不能实现的，他们之间的差值会通过本征输出阻抗，导致输出电压的变化，高增益下这个电压变化很大，会驱动电流源进入线性区，因此需要设置共模反馈电路保证输出稳定，共模反馈电路中的共模电压检测电路采用电阻电容采样调整相位裕度，同时避免了单独采用电阻造成的电阻过大和利用源跟随器使输出摆幅降低的缺点，使得低电源电压成为可能；最后得到的输出共模电压连接放大器的负向输入端与参考电压比较放大，最后将共模反馈的输出连接到N型MOS管电流源的栅极，以稳定输出共模电平，根据稳定的输出共模电压使所有晶体管工作在饱和区。The gain is increased by the first stage of the two-stage fully differential operational amplifier, and the swing is increased by the second stage. For the sake of stability, a Miller resistor and capacitor are connected between the first and second stage to adjust the zero point so that it is in the left half plane. Ensure the stability of the system; because in the high-gain amplifier, we require that the P-type current source and the N-type current source are balanced and cannot be realized. The difference between them will pass through the intrinsic output impedance, resulting in a change in the output voltage, high Under the gain, this voltage changes greatly, which will drive the current source into the linear region. Therefore, it is necessary to set up a common-mode feedback circuit to ensure stable output. The common-mode voltage detection circuit in the common-mode feedback circuit uses resistor-capacitor sampling to adjust the phase margin, while avoiding The shortcomings of excessive resistance caused by the use of resistors alone and the use of source followers to reduce the output swing make low power supply voltages possible; the final output common-mode voltage is connected to the negative input of the amplifier and compared with the reference voltage. Finally, the common-mode voltage is amplified. The output of the mode feedback is connected to the gate of the N-type MOS tube current source to stabilize the output common mode level, and make all transistors work in the saturation region according to the stable output common mode voltage.
本发明的低压全差分运算放大器在各工艺角下的增益(AV)、增益带宽(GB)和相位裕度(PM)对比如表1所示，具体的工艺角包括：TT(Typical NMOS andTypical PMOS)工艺角、SF(Slow NMOS and Fast PMOS)工艺角、FS(Fast NMOSand Slow PMOS)工艺角、FF(Fast NMOS and Fast PMOS)工艺角和SS(SlowNMOS and Slow PMOS)工艺角。The comparison of gain (AV), gain bandwidth (GB) and phase margin (PM) of the low-voltage fully differential operational amplifier of the present invention at each process angle is shown in Table 1. The specific process angles include: TT (Typical NMOS and Typical PMOS ) process corner, SF (Slow NMOS and Fast PMOS) process corner, FS (Fast NMOS and Slow PMOS) process corner, FF (Fast NMOS and Fast PMOS) process corner and SS (SlowNMOS and Slow PMOS) process corner.
表1本发明运放在各工艺角下的AV、GB和PM对比Table 1 AV, GB, and PM comparisons of the operational amplifier of the present invention under each process angle
根据图6可知，低压全差分运算放大器在TT工艺角下的直流增益为84.18dB，单位增益带宽为15.26MHz，相位裕度为63.56°，增益均在80dB以上，单位增益带宽都在15MHz以上，相位裕度在60°左右，满足应用要求。According to Figure 6, it can be seen that the DC gain of the low-voltage fully differential operational amplifier at the TT process angle is 84.18dB, the unity gain bandwidth is 15.26MHz, the phase margin is 63.56°, the gain is above 80dB, and the unity gain bandwidth is above 15MHz. The phase margin is about 60°, which meets the application requirements.
由图7所示，当给定一个1V的阶跃信号时，低压全差分运算放大器的压摆率为5.81V/μs。As shown in Figure 7, when a step signal of 1V is given, the slew rate of the low-voltage fully differential operational amplifier is 5.81V/μs.
如图8所示，所述共模反馈电路的直流增益为86.43dB，单位增益带宽为13.9MHz，相位裕度为45.78°。As shown in FIG. 8, the DC gain of the common mode feedback circuit is 86.43dB, the unity gain bandwidth is 13.9MHz, and the phase margin is 45.78°.
如图9所示，将低压全差分运算放大器连接成增益为-10的形式，通过扫描输入信号幅度，可以得到最大失真为0.1％时的输出动态幅度，所述低压全差分运算放大器的输出动态范围为±253mV。As shown in Figure 9, the low-voltage fully differential operational amplifier is connected in the form of a gain of -10, and the output dynamic range when the maximum distortion is 0.1% can be obtained by scanning the input signal amplitude. The output dynamic range of the low-voltage fully differential operational amplifier is The range is ±253mV.
如图10所示，在100Hz时，共模抑制比为198.2dB；在1MHz时，共模抑制比为97.2dB。As shown in Figure 10, at 100Hz, the common-mode rejection ratio is 198.2dB; at 1MHz, the common-mode rejection ratio is 97.2dB.
如图11所示，在100Hz时，低压全差分运算放大器的电源抑制比为194.5dB；在1MHz时，共模抑制比为92.9dB。As shown in Figure 11, at 100Hz, the power supply rejection ratio of the low-voltage fully differential operational amplifier is 194.5dB; at 1MHz, the common-mode rejection ratio is 92.9dB.
通过以上的仿真测试结果可以看出，本发明的所述低压全差分运算放大器实现了低压高增益的特性。It can be seen from the above simulation test results that the low-voltage fully differential operational amplifier of the present invention realizes the characteristics of low-voltage and high-gain.
本发明上述方案，由于在1V电源电压下实现高增益工作，同时又有足够的输出摆幅，降低了功耗；同时，由于共模反馈电路结构共用了共模放大器和差模放大器的输入级中的电流镜和输出负载，一方面降低了功耗，另一方面保证了共模放大器和差模放大器在交流特性上保持完全一致，因为共模放大器的输出级与差模放大器的输出级可以完全共用，电容补偿电路也完全一样，只要差模放大器频率特性是稳定的，则共模反馈电路也是稳定的。Said scheme of the present invention, owing to realize high-gain operation under 1V power supply voltage, has enough output swing again at the same time, has reduced power consumption; Simultaneously, because common-mode feedback circuit structure has shared the input stage of common-mode amplifier and differential-mode amplifier The current mirror and the output load in the circuit, on the one hand, reduce the power consumption, and on the other hand, ensure that the AC characteristics of the common-mode amplifier and the differential-mode amplifier are completely consistent, because the output stage of the common-mode amplifier and the output stage of the differential-mode amplifier can be It is completely shared, and the capacitance compensation circuit is exactly the same. As long as the frequency characteristic of the differential mode amplifier is stable, the common mode feedback circuit is also stable.
以上所述的是本发明的优选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本发明所述原理前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。What has been described above is a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications can also be made without departing from the principle of the present invention. These improvements and modifications should also be considered as Be the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410180809.7ACN104113295A (en) | 2014-04-30 | 2014-04-30 | Low-voltage fully-differential operation amplifier circuit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410180809.7ACN104113295A (en) | 2014-04-30 | 2014-04-30 | Low-voltage fully-differential operation amplifier circuit |
| Publication Number | Publication Date |
|---|---|
| CN104113295Atrue CN104113295A (en) | 2014-10-22 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410180809.7APendingCN104113295A (en) | 2014-04-30 | 2014-04-30 | Low-voltage fully-differential operation amplifier circuit |
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| C06 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication | Application publication date:20141022 | |
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