技术领域technical field
本发明属于半导体功率器件技术领域，特别是涉及一种U形沟槽的功率器件及其制造方法。The invention belongs to the technical field of semiconductor power devices, in particular to a U-shaped trench power device and a manufacturing method thereof.
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背景技术Background technique
随着现代微电子技术的不断深入发展，功率MOS晶体管以其输入阻抗高、低损耗、开关速度快、无二次击穿、安全工作区宽、动态性能好、易与前极耦合实现大电流化、转换效率高等优点，逐渐替代双极型器件成为当今半导体功率器件发展的主流。常用的半导体功率器件主要有平面扩散型MOS晶体管和沟槽型MOS晶体管等类型。以沟槽型MOS晶体管为例，该器件因采用了垂直沟道结构，其面积比平面扩散型MOS晶体管要小很多，所以其电流密度有很大的提高。With the continuous development of modern microelectronics technology, power MOS transistors have high input impedance, low loss, fast switching speed, no secondary breakdown, wide safe working area, good dynamic performance, and easy coupling with the front electrode to achieve high current. With the advantages of high efficiency and high conversion efficiency, gradually replacing bipolar devices has become the mainstream of the development of semiconductor power devices today. Commonly used semiconductor power devices mainly include planar diffused MOS transistors and trench MOS transistors. Taking the trench type MOS transistor as an example, because the device adopts a vertical channel structure, its area is much smaller than that of the planar diffusion type MOS transistor, so its current density is greatly improved.
公知的沟槽型功率器件的剖面结构如图1所示，在整个U形沟槽（13）的表面形成有厚度均匀的栅氧化层（15、16），该结构的沟槽型功率器件为提高开关频率需要增加栅氧化层厚度以降低栅氧电容，然而栅氧化层厚度增加会提高器件工作电压。为解决上述问题，国际专利申请PCT/US2002/028067 公开的“带有自对准源极和接触的沟槽型场效应晶体管”方案中提出了一种U形沟槽的功率器件，其剖面结构如图2所示，该结构是在U形沟槽的底部形成比栅氧化层的厚度更厚的场氧化层，使得器件具有较低的栅氧电容，以提升开关频率。但该结构的U形沟槽的功率器件还存在以下明显不足：一是受击穿电压的限制，其硅外延层的掺杂浓度较低，增大了其导通电阻，影响了U形沟槽功率器件的性能；二是U形沟槽底部的厚场氧化层和沟道区薄栅氧化层之间的过渡区过小，使得底部场氧化应力增大，导致发生漏电流及可靠性问题。The cross-sectional structure of a known trench-type power device is shown in Figure 1, and a gate oxide layer (15, 16) with a uniform thickness is formed on the surface of the entire U-shaped trench (13). The trench-type power device of this structure is Increasing the switching frequency requires increasing the thickness of the gate oxide layer to reduce the gate oxide capacitance, but increasing the thickness of the gate oxide layer will increase the operating voltage of the device. In order to solve the above problems, the "Trench Field Effect Transistor with Self-Aligned Source and Contact" scheme disclosed in the international patent application PCT/US2002/028067 proposes a power device with a U-shaped trench, and its cross-sectional structure As shown in FIG. 2 , in this structure, a field oxide layer thicker than the thickness of the gate oxide layer is formed at the bottom of the U-shaped trench, so that the device has a lower gate oxide capacitance to increase the switching frequency. However, the U-shaped groove power device of this structure still has the following obvious shortcomings: First, due to the limitation of the breakdown voltage, the doping concentration of the silicon epitaxial layer is low, which increases its on-resistance and affects the U-shaped groove. The performance of trench power devices; the second is that the transition zone between the thick field oxide layer at the bottom of the U-shaped trench and the thin gate oxide layer in the channel region is too small, which increases the field oxidation stress at the bottom, resulting in leakage current and reliability problems .
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发明内容Contents of the invention
本发明的目的是为克服现有技术的不足而提供一种U形沟槽的功率器件及其制造方法，本发明一方面通过在功率器件漏区之上的漂移区内形成电荷补偿区，形成超结结构来提高功率器件的击穿电压，可在不影响击穿电压的前提下，提高硅外延层的掺杂浓度、降低导通电阻；另一方面通过在U形沟槽的底部预置一个小的凹槽，再进行场氧化层的氧化，使得场氧化的应力过渡区得到延长，以大大降低氧化应力造成的漏电流和提高器件的可靠性。The object of the present invention is to provide a U-shaped trench power device and its manufacturing method in order to overcome the deficiencies of the prior art. On the one hand, the present invention forms a charge compensation region in the drift region above the drain region of the power device to form The super junction structure can be used to improve the breakdown voltage of power devices, which can increase the doping concentration of the silicon epitaxial layer and reduce the on-resistance without affecting the breakdown voltage; on the other hand, by presetting the bottom of the U-shaped trench A small groove, and then oxidize the field oxide layer, so that the stress transition region of field oxidation is extended, so as to greatly reduce the leakage current caused by oxidation stress and improve the reliability of the device.
根据本发明提出的一种U形沟槽的功率器件，它包括： According to the power device of a kind of U-shaped groove that the present invention proposes, it comprises:
半导体衬底底部的第一掺杂类型的漏区，以及位于所述漏区之上的半导体衬底内的第一种掺杂类型的漂移区；a drain region of the first doping type at the bottom of the semiconductor substrate, and a drift region of the first doping type in the semiconductor substrate above the drain region;
其特征在于还包括：It is characterized in that it also includes:
在所述漂移区内设有第二种掺杂类型的电荷补偿区，该电荷补偿区与所述漂移区之间设有超结结构；A charge compensation region of the second doping type is provided in the drift region, and a superjunction structure is provided between the charge compensation region and the drift region;
在所述电荷补偿区之上的半导体衬底内设有U形沟槽，该U形沟槽的底部延伸进入所述漂移区；A U-shaped trench is provided in the semiconductor substrate above the charge compensation region, and the bottom of the U-shaped trench extends into the drift region;
在所述U形沟槽侧壁两侧的半导体衬底内分别设有第二种掺杂类型的沟道区，在该U形沟槽侧壁的两个侧面上分别设有覆盖该沟道区的栅氧化层、以及在该U形沟槽底部设有场氧化层，该场氧化层的两侧呈鸟嘴形状；Channel regions of the second doping type are respectively provided in the semiconductor substrate on both sides of the side walls of the U-shaped trench. The gate oxide layer in the region and the field oxide layer are provided at the bottom of the U-shaped trench, and the two sides of the field oxide layer are in the shape of a bird's beak;
在所述U形沟槽内设有覆盖所述栅氧化层和场氧化层的多晶硅栅极；A polysilicon gate covering the gate oxide layer and the field oxide layer is provided in the U-shaped trench;
在所述半导体衬底内的两个沟道区之上分别设有第一种掺杂类型的源区。Source regions of the first doping type are respectively provided above the two channel regions in the semiconductor substrate.
本发明提出的一种U形沟槽的功率器件的进一步优化方案是：The further optimization scheme of the power device of a kind of U-shaped groove that the present invention proposes is:
本发明所述U形沟槽底部设有一个开口宽度小于该U形沟槽开口宽度的凹槽，该凹槽的深度为10-100纳米，所述场氧化层填满该凹槽。The bottom of the U-shaped groove in the present invention is provided with a groove whose opening width is smaller than that of the U-shaped groove. The depth of the groove is 10-100 nanometers, and the field oxide layer fills up the groove.
本发明所述第一种掺杂类型为n型掺杂，则所述第二种掺杂类型为p型掺杂；或所述第一种掺杂类型为p型掺杂，则所述第二种掺杂类型为n型掺杂。The first doping type mentioned in the present invention is n-type doping, then the second doping type is p-type doping; or the first doping type is p-type doping, then the first doping type The two doping types are n-type doping.
本发明所述场氧化层的厚度大于所述栅氧化层的厚度。In the present invention, the thickness of the field oxide layer is greater than the thickness of the gate oxide layer.
基于上述本发明提出的一种U形沟槽的功率器件的制造方法，它包括起始步骤：A method for manufacturing a power device based on the above-mentioned U-shaped groove proposed by the present invention, it includes initial steps:
（1）在所述第一种掺杂类型的漏区之上外延形成第一种掺杂类型的硅外延层； (1) Epitaxially forming a silicon epitaxial layer of the first doping type on the drain region of the first doping type;
（2）在所述硅外延层的表面形成硬掩膜层，之后进行光刻和刻蚀在所述硅外延层内形成U形沟槽；(2) forming a hard mask layer on the surface of the silicon epitaxial layer, and then performing photolithography and etching to form a U-shaped groove in the silicon epitaxial layer;
（3）在所述U形沟槽的表面依次形成第一层绝缘薄膜和第二层绝缘薄膜；(3) sequentially forming a first layer of insulating film and a second layer of insulating film on the surface of the U-shaped groove;
其特征在于还包括以下继续步骤：It is characterized in that it also includes the following continuing steps:
（4）进行离子注入，在所述U形沟槽底部的硅外延层内形成第二种掺杂类型的电荷补偿区； (4) performing ion implantation to form a charge compensation region of the second doping type in the silicon epitaxial layer at the bottom of the U-shaped trench;
（5）通过各向异性的刻蚀方法刻蚀掉U形沟槽底部的所述第二层绝缘薄膜；(5) Etching off the second insulating film at the bottom of the U-shaped trench by an anisotropic etching method;
（6）刻蚀掉暴露的U形沟槽底部的所述第一层绝缘薄膜，并继续在U形沟槽的底部进行10-100纳米厚度的硅外延层的刻蚀；(6) Etching away the first layer of insulating film at the bottom of the exposed U-shaped trench, and continuing to etch a silicon epitaxial layer with a thickness of 10-100 nanometers at the bottom of the U-shaped trench;
（7）通过氧化工艺在所述U形沟槽的底部形成场氧化层；(7) forming a field oxide layer at the bottom of the U-shaped trench through an oxidation process;
（8）完全刻蚀掉所述第二层绝缘薄膜、暴露的第一层绝缘薄膜和硬掩膜层；(8) completely etching away the second insulating film, the exposed first insulating film and the hard mask layer;
（9）进行热氧化，在所述U形沟槽的两个侧壁上分别形成栅氧化层，该栅氧化层厚度小于该U形沟槽底部形成的场氧化层厚度；(9) performing thermal oxidation to form a gate oxide layer on the two side walls of the U-shaped trench respectively, the thickness of the gate oxide layer being smaller than the thickness of the field oxide layer formed at the bottom of the U-shaped trench;
（10）进行多晶硅淀积和各向同性刻蚀，在所述U形沟槽内形成覆盖所述场氧化层和栅氧化层的多晶硅栅极，该多晶硅栅极顶部低于所述硅外延层的上表面；(10) Perform polysilicon deposition and isotropic etching, and form a polysilicon gate covering the field oxide layer and gate oxide layer in the U-shaped trench, and the top of the polysilicon gate is lower than the silicon epitaxial layer the upper surface of
（11）进行离子注入，在所述硅外延层内形成第二种掺杂类型的沟道区；(11) performing ion implantation to form a channel region of the second doping type in the silicon epitaxial layer;
（12）进行源区光刻和离子注入，在沟道区之上形成第一种掺杂类型的源区。(12) Perform source region photolithography and ion implantation to form a source region of the first doping type above the channel region.
本发明提出的一种U形沟槽的功率器件的制造方法的进一步优选方案是：A further preferred solution of the manufacturing method of a U-shaped groove power device proposed by the present invention is:
本发明所述的步骤（4）可在步骤（5）或步骤（6）之后进行。Step (4) in the present invention can be performed after step (5) or step (6).
本发明所述第一层绝缘薄膜的材质为氧化硅。The material of the first insulating film in the present invention is silicon oxide.
本发明所述第二层绝缘薄膜的材质为氮化硅或氮氧化硅。The material of the second insulating film in the present invention is silicon nitride or silicon oxynitride.
本发明步骤（11）所述离子注入可在步骤（1）之后进行，在整个硅外延层的顶部由离子注入形成掺杂区。The ion implantation in step (11) of the present invention can be performed after step (1), and a doped region is formed by ion implantation on the top of the entire silicon epitaxial layer.
本发明所述步骤（6）为备选步骤。The step (6) in the present invention is an optional step.
本发明与现有技术相比其显著优点在于：第一，本发明的U形沟槽的功率器件是在漏区之上的漂移区内形成电荷补偿区，从而在电荷补偿区与漂移区之间形成超结结构，它能够提高功率器件的击穿电压，即在不改变功率器件击穿电压的条件下，提高硅外延层的掺杂浓度、降低导通电阻；第二，本发明在U形凹槽的底部设置一个小的凹槽，使得场氧化应力过渡区得到延长，很好地解决了场氧化应力造成的漏电流问题和提高了器件的可靠性；第三，本发明通过自对准工艺形成电荷补偿区和U形沟槽底部的凹槽，工艺过程简单，易于控制，特别适用于20V至1000V的U形沟槽的功率器件的制造。Compared with the prior art, the present invention has significant advantages in that: first, the power device of the U-shaped trench of the present invention forms a charge compensation region in the drift region above the drain region, thereby forming a charge compensation region between the charge compensation region and the drift region. Form a super junction structure between them, which can increase the breakdown voltage of power devices, that is, without changing the breakdown voltage of power devices, increase the doping concentration of the silicon epitaxial layer and reduce the on-resistance; second, the present invention is in U A small groove is arranged at the bottom of the shaped groove, so that the field oxidation stress transition region is extended, which solves the leakage current problem caused by the field oxidation stress and improves the reliability of the device; The quasi-process forms the charge compensation area and the groove at the bottom of the U-shaped trench. The process is simple and easy to control. It is especially suitable for the manufacture of power devices with U-shaped trenches from 20V to 1000V.
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附图说明Description of drawings
图1是现有技术的一种U形沟槽的功率器件的剖面结构示意图。FIG. 1 is a schematic cross-sectional structure diagram of a U-shaped trench power device in the prior art.
图2是现有技术的另一种U形沟槽的功率器件的剖面结构示意图。FIG. 2 is a schematic cross-sectional structure diagram of another U-shaped trench power device in the prior art.
图3是本发明的一种U形沟槽的功率器件的一个实施例的剖面结构示意图。Fig. 3 is a schematic cross-sectional structure diagram of an embodiment of a U-shaped trench power device of the present invention.
图4是仿真得到的本发明的一种U形沟槽的功率器件与传统结构的U形沟槽的功率器件的导通电流的比较曲线示意图。FIG. 4 is a schematic diagram of a comparison curve of conduction current obtained by simulation between a U-shaped trench power device of the present invention and a conventional U-shaped trench power device.
图5至图11是本发明的一种U形沟槽的功率器件的制造方法的一个实施例的工艺流程示意图。5 to 11 are schematic process flow diagrams of an embodiment of a method for manufacturing a U-shaped trench power device according to the present invention.
图12和图13是本发明的一种U形沟槽的功率器件的制造方法的另一个实施例的工艺流程示意图。12 and 13 are schematic process flow diagrams of another embodiment of a method for manufacturing a U-shaped trench power device according to the present invention.
图14是本发明的一种U形沟槽的功率器件的一个实施例的俯视示意图。FIG. 14 is a schematic top view of an embodiment of a U-shaped trench power device of the present invention.
图15是本发明的一种U形沟槽的功率器件的另一个实施例的俯视示意图。FIG. 15 is a schematic top view of another embodiment of a U-shaped trench power device of the present invention.
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具体实施方式Detailed ways
为清楚地说明本发明的具体实施方式，说明书附图中所列示图，放大了本发明所述的层和区域的厚度，且所示图形大小并不代表实际尺寸；附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于附图中所示区域的特定形状，而是包括所得到的形状如制造引起的偏差等、再如刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例中均以矩形表示；同时在下面的描述中，所使用的术语半导体衬底可理解为包括正在工艺加工中的半导体晶片，还包括在其上所制备的其它薄膜层，比如半导体衬底上形成的外延层。 In order to clearly illustrate the specific implementation of the present invention, the figures listed in the accompanying drawings of the description enlarge the thickness of the layers and regions described in the present invention, and the size of the figures shown does not represent the actual size; the drawings are schematic , should not limit the scope of the present invention. The embodiments listed in the description should not be limited to the specific shapes of the regions shown in the drawings, but include the obtained shapes such as deviations caused by manufacturing, etc., and the curves obtained by etching usually have curved or rounded characteristics, but In the embodiment of the present invention, they are all represented by rectangles; meanwhile, in the following description, the term semiconductor substrate used can be understood as including the semiconductor wafer in process processing, and also includes other thin film layers prepared thereon, such as epitaxial layer formed on a semiconductor substrate. the
以下所述本发明的剖面结构，如无特殊说明，均为沿采用条状元胞结构的沟道长度方向的剖面结构。The sectional structure of the present invention described below is a sectional structure along the length direction of the channel adopting the strip cell structure unless otherwise specified.
下面结合附图和实施例对本发明的具体实施方式作进一步的详细说明。The specific implementation manners of the present invention will be further described in detail below in conjunction with the drawings and examples.
图3是本发明的一种U形沟槽的功率器件的一个实施例的剖面结构示意图，它是由本发明的三个U形沟槽的功率器件组成的并联结构。如图3所示，本发明的U形沟槽的功率器件包括半导体衬底内的第一掺杂类型的漏区200，在该漏区200之上形成有硅外延层，在该硅外延层内形成有第一种掺杂类型的漂移区201，在该漂移区201内形成第二种掺杂类型的电荷补偿区205，该电荷补偿区205与漂移区201之间形成超结结构；所述第一种掺杂类型与第二种掺杂类型为相反的掺杂类型，若第一种掺杂类型为n型掺杂，则第二种掺杂类型为p型掺杂；相对应的，若第一种掺杂类型为p型掺杂，则第二种掺杂类型为n型掺杂。Fig. 3 is a schematic cross-sectional structure diagram of an embodiment of a U-shaped trench power device of the present invention, which is a parallel structure composed of three U-shaped trench power devices of the present invention. As shown in FIG. 3 , the power device of the U-shaped trench of the present invention includes a drain region 200 of the first doping type in the semiconductor substrate, a silicon epitaxial layer is formed on the drain region 200, and a silicon epitaxial layer is formed on the silicon epitaxial layer A drift region 201 of the first doping type is formed in the drift region 201, a charge compensation region 205 of the second doping type is formed in the drift region 201, and a super junction structure is formed between the charge compensation region 205 and the drift region 201; The first doping type and the second doping type are opposite doping types, if the first doping type is n-type doping, then the second doping type is p-type doping; the corresponding , if the first doping type is p-type doping, then the second doping type is n-type doping.
在所述电荷补偿区205之上的硅外延层内形成的一个U形沟槽，该U形凹槽的底部延伸进入漂移区201；在所述U形沟槽侧壁两侧的硅外延层内分别形成第二种掺杂类型的沟道区209，在所述U形沟槽的两个侧壁上分别形成的覆盖沟道区209的栅氧化层207。A U-shaped groove formed in the silicon epitaxial layer above the charge compensation region 205, the bottom of the U-shaped groove extends into the drift region 201; the silicon epitaxial layer on both sides of the U-shaped groove sidewall Channel regions 209 of the second doping type are respectively formed therein, and gate oxide layers 207 covering the channel regions 209 are respectively formed on two sidewalls of the U-shaped trenches.
在U形沟槽的底部设有开口宽度小于U形沟槽开口宽度的凹槽400，该凹槽400的深度为10-100纳米，覆盖该凹槽400和U形沟槽的底部设有场氧化层206，该场氧化层206的两侧呈鸟嘴形状，该场氧化层206的厚度大于所述栅氧化层207的厚度。The bottom of U-shaped groove is provided with the groove 400 that opening width is less than U-shaped groove opening width, and the depth of this groove 400 is 10-100 nanometer, covers this groove 400 and the bottom of U-shaped groove and is provided with field Oxide layer 206 , the two sides of the field oxide layer 206 are in the shape of a bird's beak, and the thickness of the field oxide layer 206 is greater than the thickness of the gate oxide layer 207 .
对应的虚线框中的结构详细展示了进行场氧化前的U形沟槽底部的凹槽结构，凹槽400是为延长场氧化层206与栅氧化层206之间的场氧化应力过渡区，很好地解决了场氧化应力造成的漏电流问题和提高了器件可靠性。The structure in the corresponding dotted box shows in detail the groove structure at the bottom of the U-shaped trench before field oxidation. The groove 400 is to extend the field oxidation stress transition region between the field oxide layer 206 and the gate oxide layer 206. The leakage current problem caused by the field oxidation stress is well solved and the reliability of the device is improved.
根据需要，本发明也可不形成U形沟槽底部的深度为10-100纳米的凹槽400。According to requirements, the present invention may not form the groove 400 at the bottom of the U-shaped groove with a depth of 10-100 nanometers.
在所述U形沟槽内形成的覆盖栅氧化层207和场氧化层206的多晶硅栅极208，该多晶硅栅极208的顶部低于该U形沟槽的顶部，这是为了在U形沟槽顶部填充绝缘层211，使得多晶硅栅极208与外部电极绝缘；在所述硅外延层内、所述两个沟道区209之上分别设有第一种掺杂类型的源区210。The polysilicon gate 208 covering the gate oxide layer 207 and the field oxide layer 206 formed in the U-shaped trench, the top of the polysilicon gate 208 is lower than the top of the U-shaped trench, this is for the U-shaped trench The top of the trench is filled with an insulating layer 211 to insulate the polysilicon gate 208 from the external electrodes; source regions 210 of the first doping type are provided in the silicon epitaxial layer and above the two channel regions 209 .
在所述源区210之上还设有与源区210和沟道区209相接触的源极金属212，源极金属212通过沟道区接触区213与沟道区209接触。A source metal 212 in contact with the source region 210 and the channel region 209 is further provided on the source region 210 , and the source metal 212 is in contact with the channel region 209 through a channel region contact region 213 .
源极金属212与源区210和沟道区209之间还有多为业界所公知的接触技术，在本实施例中不在详细描述。There are many contact technologies known in the industry between the source metal 212 and the source region 210 and the channel region 209 , which will not be described in detail in this embodiment.
图4为通过仿真得到的本发明的U形沟槽的功率器件与传统结构的U形沟槽的功率器件的导通电流的比较曲线图。如图4所示，本发明的U形沟槽的功率器件可在相同的击穿电压（BVdss）下获得更大的导通电流（Ids_on），即在相同的击穿电压条件下具有更低的导通电阻。FIG. 4 is a comparative graph of conduction current of the U-shaped groove power device of the present invention and the U-shaped groove power device of the traditional structure obtained through simulation. As shown in Figure 4, the U-shaped groove power device of the present invention can obtain a larger on-current (Ids_on) at the same breakdown voltage (BVdss), that is, it has a lower on-resistance.
图5至图11是本发明提出的一种U型沟槽的功率器件的制造方法的一个实施例的工艺流程示意图，该实施例是同时制造本发明的三个并联的U型沟槽的功率器件，其具体实施步骤依次如下：5 to 11 are schematic process flow diagrams of an embodiment of a method for manufacturing a U-shaped groove power device proposed by the present invention. This embodiment is to simultaneously manufacture three parallel U-shaped groove power devices of the present invention. device, its specific implementation steps are as follows:
结合图5，首先在半导体衬底的第一种掺杂类型的漏区200之上外延形成一层第一种掺杂类型的硅外延层201，然后在硅外延层210上形成硬掩膜层202，之后进行光刻和刻蚀，在硅外延层内形成一个U形沟槽，该硬掩膜层202通常包括一层薄的衬垫氧化层和一层厚的氮化硅介质层，薄氧化层用于改善氮化硅层与硅外延层之间的应力。Referring to FIG. 5 , first epitaxially form a silicon epitaxial layer 201 of the first doping type on the drain region 200 of the first doping type of the semiconductor substrate, and then form a hard mask layer on the silicon epitaxial layer 210 202, followed by photolithography and etching to form a U-shaped trench in the silicon epitaxial layer, the hard mask layer 202 usually includes a thin pad oxide layer and a thick silicon nitride dielectric layer, thin The oxide layer is used to improve the stress between the silicon nitride layer and the silicon epitaxial layer.
接下来，结合图6，在 U形沟槽的表面氧化形成第一层绝缘薄膜203，该第一层绝缘薄膜203的材质为氧化硅，其厚度范围为10～20纳米；接下来，继续在第一层绝缘薄膜203的表面形成第二层绝缘薄膜204，该第二层绝缘薄膜204的材质为氮化硅或氮氧化硅，其厚度范围优选为10～20纳米；之后进行离子注入，在U形沟槽底部的硅外延层内形成第二种掺杂类型的电荷补偿区205。Next, in conjunction with FIG. 6, a first layer of insulating film 203 is oxidized on the surface of the U-shaped groove. The material of the first layer of insulating film 203 is silicon oxide, and its thickness ranges from 10 to 20 nanometers; A second layer of insulating film 204 is formed on the surface of the first layer of insulating film 203, and the material of the second layer of insulating film 204 is silicon nitride or silicon oxynitride, and its thickness range is preferably 10-20 nanometers; Perform ion implantation afterwards, A charge compensation region 205 of the second doping type is formed in the silicon epitaxial layer at the bottom of the U-shaped trench.
接下来，结合图7，采用各向异性的刻蚀方法，如选择等离子体刻蚀的方法，刻蚀掉U形沟槽底部的第二层绝缘薄膜204，之后进行氧化处理，在U形沟槽的底部形成厚的场氧化层206，该场氧化层206的两侧呈鸟嘴形状，之后去除第二层绝缘薄膜204。Next, in conjunction with FIG. 7, an anisotropic etching method, such as selective plasma etching, is used to etch away the second layer of insulating film 204 at the bottom of the U-shaped trench, followed by oxidation treatment, and the U-shaped trench A thick field oxide layer 206 is formed at the bottom of the groove, and both sides of the field oxide layer 206 are in the shape of a bird's beak, and then the second insulating film 204 is removed.
根据需要，在等离子体刻蚀掉U形沟槽底部的第二层绝缘薄膜204后，可以继续刻蚀掉U形沟槽底部的第一层绝缘薄膜203，然后进行10-100纳米厚度的硅外延层的刻蚀，从而在U形沟槽的底部形成一个开口宽度小于U形沟槽开口宽度的凹槽，如图8所示；之后再进行场氧化层206的氧化，形成如图9所示的结构。由图9和图7可知，在U形沟槽的底部形成一个凹槽后再进行场氧化层氧化，可以使得场氧化应力过渡区得到延长。According to requirements, after the second layer of insulating film 204 at the bottom of the U-shaped groove is etched by plasma, the first layer of insulating film 203 at the bottom of the U-shaped groove can be continuously etched, and then silicon with a thickness of 10-100 nanometers is formed. Etching of the epitaxial layer, thereby forming a groove with an opening width smaller than the opening width of the U-shaped trench at the bottom of the U-shaped trench, as shown in FIG. 8 ; structure shown. It can be seen from FIG. 9 and FIG. 7 that after forming a groove at the bottom of the U-shaped groove, the field oxide layer is oxidized, which can extend the field oxidation stress transition region.
根据需要，电荷补偿区205也可以在刻蚀第二层绝缘204后或者形成凹槽后通过离子注入形成。According to needs, the charge compensation region 205 can also be formed by ion implantation after etching the second layer of insulation 204 or forming grooves.
接下来，以图7所示结构继续描述本发明的一种U形沟槽的功率器件的制造工艺。Next, continue to describe the manufacturing process of a U-shaped trench power device of the present invention with the structure shown in FIG. 7 .
结合图10，完全蚀掉硬掩膜层202，并清洗掉U形沟槽两个侧壁上的第一层绝缘薄膜203，然后进行热氧化在U形沟槽的两个侧壁上形成薄的栅氧化层207。10, the hard mask layer 202 is completely etched away, and the first layer of insulating film 203 on the two side walls of the U-shaped groove is cleaned, and then thermal oxidation is performed to form a thin film on the two side walls of the U-shaped groove. gate oxide layer 207 .
接下来，结合图11，淀积一层多晶硅并回刻，以在U形沟槽内形成覆盖栅氧化层207和场氧化层206的多晶硅栅极208，刻蚀后的多晶硅栅极的顶部应低于U形沟槽的顶部；然后进行离子注入，在所述硅外延层内形成第二种掺杂类型的沟道区209；然后淀积绝缘层211并回刻，使得刻蚀后的绝缘层211位于多晶硅栅极的顶部并填满所述U形沟槽的顶部，该绝缘层211的材质为氧化硅或氮化硅，其厚度范围为50～500纳米；之后再进行光刻和离子注入，在沟道区209顶部形成第一种掺杂类型的源区210；然后再次进行光刻和离子注入，在沟道区209的顶部形成形成沟道区掺杂区213，最后淀积一层金属以形成与源区210和沟道区209相接触的源极金属212。Next, with reference to FIG. 11, a layer of polysilicon is deposited and etched back to form a polysilicon gate 208 covering the gate oxide layer 207 and the field oxide layer 206 in the U-shaped trench. The etched top of the polysilicon gate should be lower than the top of the U-shaped trench; then carry out ion implantation to form a channel region 209 of the second doping type in the silicon epitaxial layer; then deposit an insulating layer 211 and etch back, so that the insulating layer 211 after etching Layer 211 is located on the top of the polysilicon gate and fills the top of the U-shaped trench. The material of the insulating layer 211 is silicon oxide or silicon nitride, and its thickness ranges from 50 to 500 nanometers; implantation to form a source region 210 of the first doping type at the top of the channel region 209; then perform photolithography and ion implantation again to form a channel region doped region 213 at the top of the channel region 209, and finally deposit a layer metal to form source metal 212 in contact with source region 210 and channel region 209 .
根据需要，沟道区209的离子注入也可在硅外延层形成后接着进行，得到整个硅外延层顶部的掺杂区，后续形成的U形凹槽会将该掺杂区分开并形成器件的沟道区209。 According to needs, the ion implantation of the channel region 209 can also be carried out after the formation of the silicon epitaxial layer, to obtain the doped region on the top of the entire silicon epitaxial layer, and the U-shaped groove formed subsequently will separate the doped region and form the device. channel region 209 . the
本发明的具体实施方式需要进一步说明的是：The specific embodiment of the present invention needs to be further explained as follows:
在形成源区210时，可以不进行光刻，而通过离子注入普注的方式在沟道区209的顶部形成源区210，其结构如图12所示。然后通过光刻工艺定义沟道区接触区的位置，并对暴露的源区210进行刻蚀至露出沟道区209的表面，之后进行离子注入在沟道区209内形成沟道区接触区203，最后再淀积一层金属以形成与源区210和沟道区209相接触的源极金属212，如图13所示。采用该方法可以省略掉一步定义源区的光刻工艺，但是会增加对硅外延层的刻蚀工艺。When forming the source region 210 , photolithography may not be performed, but the source region 210 is formed on the top of the channel region 209 by ion implantation, and its structure is shown in FIG. 12 . Then, the position of the channel region contact region is defined by photolithography, and the exposed source region 210 is etched to expose the surface of the channel region 209, and then ion implantation is performed to form the channel region contact region 203 in the channel region 209. , and finally deposit a layer of metal to form the source metal 212 in contact with the source region 210 and the channel region 209 , as shown in FIG. 13 . Using this method can omit a photolithography process for defining the source region, but it will increase the etching process for the silicon epitaxial layer.
本发明的一种U形沟槽的功率器件的器件元胞可以成条状结构，也可以为井状结构。其中，条状元胞结构的俯视示意图如图14所示，井状元胞结构的俯视示意图如图15所示。The device unit cells of the U-shaped groove power device of the present invention can be in a strip structure or in a well structure. Wherein, a schematic top view of the strip-shaped cell structure is shown in FIG. 14 , and a top view schematic view of the well-shaped cell structure is shown in FIG. 15 .
本发明的具体实施方式中凡未涉到的说明属于本领域的公知技术，可参考公知技术加以实施。All descriptions that are not involved in the specific embodiments of the present invention belong to the known technology in the art and can be implemented with reference to the known technology.
以上具体实施方式及实施例是对本发明提出的一种U形沟槽的功率器件及其制造方法技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。The above specific implementation methods and examples are specific support for the technical idea of a U-shaped groove power device and its manufacturing method proposed by the present invention, and cannot limit the protection scope of the present invention. Any technical idea proposed in accordance with the present invention, Any equivalent changes or equivalent changes made on the basis of this technical solution still belong to the scope of protection of the technical solution of the present invention.
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| CN201410357005.XAPendingCN104103693A (en) | 2014-07-25 | 2014-07-25 | U-groove power device and manufacturing method thereof |
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