技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种鳍式场效应晶体管的形成方法。The invention relates to the technical field of semiconductors, in particular to a method for forming a fin field effect transistor.
背景技术Background technique
MOS晶体管通过在栅极施加电压，调节通过沟道区域的电流来产生开关信号。随着半导体技术的发展，传统的平面式MOS晶体管对沟道电流的控制能力变弱，造成严重的漏电流。鳍式场效应晶体管（Fin FET）是一种新兴的多栅器件，它一般包括凸出于半导体衬底表面的半导体鳍部，覆盖部分所述鳍部的顶部和侧壁的栅极结构，位于所述栅极结构两侧的鳍部内的源区和漏区。MOS transistors generate switching signals by regulating the current through the channel region by applying a voltage to the gate. With the development of semiconductor technology, the control ability of the traditional planar MOS transistor on the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes semiconductor fins protruding from the surface of the semiconductor substrate, and a gate structure covering part of the top and side walls of the fins. The source region and the drain region in the fins on both sides of the gate structure.
在鳍式场效应晶体管的制备过程中，通常会形成位于栅极两侧的侧墙。During the fabrication of the FinFET, sidewalls on both sides of the gate are usually formed.
图1和图2是现有技术鳍式场效应晶体管的侧墙形成过程的结构示意图。FIG. 1 and FIG. 2 are structural schematic diagrams of the formation process of the sidewall of the fin field effect transistor in the prior art.
请参考图1，提供半导体衬底100；刻蚀所述半导体衬底100形成凸出于所述半导体衬底100表面的鳍部101；形成覆盖所述半导体衬底100表面和部分所述鳍部101侧壁的隔离结构103；形成覆盖部分所述鳍部101的顶表面和侧壁的栅极102。请参考图2，形成覆盖所述鳍部101、所述栅极102和所述隔离结构103的侧墙材料层（未图示）；回刻蚀所述侧墙材料层，形成位于所述栅极102两侧的侧墙104。Please refer to FIG. 1 , providing a semiconductor substrate 100; etching the semiconductor substrate 100 to form fins 101 protruding from the surface of the semiconductor substrate 100; forming fins covering the surface of the semiconductor substrate 100 and part of the fins 101 isolating structure 103 on the sidewall; forming a gate 102 covering part of the top surface and sidewall of the fin 101 . Referring to FIG. 2 , a sidewall material layer (not shown) covering the fin 101 , the gate 102 and the isolation structure 103 is formed; the sidewall material layer is etched back to form a The side walls 104 on both sides of the pole 102.
请继续参考图2，现有技术中通过回刻蚀工艺，去除覆盖所述鳍部101顶表面和侧壁、所述栅极102顶表面和所述隔离结构103表面的侧墙材料层，保留位于所述栅极102侧壁表面的侧墙材料层形成侧墙104。但由于所述鳍部101凸出于所述半导体衬底100表面，在所述鳍部101侧壁表面也会形成侧墙材料层，在回刻蚀工艺之后，并不能完全去除位于所述鳍部101两侧的侧墙材料层。在所述鳍部101的底部与所述隔离结构103的接触部分会形成残余侧墙材料105，影响后续形成的鳍式场效应晶体管的性能。Please continue to refer to FIG. 2. In the prior art, the sidewall material layer covering the top surface and sidewall of the fin 101, the top surface of the gate 102, and the surface of the isolation structure 103 is removed through an etch-back process, leaving The sidewall material layer located on the sidewall surface of the gate 102 forms the sidewall 104 . However, since the fin portion 101 protrudes from the surface of the semiconductor substrate 100, a sidewall material layer will also be formed on the side wall surface of the fin portion 101. Layers of side wall material on both sides of the portion 101. Residual spacer material 105 will be formed at the contact portion between the bottom of the fin portion 101 and the isolation structure 103 , which will affect the performance of the subsequently formed FinFET.
其他有鳍式场效应晶体管中侧墙的形成方法还可以参考公开号为US2011/0198673A1的美国专利申请。For other methods of forming sidewalls in FinFETs, reference may also be made to US Patent Application Publication No. US2011/0198673A1.
发明内容Contents of the invention
本发明解决的问题是现有技术鳍式场效应晶体管的侧墙的形成过程中在鳍部的底部残余侧墙材料。The problem to be solved by the present invention is that the sidewall material remains at the bottom of the fin during the formation of the sidewall of the fin field effect transistor in the prior art.
为解决上述问题，本发明提供了一种鳍式场效应晶体管的形成方法，包括：提供半导体衬底，所述半导体衬底表面具有凸起的鳍部，位于所述鳍部上的栅极，所述栅极覆盖部分所述鳍部的顶部和侧壁；形成覆盖所述鳍部和所述栅极的侧墙材料层；对覆盖所述鳍部的侧墙材料层进行离子注入，形成改质侧墙材料层，所述改质侧墙材料层的刻蚀速率大于所述侧墙材料层的刻蚀速率；去除覆盖所述鳍部的改质侧墙材料层和位于所述栅极顶表面的侧墙材料层，形成位于所述栅极两侧的侧墙。In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has raised fins, a gate located on the fins, The gate covers part of the top and sidewall of the fin; forming a sidewall material layer covering the fin and the gate; performing ion implantation on the sidewall material layer covering the fin to form an improved A quality sidewall material layer, the etching rate of the modified sidewall material layer is greater than the etching rate of the sidewall material layer; the modified sidewall material layer covering the fin and the top surface of the gate are removed layer of sidewall material to form sidewalls on both sides of the grid.
可选的，所述离子注入的方向垂直于所述鳍部延伸的方向。Optionally, the direction of the ion implantation is perpendicular to the direction in which the fins extend.
可选的，所述离子注入的方向与所述半导体衬底平面的夹角为30度～70度。Optionally, the angle between the direction of the ion implantation and the plane of the semiconductor substrate is 30 degrees to 70 degrees.
可选的，所述离子注入的注入离子为氧离子、氩离子、硼离子、氙离子、砷离子、硼离子、氦离子或者氢离子。Optionally, implanted ions of the ion implantation are oxygen ions, argon ions, boron ions, xenon ions, arsenic ions, boron ions, helium ions or hydrogen ions.
可选的，所述离子注入的注入剂量为1015cm-2～1016cm-2。Optionally, the ion implantation dose is 1015 cm-2 to 1016 cm-2 .
可选的，所述离子注入的注入能量为1KeV～10KeV。Optionally, the implantation energy of the ion implantation is 1KeV˜10KeV.
可选的，所述离子注入工艺过程中，所述半导体衬底背偏置。Optionally, during the ion implantation process, the semiconductor substrate is back-biased.
可选的，所述半导体衬底背偏置的功率为200W～400W。Optionally, the back bias power of the semiconductor substrate is 200W-400W.
可选的，所述侧墙材料层的材料为氮化硅、氧化硅或者氮氧化硅。Optionally, the material of the sidewall material layer is silicon nitride, silicon oxide or silicon oxynitride.
可选的，所述栅极的材料为多晶硅。Optionally, the material of the gate is polysilicon.
可选的，去除覆盖所述鳍部的改质侧墙材料层和位于所述栅极顶表面的侧墙材料层的工艺为干法刻蚀。Optionally, the process of removing the modified sidewall material layer covering the fin and the sidewall material layer located on the top surface of the gate is dry etching.
可选的，所述干法刻蚀工艺为反应离子刻蚀。Optionally, the dry etching process is reactive ion etching.
可选的，还包括在所述栅极两侧的鳍部内形成源区和漏区。Optionally, it also includes forming a source region and a drain region in the fins on both sides of the gate.
可选的，所述源区和漏区为嵌入式源区和漏区。Optionally, the source region and the drain region are embedded source regions and drain regions.
可选的，所述嵌入式源区和漏区的材料为硅、锗硅或者碳化硅。Optionally, the material of the embedded source region and drain region is silicon, silicon germanium or silicon carbide.
可选的，所述嵌入式源区和漏区掺杂有N型或者P型杂质。Optionally, the embedded source region and drain region are doped with N-type or P-type impurities.
可选的，还包括在形成源区和漏区之后，形成覆盖所述半导体衬底、鳍部和侧墙的介质层，所述介质层的顶表面与所述栅极的顶表面齐平。Optionally, after forming the source region and the drain region, forming a dielectric layer covering the semiconductor substrate, fins and sidewalls, the top surface of the dielectric layer is flush with the top surface of the gate.
可选的，还包括在形成介质层之后，去除所述栅极，形成开口，所述开口暴露出部分所述鳍部的顶表面。Optionally, after forming the dielectric layer, removing the gate to form an opening, the opening exposes part of the top surface of the fin.
可选的，还包括：在所述开口内形成高介电常数栅介质层，在所述高介电常数栅介质层上形成金属栅极。Optionally, the method further includes: forming a high dielectric constant gate dielectric layer in the opening, and forming a metal gate on the high dielectric constant gate dielectric layer.
可选的，所述高介电常数栅介质层的材料为HfO2、Al2O3、ZrO2、HfSiO、HfSiON、HfTaO和HfZrO中的一种或几种。Optionally, the material of the high dielectric constant gate dielectric layer is one or more of HfO2 , Al2 O3 , ZrO2 , HfSiO, HfSiON, HfTaO and HfZrO.
与现有技术相比，本发明技术方案具有以下优点：Compared with the prior art, the technical solution of the present invention has the following advantages:
本发明实施例的鳍式场效应晶体管的形成方法中，在形成覆盖鳍部和栅极的侧墙材料层后，对覆盖所述鳍部的侧墙材料层进行离子注入，可以破坏所述鳍部两侧以及顶部的侧墙材料层的化学键，降低侧墙材料层的晶格质量，改变侧墙材料层的组分，形成改质侧墙材料层，可以使覆盖所述鳍部的改质侧墙材料层的刻蚀速率大于覆盖所述栅极的侧墙材料层的刻蚀速率。在后续回刻蚀侧墙材料层形成侧墙的工艺中，有利于将覆盖所述鳍部的改质侧墙材料层去除干净，仅在所述栅极两侧形成侧墙。In the method for forming a fin field effect transistor according to the embodiment of the present invention, after forming the sidewall material layer covering the fin and the gate, performing ion implantation on the sidewall material layer covering the fin can destroy the fin The chemical bonds of the side wall material layer on both sides and top of the fin can reduce the lattice quality of the side wall material layer, change the composition of the side wall material layer, and form a modified side wall material layer, which can make the modification covering the fin part The etching rate of the sidewall material layer is greater than the etching rate of the sidewall material layer covering the gate. In the subsequent process of etching back the sidewall material layer to form sidewalls, it is beneficial to remove the modified sidewall material layer covering the fins, and only form sidewalls on both sides of the gate.
进一步的，本实施例的鳍式场效应晶体管的形成方法中，对覆盖所述鳍部的侧墙材料层进行离子注入的方向垂直于所述鳍部的延伸方向，所述鳍部的延伸方向是指待形成鳍式场效应晶体管中从源区到漏区或者从漏区到源区的方向。由于所述离子注入的方向垂直于鳍部的延伸方向，因此所述离子注入过程中，离子更多的被注入到覆盖所述鳍部的侧墙材料层，而较少注入到位于所述栅极两侧的侧墙材料层，使得在覆盖所述鳍部的侧墙材料层的材料性能发生改变形成改质侧墙材料层，而对覆盖所述栅极的侧墙材料层的影响较小。Further, in the method for forming the fin field effect transistor of this embodiment, the direction of ion implantation to the sidewall material layer covering the fin is perpendicular to the extending direction of the fin, and the extending direction of the fin is Refers to the direction from the source region to the drain region or from the drain region to the source region in the fin field effect transistor to be formed. Since the direction of the ion implantation is perpendicular to the extending direction of the fin, during the ion implantation, more ions are implanted into the sidewall material layer covering the fin, and less into the The sidewall material layers on both sides of the pole, so that the material properties of the sidewall material layers covering the fins are changed to form a modified sidewall material layer, and the impact on the sidewall material layers covering the gate is small .
进一步的，本实施例的鳍式场效应晶体管的形成方法中，对覆盖所述鳍部的侧墙材料层进行离子注入的过程中，所述半导体衬底背偏置。由于所述鳍部与所述半导体衬底的连接方式是一体的，所述半导体衬底被背偏置于负电位时，所述鳍部也被背偏置于负电位；而所述栅极与所述半导体衬底之间具有伪栅介质层，所述栅极的电位高于所述半导体衬底的电位，也高于所述鳍部的电位。在离子注入工艺过程中，带正电荷的注入离子更容易到达负电位的鳍部对覆盖所述鳍部的侧墙材料层进行离子注入，而较少到达处于较高电位的栅极对覆盖所述栅极的侧墙材料层进行离子注入。Further, in the method for forming the fin field effect transistor of this embodiment, during the ion implantation process of the sidewall material layer covering the fin, the semiconductor substrate is back-biased. Since the connection between the fin and the semiconductor substrate is integral, when the semiconductor substrate is back-biased at a negative potential, the fin is also back-biased at a negative potential; and the gate There is a dummy gate dielectric layer between the semiconductor substrate and the potential of the gate is higher than that of the semiconductor substrate and also higher than that of the fin. During the ion implantation process, positively charged implanted ions are more likely to reach the negative potential fins for ion implantation on the sidewall material layer covering the fins, and less likely to reach the higher potential gate pair covering the fins. Ion implantation is performed on the side wall material layer of the grid.
附图说明Description of drawings
图1和图2是现有技术鳍式场效应晶体管的形成过程中部分步骤的结构示意图；1 and 2 are structural schematic diagrams of some steps in the formation process of the prior art fin field effect transistor;
图3至图8是本发明实施例的鳍式场效应晶体管的形成过程的结构示意图。FIG. 3 to FIG. 8 are structural schematic diagrams of the forming process of the fin field effect transistor according to the embodiment of the present invention.
具体实施方式detailed description
由背景技术可知，现有技术鳍式场效应晶体管的侧墙的形成过程中在鳍部的底部会残余侧墙材料。It can be seen from the background art that, in the prior art, during the formation of the sidewall of the fin field effect transistor, there will be residual sidewall material at the bottom of the fin.
本发明的发明人通过研究现有技术鳍式场效应晶体管中侧墙的形成工艺，请继续参考图1和图2，发现现有技术在形成覆盖所述鳍部101和所述栅极102的侧墙材料层后，直接对所述侧墙材料层进行回刻蚀形成侧墙104。但由于所述鳍部101凸出于所述半导体衬底100表面，且刻蚀通常为各向异性的干法刻蚀，因此在回刻蚀过程后，位于所述鳍部100两侧的侧墙材料层不能被完全去除，影响后续形成鳍式场效应晶体管的性能。进一步的，本发明的发明人研究了离子注入工艺对侧墙材料性能的影响，发现注入离子可以破坏侧墙材料的化学键，降低侧墙材料层的晶格质量，改变侧墙材料层的组分，进而改变侧墙材料的刻蚀速率。The inventors of the present invention have studied the formation process of the sidewall in the prior art fin field effect transistor, please continue to refer to FIG. 1 and FIG. After the sidewall material layer is formed, the sidewall material layer is directly etched back to form the sidewall 104 . However, since the fins 101 protrude from the surface of the semiconductor substrate 100, and the etching is generally anisotropic dry etching, after the etch-back process, the sides located on both sides of the fins 100 The wall material layer cannot be completely removed, which affects the performance of the subsequently formed FinFET. Further, the inventors of the present invention have studied the influence of ion implantation process on the performance of the sidewall material, and found that implanting ions can destroy the chemical bonds of the sidewall material, reduce the lattice quality of the sidewall material layer, and change the composition of the sidewall material layer , and then change the etch rate of the sidewall material.
基于以上研究，本发明的发明人提出了一种鳍式场效应晶体管的形成方法，在形成覆盖鳍部和栅极的侧墙材料层后，对覆盖所述鳍部的侧墙材料层进行离子注入，形成改质侧墙材料层，可以使覆盖所述鳍部的改质侧墙材料层的刻蚀速率大于覆盖所述栅极的侧墙材料层的刻蚀速率，在后续回刻蚀侧墙材料层形成侧墙的工艺中，有利于将覆盖所述鳍部的改质侧墙材料层去除干净，仅在所述栅极两侧形成侧墙。Based on the above studies, the inventors of the present invention have proposed a method for forming a fin field effect transistor. After forming the sidewall material layer covering the fin and the gate, ionizing the sidewall material layer covering the fin injection to form a modified sidewall material layer, which can make the etching rate of the modified sidewall material layer covering the fin be greater than the etching rate of the sidewall material layer covering the gate. In the process of forming the sidewall by the wall material layer, it is beneficial to remove the modified sidewall material layer covering the fin, and only form the sidewall on both sides of the gate.
下面结合附图详细地描述具体实施例，上述的目的和本发明的优点将更加清楚。The specific embodiments will be described in detail below in conjunction with the accompanying drawings, and the above-mentioned purpose and advantages of the present invention will be more clear.
图3至图8是本发明实施例的鳍式场效应晶体管的形成过程的结构示意图。FIG. 3 to FIG. 8 are structural schematic diagrams of the forming process of the fin field effect transistor according to the embodiment of the present invention.
请参考图3，提供半导体衬底200，所述半导体衬底200表面具有凸起的鳍部201，位于所述鳍部201上的栅极202，所述栅极202覆盖部分所述鳍部201的顶部和侧壁。Referring to FIG. 3 , a semiconductor substrate 200 is provided, the surface of the semiconductor substrate 200 has a raised fin 201, a gate 202 located on the fin 201, the gate 202 covers part of the fin 201 top and side walls.
所述半导体衬底200可以是硅或者绝缘体上硅（SOI），所述半导体衬底200也可以是锗、锗硅、砷化镓或者绝缘体上锗。本实施例中，所述半导体衬底200为硅衬底。所述半导体衬底200表面具有凸起的鳍部201，所述鳍部201与所述半导体衬底200的连接方式是一体的，例如所述鳍部201是通过对所述半导体衬底200刻蚀后所形成的凸起结构。The semiconductor substrate 200 may be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 200 may also be germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. In this embodiment, the semiconductor substrate 200 is a silicon substrate. The surface of the semiconductor substrate 200 has a protruding fin 201, the connection of the fin 201 and the semiconductor substrate 200 is integral, for example, the fin 201 is formed by engraving the semiconductor substrate 200 The raised structure formed after etching.
本实施例中，还包括位于所述半导体衬底200表面，且覆盖部分所述鳍部201侧壁的隔离结构203，所述隔离结构203用于隔离所述半导体衬底200上的不同鳍部。本实施例中，所述隔离结构203为浅沟槽隔离结构（STI），所述浅沟槽隔离结构的材料为氧化硅，所述浅沟槽隔离结构的形成方法可以参考现有工艺，在此不再赘述。In this embodiment, an isolation structure 203 located on the surface of the semiconductor substrate 200 and covering part of the sidewall of the fin 201 is also included, and the isolation structure 203 is used to isolate different fins on the semiconductor substrate 200 . In this embodiment, the isolation structure 203 is a shallow trench isolation structure (STI), the material of the shallow trench isolation structure is silicon oxide, the formation method of the shallow trench isolation structure can refer to the existing process, in This will not be repeated here.
所述栅极202位于所述鳍部201上，覆盖部分所述鳍部201的顶部和侧壁，且覆盖部分所述隔离结构203。本实施例中所述栅极202的材料为多晶硅，所述栅极202作为伪栅极。本实施例中还包括位于所述半导体衬底200表面的伪栅介质层（未示出），所述栅极202位于所述伪栅介质层上。在后栅（gate-last）工艺中，后续去除所述伪栅极和伪栅介质层，再在原伪栅极和伪栅介质层的位置形成高介电常数栅介质层和位于所述高介电常数栅介质层上的金属栅极，形成高K金属栅结构（HKMG）结构，有利于提高晶体管的击穿电压，减小漏电流，提高晶体管性能。The gate 202 is located on the fin 201 , covers part of the top and sidewall of the fin 201 , and covers part of the isolation structure 203 . In this embodiment, the material of the gate 202 is polysilicon, and the gate 202 is used as a dummy gate. This embodiment also includes a dummy gate dielectric layer (not shown) on the surface of the semiconductor substrate 200 , and the gate 202 is located on the dummy gate dielectric layer. In the gate-last (gate-last) process, the dummy gate and the dummy gate dielectric layer are subsequently removed, and then a high dielectric constant gate dielectric layer is formed at the position of the original dummy gate and the dummy gate dielectric layer and a The metal gate on the electric constant gate dielectric layer forms a high-K metal gate structure (HKMG) structure, which is beneficial to improve the breakdown voltage of the transistor, reduce the leakage current, and improve the performance of the transistor.
在其他实施例中，所述栅极与所述半导体衬底之间还具有栅介质层，所述栅极的材料为多晶硅，所述栅介质层的材料为氧化硅，所述栅极和栅介质层共同构成鳍式场效应晶体管的栅极结构。In other embodiments, there is a gate dielectric layer between the gate and the semiconductor substrate, the material of the gate is polysilicon, the material of the gate dielectric layer is silicon oxide, and the gate and gate The dielectric layer together constitutes the gate structure of the fin field effect transistor.
请参考图4，图4为图3沿AA1方向的剖面结构示意图，形成覆盖所述鳍部201和所述栅极202侧墙材料层204。Please refer to FIG. 4 . FIG. 4 is a schematic cross-sectional structural view along the direction AA1 of FIG. 3 , forming a sidewall material layer 204 covering the fin 201 and the gate 202 .
具体的，采用物理气相沉积、化学气相沉积或者原子层沉积工艺形成覆盖所述鳍部201和所述栅极202的侧墙材料层204。本实施例中，采用原子层沉积工艺形成所述侧墙材料层204。原子层沉积工艺通过将气相前驱物脉冲交替地通入反应腔室，在沉积基底上化学吸附并反应，单层生长形成沉积薄膜，厚度可控性好，薄膜保形性好。由于后续的侧墙通过刻蚀所述侧墙材料层204形成，所述侧墙的宽度与所述侧墙材料层204的厚度相关，因此，采用原子层沉积工艺形成所述侧墙材料层204，有利于精确控制后续形成的侧墙的宽度。所述侧墙材料层204的厚度根据待形成侧墙的宽度和具体的工艺确定，所述侧墙材料层204的材料为氮化硅、氧化硅或者氮氧化硅。本实施例中，所述侧墙材料层204的厚度为50nm～500nm，所述侧墙材料层204的材料为氮化硅。Specifically, the sidewall material layer 204 covering the fin 201 and the gate 202 is formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition. In this embodiment, the side wall material layer 204 is formed by atomic layer deposition process. The atomic layer deposition process pulses gas-phase precursors into the reaction chamber alternately, chemically adsorbs and reacts on the deposition substrate, and grows as a single layer to form a deposited film with good thickness controllability and good shape retention. Since the subsequent sidewall is formed by etching the sidewall material layer 204, the width of the sidewall is related to the thickness of the sidewall material layer 204, therefore, the sidewall material layer 204 is formed by an atomic layer deposition process , which is beneficial to accurately control the width of the subsequent side wall. The thickness of the sidewall material layer 204 is determined according to the width of the sidewall to be formed and the specific process, and the material of the sidewall material layer 204 is silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, the thickness of the sidewall material layer 204 is 50 nm˜500 nm, and the material of the sidewall material layer 204 is silicon nitride.
请参考图5，图5为图3沿BB1方向的剖面结构示意图，对覆盖所述鳍部201的侧墙材料层204（参考图4）进行离子注入，形成改质侧墙材料层205，所述改质侧墙材料层205的刻蚀速率大于所述侧墙材料层204的刻蚀速率。。Please refer to FIG. 5. FIG. 5 is a schematic cross-sectional structure diagram along the BB1 direction of FIG. The etching rate of the modified sidewall material layer 205 is greater than the etching rate of the sidewall material layer 204 . .
在形成覆盖所述鳍部201和所述栅极202（参考图4）的侧墙材料层204后，由于所述鳍部201凸出于所述半导体衬底200表面，所述侧墙材料层204不仅形成于所述栅极202的侧壁表面，也形成于所述鳍部201的侧壁表面。若采用现有技术回刻蚀所述侧墙材料层204，则在形成位于所述栅极202两侧的侧墙的同时，也会在所述鳍部201的底部残余侧墙材料，影响晶体管性能。因此，在本实施例中，通过对覆盖所述鳍部201的侧墙材料层204进行离子注入，破环所述侧墙材料层204的化学键，降低所述侧墙材料层204的晶格质量，改变所述侧墙材料层204的组分，形成改质侧墙材料层205，使覆盖所述鳍部201的改质侧墙材料层205的刻蚀速率大于覆盖所述栅极202的侧墙材料层204的刻蚀速率，有利于在后续回刻蚀工艺中将覆盖所述鳍部201的改质侧墙材料层205去除干净。After forming the sidewall material layer 204 covering the fin 201 and the gate 202 (refer to FIG. 4 ), since the fin 201 protrudes from the surface of the semiconductor substrate 200, the sidewall material layer 204 is formed not only on the sidewall surface of the gate 202 but also on the sidewall surface of the fin 201 . If the existing technology is used to etch back the sidewall material layer 204, while forming the sidewalls on both sides of the gate 202, the sidewall material will also remain at the bottom of the fin 201, which will affect the transistor. performance. Therefore, in this embodiment, by performing ion implantation on the sidewall material layer 204 covering the fin portion 201, the chemical bonds of the sidewall material layer 204 are broken, and the lattice quality of the sidewall material layer 204 is reduced. , changing the composition of the sidewall material layer 204 to form a modified sidewall material layer 205, so that the etching rate of the modified sidewall material layer 205 covering the fin 201 is greater than that of the side covering the gate 202 The etch rate of the wall material layer 204 is beneficial to remove the modified sidewall material layer 205 covering the fin portion 201 in the subsequent etch-back process.
本实施例中，对覆盖所述鳍部201的侧墙材料层204进行离子注入的方向垂直于所述鳍部201延伸的方向。所述鳍部201延伸的方向是指待形成鳍式场效应晶体管中从源区到漏区或者从漏区到源区的方向。由于所述离子注入的方向垂直于鳍部201延伸的方向，因此所述离子注入过程中，离子更多的被注入到覆盖所述鳍部201的侧墙材料层204，而较少注入到位于所述栅极202两侧的侧墙材料层204，使得覆盖所述鳍部201的侧墙材料层204的材料性能发生改变形成改质侧墙材料层205的同时，对覆盖所述栅极202的侧墙材料层204的影响较小。本实施例中，所述离子注入的方向垂直于所述鳍部201延伸的方向，且所述离子注入的方向与所述半导体衬底200平面的夹角为30度～70度。需要说明的是，在离子注入的过程中，可以在与所述鳍部201延伸方向垂直的平面内旋转注入角度，对所述鳍部201两侧的侧墙材料层204进行均匀注入。In this embodiment, the ion implantation direction of the sidewall material layer 204 covering the fin portion 201 is perpendicular to the extending direction of the fin portion 201 . The extending direction of the fin portion 201 refers to the direction from the source region to the drain region or from the drain region to the source region in the FinFET to be formed. Since the ion implantation direction is perpendicular to the extending direction of the fin portion 201, during the ion implantation process, more ions are implanted into the sidewall material layer 204 covering the fin portion 201, and less into the The sidewall material layer 204 on both sides of the gate 202 changes the material properties of the sidewall material layer 204 covering the fin 201 to form a modified sidewall material layer 205 , while the sidewall material layer 204 covering the gate 202 The sidewall material layer 204 has less influence. In this embodiment, the direction of the ion implantation is perpendicular to the direction in which the fins 201 extend, and the included angle between the direction of the ion implantation and the plane of the semiconductor substrate 200 is 30 degrees to 70 degrees. It should be noted that, during the ion implantation process, the implantation angle can be rotated in a plane perpendicular to the extending direction of the fin portion 201 to uniformly implant the sidewall material layers 204 on both sides of the fin portion 201 .
所述离子注入的注入离子为氧离子、氩离子、硼离子、氙离子、砷离子、硼离子、氦离子或者氢离子。所述离子注入的注入剂量为1015cm-2～1016cm-2，所述离子注入的注入能量为1KeV～10KeV。本实施例中，所述侧墙材料层204的材料为氮化硅，所述离子注入工艺的注入离子为氧离子，所述氧离子被注入氮化硅侧墙材料层后，不仅会破坏氮化硅材料中的氮-硅化学键，降低氮化硅材料的晶格质量，还会在氮化硅材料中引入氧元素，改变氮化硅材料的化学组分，形成改质侧墙材料层205。由于所述改质侧墙材料层205的晶格质量降低，化学组分变化，使得其刻蚀速率在后续的回刻蚀工艺中大于所述侧墙材料层204的刻蚀速率，可以被去除干净。The implanted ions of the ion implantation are oxygen ions, argon ions, boron ions, xenon ions, arsenic ions, boron ions, helium ions or hydrogen ions. The implantation dose of the ion implantation is 1015 cm−2 to 1016 cm−2 , and the implantation energy of the ion implantation is 1KeV˜10KeV. In this embodiment, the material of the sidewall material layer 204 is silicon nitride, and the implanted ions in the ion implantation process are oxygen ions. After the oxygen ions are implanted into the silicon nitride sidewall material layer, it will not only destroy the nitrogen The nitrogen-silicon chemical bond in the silicon nitride material reduces the lattice quality of the silicon nitride material, and introduces oxygen element into the silicon nitride material to change the chemical composition of the silicon nitride material to form a modified sidewall material layer 205 . As the lattice quality of the modified sidewall material layer 205 decreases and the chemical composition changes, its etching rate is greater than the etching rate of the sidewall material layer 204 in the subsequent etch-back process, and can be removed. clean.
另外，本实施例中，在对覆盖所述鳍部201的侧墙材料层进行离子注入的过程中，所述半导体衬底200背偏置（Back bias），背偏置功率为200W～400W。本实施例中，由于所述鳍部201与所述半导体衬底200的连接方式是一体的，所述鳍部201为通过对所述半导体鳍部200刻蚀后形成的凸起结构，因此在所述半导体衬底200被背偏置于负电位时，所述鳍部201也被背偏置于负电位；而所述栅极202与所述半导体衬底200之间具有伪栅介质层，因此所述栅极202的电位高于所述半导体衬底200的电位，也高于所述鳍部201的电位。在离子注入工艺过程中，带正电荷的注入离子更容易到达负电位的鳍部201，对覆盖所述鳍部201的侧墙材料层204进行离子注入，而较少到达处于较高电位的栅极202，对覆盖所述栅极202的侧墙材料层204进行离子注入。因此，在离子注入工艺过程中，对所述半导体衬底200背偏置有利于在对覆盖所述鳍部201的侧墙材料层204进行离子注入的同时，减小对覆盖所述栅极202的侧墙材料层204的影响。In addition, in this embodiment, during the ion implantation process of the sidewall material layer covering the fin portion 201 , the semiconductor substrate 200 is back biased, and the back bias power is 200W˜400W. In this embodiment, since the connection of the fin 201 and the semiconductor substrate 200 is integral, the fin 201 is a raised structure formed by etching the semiconductor fin 200 , so in When the semiconductor substrate 200 is back-biased at a negative potential, the fin portion 201 is also back-biased at a negative potential; and there is a dummy gate dielectric layer between the gate 202 and the semiconductor substrate 200, Therefore, the potential of the gate 202 is higher than that of the semiconductor substrate 200 and also higher than that of the fin 201 . During the ion implantation process, positively charged implanted ions are more likely to reach the fin portion 201 at a negative potential to perform ion implantation on the sidewall material layer 204 covering the fin portion 201, and less likely to reach the gate at a higher potential. electrode 202 , performing ion implantation on the side wall material layer 204 covering the gate 202 . Therefore, during the ion implantation process, back-biasing the semiconductor substrate 200 is beneficial to performing ion implantation on the sidewall material layer 204 covering the fin portion 201 while reducing the impact on the gate electrode 202. The effect of the sidewall material layer 204 .
请参考图6，去除覆盖所述鳍部201的改质侧墙材料层205（参考图5）和位于所述栅极202顶表面的侧墙材料层204（参考图4），形成位于所述栅极202两侧的侧墙206。Please refer to FIG. 6 , remove the modified spacer material layer 205 covering the fin 201 (refer to FIG. 5 ) and the sidewall material layer 204 on the top surface of the gate 202 (refer to FIG. 4 ), forming a sidewalls 206 on both sides of the gate 202 .
具体的，去除覆盖所述鳍部201的改质侧墙材料层205和位于所述栅极202顶表面的侧墙材料层204的工艺为干法刻蚀。本实施例中所述干法刻蚀工艺为反应离子刻蚀，所述反应离子刻蚀工艺采用CF4、CHF3和O2的混合气体。由于反应离子刻蚀工艺为各向异性刻蚀，具有较好的方向性，无需形成掩膜，回刻蚀工艺之后，仅位于所述栅极202两侧的侧墙材料层204保留形成侧墙206，位于所述栅极202顶表面的侧墙材料层204、覆盖所述鳍部201的改质侧墙材料层205以及其他区域的侧墙材料被去除。由于通过上述的离子注入步骤，覆盖所述鳍部201的改质侧墙材料层205的刻蚀速率大于覆盖所述栅极202的侧墙材料层204的刻蚀速率，更容易被去除，因此在刻蚀工艺后，覆盖所述鳍部201的改质侧墙材料层205可以被完全去除，不会有残留。Specifically, the process of removing the modified sidewall material layer 205 covering the fin portion 201 and the sidewall material layer 204 located on the top surface of the gate 202 is dry etching. The dry etching process described in this embodiment is reactive ion etching, and the reactive ion etching process uses a mixed gas of CF4 , CHF3 and O2 . Since the reactive ion etching process is anisotropic etching, it has good directionality and does not need to form a mask. After the etch-back process, only the sidewall material layers 204 located on both sides of the gate 202 remain to form sidewalls. 206 , the sidewall material layer 204 on the top surface of the gate 202 , the modified sidewall material layer 205 covering the fin 201 , and the sidewall material in other areas are removed. Due to the aforementioned ion implantation step, the etching rate of the modified sidewall material layer 205 covering the fin portion 201 is greater than the etching rate of the sidewall material layer 204 covering the gate 202, and is easier to be removed, therefore After the etching process, the modified sidewall material layer 205 covering the fin portion 201 can be completely removed without any residue.
请参考图7，图7为图6沿AA1方向的剖面结构示意图，在所述栅极202两侧鳍部201内形成源区和漏区207。Please refer to FIG. 7 . FIG. 7 is a schematic cross-sectional structure view along the direction AA1 of FIG. 6 , in which a source region and a drain region 207 are formed in the fins 201 on both sides of the gate 202 .
本实施例中，所述源区和漏区207为嵌入式源区和漏区。所述嵌入式源区和漏区的形成工艺包括：去除所述栅极202两侧的部分鳍部201，形成凹槽（未图示）；在所述凹槽内选择性外延半导体材料，形成嵌入式源区和漏区。所述的选择性外延工艺可以为分子束外延（MBE）或者超高真空化学气相沉积（UHVCVD），所述半导体材料可以为硅、锗硅或者碳化硅，所形成的嵌入式源区和漏区的材料也为硅、锗硅或者碳化硅。In this embodiment, the source and drain regions 207 are embedded source and drain regions. The formation process of the embedded source region and drain region includes: removing part of the fins 201 on both sides of the gate 202 to form a groove (not shown); selectively epitaxial semiconductor material in the groove to form Embedded source and drain regions. The selective epitaxy process can be molecular beam epitaxy (MBE) or ultra-high vacuum chemical vapor deposition (UHVCVD), and the semiconductor material can be silicon, germanium silicon or silicon carbide, and the embedded source and drain regions formed The material is also silicon, silicon germanium or silicon carbide.
当所述待形成鳍式场效应晶体管为NMOS晶体管时，所述嵌入式源区和漏区的材料为硅或者碳化硅，所述硅或者碳化硅掺杂有N型杂质；当所述待形成鳍式场效应晶体管为PMOS晶体管时，所述嵌入式源区和漏区的材料为硅或锗硅，所述硅或者锗硅掺杂有P型杂质。当所述嵌入式源区和漏区的材料为硅时，可以形成抬高的源区和漏区，使所述嵌入式源区和漏区的体积大于所述被刻蚀鳍部201的体积，有利于后续源区和漏区上导电插塞的形成，防止由于鳍部201的体积过小导致导电插塞与源区和漏区的接触不良。在NMOS晶体管中，当所述嵌入式源区和漏区的材料为碳化硅时，由于碳化硅的晶格常数小于硅的晶格常数，可以在NMOS鳍式场效应晶体管的沟道区域引入拉伸应力，提高电子迁移率；在PMOS晶体管中，当所述嵌入式源区和漏区的材料为锗硅时，由于锗硅的晶格常数大于硅的晶格常数，可以在PMOS晶体管的沟道区域引入压缩应力，提高空穴迁移率。When the fin field effect transistor to be formed is an NMOS transistor, the material of the embedded source region and drain region is silicon or silicon carbide, and the silicon or silicon carbide is doped with N-type impurities; when the to-be-formed When the FinFET is a PMOS transistor, the material of the embedded source region and the drain region is silicon or silicon germanium, and the silicon or silicon germanium is doped with P-type impurities. When the material of the embedded source region and drain region is silicon, raised source region and drain region can be formed, so that the volume of the embedded source region and drain region is larger than the volume of the etched fin 201 , which is beneficial to the subsequent formation of conductive plugs on the source region and the drain region, and prevents poor contact between the conductive plugs and the source region and the drain region due to the too small volume of the fin portion 201 . In the NMOS transistor, when the material of the embedded source region and the drain region is silicon carbide, since the lattice constant of silicon carbide is smaller than that of silicon, a pull can be introduced in the channel region of the NMOS fin field effect transistor. Stretch stress, improve electron mobility; In PMOS transistor, when the material of described embedded source area and drain area is germanium silicon, because the lattice constant of germanium silicon is greater than that of silicon, can be in the trench of PMOS transistor The compressive stress is introduced into the channel region to increase the hole mobility.
在其他实施例中，也可以直接对所述栅极两侧的鳍部进行N型或P型离子注入，形成源区和漏区。In other embodiments, N-type or P-type ion implantation may also be directly performed on the fins on both sides of the gate to form a source region and a drain region.
请参考图8，形成覆盖所述半导体衬底200、鳍部201和侧墙206的介质层208，所述介质层208的顶表面与所述栅极202（参考图7）的顶表面齐平；去除所述栅极202，形成开口（未图示），所述开口暴露出部分所述鳍部201的顶表面；在所述开口内形成高介电常数栅介质层（未图示），在所述高介电常数栅介质层上形成金属栅极209。Referring to FIG. 8 , a dielectric layer 208 covering the semiconductor substrate 200 , fins 201 and sidewalls 206 is formed, and the top surface of the dielectric layer 208 is flush with the top surface of the gate 202 (see FIG. 7 ). ; removing the gate 202 to form an opening (not shown), the opening exposes part of the top surface of the fin 201; forming a high dielectric constant gate dielectric layer (not shown) in the opening, A metal gate 209 is formed on the high dielectric constant gate dielectric layer.
具体的，形成所述介质层208的工艺包括：形成覆盖所述半导体衬底200、鳍部201、栅极202和侧墙206的介质材料层（未图示），所述介质材料层的材料可以为氧化硅或者氮化硅；采用化学机械抛光工艺研磨所述介质材料层，直至暴露出所述栅极202的顶表面，形成与所述栅极202顶表面齐平的介质层208，所述介质层208起到电学隔离的作用。Specifically, the process of forming the dielectric layer 208 includes: forming a dielectric material layer (not shown) covering the semiconductor substrate 200, fins 201, gates 202 and sidewalls 206, the material of the dielectric material layer It can be silicon oxide or silicon nitride; the dielectric material layer is ground by a chemical mechanical polishing process until the top surface of the gate 202 is exposed to form a dielectric layer 208 flush with the top surface of the gate 202, so The dielectric layer 208 plays the role of electrical isolation.
本实施中，所述栅极202为伪栅极，在后栅（gate-last）工艺中，栅介质层和栅电极层在源区和漏区形成之后形成，可以减小栅介质层和栅电极层的热预算，有利于获得理想的阈值电压，提高晶体管性能。In this implementation, the gate 202 is a dummy gate. In the gate-last process, the gate dielectric layer and the gate electrode layer are formed after the source region and the drain region are formed, which can reduce the size of the gate dielectric layer and the gate electrode layer. The thermal budget of the electrode layer is conducive to obtaining an ideal threshold voltage and improving transistor performance.
本实施例中，所述半导体衬底200与所述栅极202之间还具有伪栅介质层，因此在去除所述栅极202的同时去除所述伪栅介质层，形成开口。所述开口暴露出部分所述鳍部201的顶表面，在所述开口内形成高介电常数栅介质层，在所述高介电常数栅介质层上形成金属栅极209。具体的，先在所述开口内形成高介电常数栅介质材料层，再在所述高介电常数栅介质材料层上形成金属栅材料层，所述金属栅材料层填充满所述开口，采用化学机械抛光工艺研磨所述金属栅材料层和所述高介电常数栅介质层，直至暴露出所述介质层208表面，形成高介电常数栅介质层和金属栅极209。形成所述高介电常数栅介质材料层和所述金属栅材料层的工艺为化学气相沉积或者原子层沉积，所述高介电常数栅介质层的材料为HfO2、Al2O3、ZrO2、HfSiO、HfSiON、HfTaO和HfZrO中的一种或几种，所述金属栅材料层的材料为W、Al、Cu、Ti、Ta、TaN、NiSi、CoSi、TiN、TiAl和TaSiN中的一种或几种。所述高介电常数栅介质层和金属栅极209结构，有利于提高晶体管的击穿电压，减小漏电流，提高晶体管性能。In this embodiment, there is a dummy gate dielectric layer between the semiconductor substrate 200 and the gate 202 , so the dummy gate dielectric layer is removed while removing the gate 202 to form an opening. The opening exposes part of the top surface of the fin portion 201 , a high dielectric constant gate dielectric layer is formed in the opening, and a metal gate 209 is formed on the high dielectric constant gate dielectric layer. Specifically, a high dielectric constant gate dielectric material layer is first formed in the opening, and then a metal gate material layer is formed on the high dielectric constant gate dielectric material layer, and the metal gate material layer fills the opening, The metal gate material layer and the high dielectric constant gate dielectric layer are ground by a chemical mechanical polishing process until the surface of the dielectric layer 208 is exposed to form a high dielectric constant gate dielectric layer and a metal gate 209 . The process of forming the high dielectric constant gate dielectric material layer and the metal gate material layer is chemical vapor deposition or atomic layer deposition, and the material of the high dielectric constant gate dielectric layer is HfO2 , Al2 O3 , ZrO2. One or more of HfSiO, HfSiON, HfTaO and HfZrO, the material of the metal gate material layer is one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN species or several. The structure of the high dielectric constant gate dielectric layer and the metal gate 209 is beneficial to increase the breakdown voltage of the transistor, reduce the leakage current, and improve the performance of the transistor.
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can utilize the methods and techniques disclosed above to analyze the technical aspects of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the protection of the technical solution of the present invention. scope.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310093717.0ACN104064453B (en) | 2013-03-21 | 2013-03-21 | Method for forming fin field-effect transistor |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310093717.0ACN104064453B (en) | 2013-03-21 | 2013-03-21 | Method for forming fin field-effect transistor |
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| CN104064453A CN104064453A (en) | 2014-09-24 |
| CN104064453Btrue CN104064453B (en) | 2017-05-17 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201310093717.0AActiveCN104064453B (en) | 2013-03-21 | 2013-03-21 | Method for forming fin field-effect transistor |
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