CN104063257A - System and method for FPGA automatic loading - Google Patents

Abstract

Translated fromChinese

本发明公开一种FPGA的自动加载系统及方法，具体涉及一种Norflash的多个FPGA加载方式。其采用的Norflash和TCP/IP网络技术，实现了基站内部多个FPGA代码的自动加载。该方法包括通过网络从服务器将多个FPGA代码下载到基站设备的Norflash指定存储位置；基站再次启动时，通过CPLD逻辑控制一个或多个FPGA的加载流程，从Norflash指定的存储位置读取FPGAimage配置文件，进入加载过程。此方法可以在运营商机房实现基站设备内部不同FPGA的自动加载，可以在任何时间、无需线缆的实现FPGA代码正确、快速、高效加载。

The invention discloses an FPGA automatic loading system and method, in particular to a multiple FPGA loading mode of Norflash. It adopts Norflash and TCP/IP network technology to realize the automatic loading of multiple FPGA codes inside the base station. The method comprises downloading a plurality of FPGA codes from the server to the storage location specified by Norflash of the base station equipment through the network; when the base station starts up again, the loading process of one or more FPGAs is controlled by CPLD logic, and the FPGA image configuration is read from the storage location specified by Norflash file, enter the loading process. This method can realize the automatic loading of different FPGAs inside the base station equipment in the operator's computer room, and can realize correct, fast and efficient loading of FPGA codes at any time without cables.

Description

Translated fromChinese

一种FPGA自动加载系统及方法A kind of FPGA automatic loading system and method

技术领域technical field

本发明涉及一种FPGA自动加载系统及方法，具体涉及一种Nor flash(非易失闪存)的多个FPGA(现场可编程门阵列)加载方式。The invention relates to an FPGA automatic loading system and method, in particular to a multiple FPGA (Field Programmable Gate Array) loading mode of Nor flash (non-volatile flash memory).

背景技术Background technique

随着无线通信数据量的不断增大，FPGA在基站类产品中有很大的作用，特别是越来越复杂的数据处理，所以FPGA代码加载和升级的方便性需求会变得越来越明显。As the amount of wireless communication data continues to increase, FPGAs play an important role in base station products, especially for more and more complex data processing, so the need for convenience in FPGA code loading and upgrading will become more and more obvious .

以往的FPGA程序的调试及加载，均采用各FPGA厂商推出的专用下载器，采用下载器不但价格昂贵，而且对使用环境要求高，在带电在线调试过程中极易损坏。下载程序时需要在本地将PC(个人计算机)通过USB(通用串行总线)下载线缆与FPGA相连接，一旦产品装配好后，在修改和升级FPGA程序，其加载过程会很麻烦，需在本地拆卸包装后连接下载线才能实现程序的更新；但是此过程操作不灵活且效率低下，尤其在新型基站设备的升级中弊端更为突出。In the past, the debugging and loading of FPGA programs all used special downloaders launched by various FPGA manufacturers. Using downloaders is not only expensive, but also has high requirements for the use environment, and is easily damaged during live online debugging. When downloading the program, it is necessary to connect the PC (personal computer) to the FPGA locally through the USB (universal serial bus) download cable. Once the product is assembled, the loading process will be very troublesome when modifying and upgrading the FPGA program. The update of the program can only be realized by connecting the download line after the local unpacking; however, this process is inflexible and inefficient, especially in the upgrade of new base station equipment.

发明内容Contents of the invention

针对背景技术存在的问题，本发明利用基站设备都具备的网口，采用Nor flash和TCP/IP(传输控制协议/因特网互联协议)网络技术，通过CPLD(复杂可编程逻辑器件)逻辑实现FPGA代码的正确、快速、高效加载，可以更加灵活的实现远程基站设备的FPGA代码加载。For the problems existing in the background technology, the present invention utilizes the network port that base station equipment all possesses, adopts Nor flash and TCP/IP (Transmission Control Protocol/Internet Interconnection Protocol) network technology, realizes FPGA code by CPLD (Complex Programmable Logic Device) logic The correct, fast and efficient loading can realize the FPGA code loading of remote base station equipment more flexibly.

要解决的技术问题：Technical problem to be solved:

在基站设备中，利用下载器加载FPGA不方便、不灵活、效率低，而且无法实现远程加载，多个FPGA需要多个接口、多次下载，本发明的目的在于采用Nor flash和TCP/IP网络技术，可以更加灵活的实现远程基站设备的FPGA代码正确、快速、高效加载。In the base station equipment, it is inconvenient, inflexible, and inefficient to use the downloader to load the FPGA, and remote loading cannot be realized. Multiple FPGAs require multiple interfaces and multiple downloads. The purpose of the present invention is to use Nor flash and TCP/IP network technology, it can more flexibly realize the correct, fast and efficient loading of the FPGA code of the remote base station equipment.

解决该技术问题所采用的技术方案是：The technical solution adopted to solve this technical problem is:

一种FPGA的自动加载系统，包括Nor flash、CPLD、POWERPC、FPGA；Nor flash与CPLD双向数据连接，CPLD与POWERPC双向数据连接；CPLD与FPGA双向数据连接，POWERPC与以太网口双向数据连接。An automatic loading system of FPGA, including Nor flash, CPLD, POWERPC, FPGA; Nor flash and CPLD two-way data connection, CPLD and POWERPC two-way data connection; CPLD and FPGA two-way data connection, POWERPC and Ethernet port two-way data connection.

一种基于上述系统的FPGA的自动加载方法，采用Nor flash和TCP/IP网络技术，PowerPC通过CPLD逻辑实现基站内部多个FPGA代码自动加载；A kind of automatic loading method based on the FPGA of above-mentioned system, adopts Nor flash and TCP/IP network technology, PowerPC realizes the automatic loading of a plurality of FPGA codes inside the base station by CPLD logic;

包括通过网络将FPGA代码写入Norflash和通过CPLD实现FPGA的自动加载两个过程；从设备服务器将多个FPGA代码下载到基站设备的Norflash指定存储位置；基站再次启动时，POWERPC通过CPLD从Nor flash指定的存储位置读取FPGA image配置文件，进入加载过程。Including the two processes of writing FPGA code into Norflash through the network and realizing automatic loading of FPGA through CPLD; downloading multiple FPGA codes from the device server to the Norflash designated storage location of the base station equipment; The specified storage location reads the FPGA image configuration file and enters the loading process.

具体包括以下步骤，Specifically include the following steps,

步骤1、将需要重新加载的FPGA image文件存储在服务器上；Step 1, store the FPGA image file that needs to be reloaded on the server;

步骤2、通过TCP/IP网络技术将需要升级的FPGA image文件发送到指定IP地址设备，设备中的POWERPC通过报文中IP地址判断是否为送到本机数据，如果符合则接收数据，POWERPC接收到数据后将擦除Nor flash相关存储位置，并将收到的配置文件写入Nor flash指定存储位置；Step 2. Send the FPGA image file that needs to be upgraded to the device with the specified IP address through TCP/IP network technology. The POWERPC in the device judges whether it is the data sent to the local machine through the IP address in the message. If it matches, it receives the data, and the POWERPC receives it After receiving the data, the related storage location of Nor flash will be erased, and the received configuration file will be written into the designated storage location of Nor flash;

步骤3、在设备启动过程中，POWERPC通过CPLD控制多片FPGA的加载进程，从Nor flash指定的存储位置读取需要加载FPGA image配置文件；Step 3. During device startup, POWERPC controls the loading process of multiple FPGAs through CPLD, and reads the FPGA image configuration file that needs to be loaded from the storage location specified by Nor flash;

步骤4、CPLD首先将FPGA的PROG_B管脚拉低，启动配置过程；当PROG_B拉低，FPGA开始清除自身内部RAM，在这个过程中FPGA把INIT_B引脚配低，当RAM清除完成后，INIT_B引脚变高；CPLD将INIT_B引脚作为输入监测，当该引脚变为高电平后，CPLD就将所要配置的image文件送至FPGA的DIN引脚，同时将相应的时钟CCLK送至FPGA；在这个过程中CPLD监测FPGA的DONE引脚，如果DONE引脚变为高电平，则说明FPGA加载成功，如果DONE为低电平，则重复步骤3和本步骤4，直至本片FPGA加载成功；Step 4. The CPLD first pulls down the PROG_B pin of the FPGA to start the configuration process; when PROG_B is pulled down, the FPGA starts to clear its own internal RAM. During this process, the FPGA sets the INIT_B pin low. The pin becomes high; CPLD monitors the INIT_B pin as an input, and when the pin becomes high, the CPLD sends the image file to be configured to the DIN pin of the FPGA, and at the same time sends the corresponding clock CCLK to the FPGA; During this process, the CPLD monitors the DONE pin of the FPGA. If the DONE pin becomes high, it means that the FPGA is loaded successfully. If the DONE is low, repeat step 3 and this step 4 until the FPGA is loaded successfully. ;

步骤5、POWERPC进程管理检查是否还有FPGA需要加载，如果有，则重复步骤3和步骤4；Step 5, POWERPC process management checks whether there are still FPGAs to be loaded, if so, repeat steps 3 and 4;

步骤6、无FPGA需要加载，则所有的FPGA都加载完成。Step 6. If no FPGA needs to be loaded, all FPGAs are loaded.

与现有技术相比，本发明的显著优点在于：Compared with prior art, remarkable advantage of the present invention is:

1)采用基站设备必备的网口作为FPGA代码的传输口，通过成熟的TCP/IP网络技术，实现代码正确快速的下载到目的设备端，提高了数据传输的可靠性；1) The necessary network port of the base station equipment is used as the transmission port of the FPGA code, and the mature TCP/IP network technology is used to realize the correct and fast download of the code to the destination device, which improves the reliability of data transmission;

2)采用CPLD复杂可编程逻辑器件处理FPGA代码的自动加载逻辑，实现简单、不占用其他资源；功能逻辑简单易实施，提高了加载过程的逻辑可靠性；2) CPLD complex programmable logic device is used to process the automatic loading logic of FPGA code, which is simple to implement and does not occupy other resources; the functional logic is simple and easy to implement, which improves the logical reliability of the loading process;

3)不依赖与各个厂家的FPGA下载线缆，可以实现任何时间、任何地点对基站设备的FPGA代码更新；3) It does not rely on the FPGA download cables of various manufacturers, and can update the FPGA code of the base station equipment at any time and any place;

4）采用非易失存储器Nor flash，其接口简单，可以很容易地存取其内部的每一个字节；其读取速度非常快，可以有效的减少基站的启动时间；4) Using non-volatile memory Nor flash, its interface is simple, and every byte inside it can be easily accessed; its reading speed is very fast, which can effectively reduce the start-up time of the base station;

5）PowerPC控制Nor flash的擦除、读、写等操作，实现多版本、多数量FPGA代码的存储。5) PowerPC controls Nor flash operations such as erasing, reading, and writing, and realizes the storage of multi-version and multi-quantity FPGA codes.

附图说明Description of drawings

附图1为本发明的系统实现框图，图中LBC指数据/地址复用总线，RJ45指网络接口（以太网口）。Accompanying drawing 1 is the system realization block diagram of the present invention, among the figure LBC refers to data/address multiplexing bus, RJ45 refers to network interface (Ethernet port).

附图2为本发明自动加载一个FPGA的流程框图。Accompanying drawing 2 is the flow chart of automatically loading an FPGA of the present invention.

附图3为本发明自动加载多个FPGA的流程框图。Accompanying drawing 3 is the flow chart of automatically loading multiple FPGAs of the present invention.

具体实施方式Detailed ways

本发明采用Nor flash和TCP/IP网络技术，通过CPLD逻辑实现基站内部多个FPGA代码自动加载，包括通过网络将FPGA代码写入Norflash和通过CPLD实现FPGA的自动加载两个过程。这样可以在运营商机房实现基站设备内部不同FPGA的代码升级和自动加载，可以在任何时间、无需线缆的实现FPGA代码正确、快速、高效加载。The invention adopts Nor flash and TCP/IP network technology to realize automatic loading of multiple FPGA codes inside the base station through CPLD logic, including two processes of writing FPGA codes into Norflash through the network and realizing automatic loading of FPGA through CPLD. In this way, the code upgrade and automatic loading of different FPGAs inside the base station equipment can be realized in the operator's computer room, and the FPGA code can be loaded correctly, quickly and efficiently at any time without cables.

从设备服务器将多个FPGA代码下载到基站设备的Norflash指定存储位置；基站再次启动时，POWERPC(性能优化的增强型精简指令集中央处理器)可以通过CPLD从Nor flash指定的存储位置读取FPGA image配置文件，进入加载过程。Download multiple FPGA codes from the device server to the Norflash specified storage location of the base station equipment; when the base station starts up again, POWERPC (performance-optimized enhanced reduced instruction set central processing unit) can read the FPGA from the Norflash specified storage location through CPLD image configuration file, enter the loading process.

设备的FPGA代码需要升级时，主机会通过TCP/IP技术向指定IP地址设备传送数据，设备中的POWERPC通过报文中IP地址判断是否为送到本机数据，如果符合则接收数据，并将数据存储在Nor flash指定存储位置；当然，传送的数据也不仅限于FPGA代码，也可以是系统引导文件等。When the FPGA code of the device needs to be upgraded, the host computer will transmit data to the device with the specified IP address through TCP/IP technology. The data is stored in the designated storage location of Nor flash; of course, the transmitted data is not limited to FPGA code, but also system boot files, etc.

在设备启动过程中，POWERPC从Nor flash指定的存储位置读取FPGA image(镜像)配置文件。CPLD将FPGA的PROG_B管脚拉低，启动配置过程；当PROG_B拉低，FPGA开始清除自身内部RAM(随机存取存储器)，在这个过程中FPGA把INIT_B引脚配低，当RAM清除完成后，INIT_B引脚变高；CPLD将INIT_B引脚作为输入监测，当该引脚变为高电平后，CPLD就将所要配置的image文件送至FPGA的DIN引脚，同时将相应的时钟CCLK送至FPGA；在这个过程中CPLD监测FPGA的DONE引脚，如果DONE引脚变为高电平，则说明FPGA加载成功，如果DONE为低电平，则重复上面的步骤，直至FPGA加载成功。During device startup, POWERPC reads the FPGA image (image) configuration file from the storage location specified by Nor flash. The CPLD pulls the PROG_B pin of the FPGA low to start the configuration process; when the PROG_B is pulled low, the FPGA starts to clear its internal RAM (random access memory). During this process, the FPGA sets the INIT_B pin low. When the RAM is cleared, The INIT_B pin becomes high; the CPLD monitors the INIT_B pin as an input. When the pin becomes high, the CPLD sends the image file to be configured to the DIN pin of the FPGA, and at the same time sends the corresponding clock CCLK to the FPGA; during this process, the CPLD monitors the DONE pin of the FPGA. If the DONE pin becomes high, it means that the FPGA is loaded successfully. If the DONE is low, repeat the above steps until the FPGA is loaded successfully.

具体步骤如下：Specific steps are as follows:

步骤1.将需要重新加载的FPGA image文件存储在服务器上。Step 1. Store the FPGA image file that needs to be reloaded on the server.

步骤2.通过TCP/IP网络技术将需要升级的FPGA image文件发送到指定IP地址设备，设备中的POWERPC(性能优化的增强型精简指令集中央处理器)通过报文中IP地址判断是否为送到本机数据，如果符合则接收数据，POWERPC接收到数据后将擦除Nor flash相关存储位置，并将收到的配置文件写入Nor flash指定存储位置。Step 2. Send the FPGA image file that needs to be upgraded to the device with the specified IP address through TCP/IP network technology, and the POWERPC (performance-optimized enhanced simplified instruction set central processing unit) in the device judges whether it is sent by the IP address in the message. If it meets the local data, it will receive the data. After receiving the data, POWERPC will erase the related storage location of Nor flash, and write the received configuration file into the specified storage location of Nor flash.

步骤3.在设备启动过程中，POWERPC通过CPLD控制多片FPGA的加载进程，从Nor flash指定的存储位置读取需要加载FPGA image配置文件。Step 3. During device startup, POWERPC controls the loading process of multiple FPGAs through CPLD, and reads the FPGA image configuration file that needs to be loaded from the storage location specified by Nor flash.

步骤4.CPLD首先将FPGA的PROG_B管脚拉低，启动配置过程；当PROG_B拉低，FPGA开始清除自身内部RAM，在这个过程中FPGA把INIT_B引脚配低，当RAM清除完成后，INIT_B引脚变高；CPLD将INIT_B引脚作为输入监测，当该引脚变为高电平后，CPLD就将所要配置的image文件送至FPGA的DIN引脚，同时将相应的时钟CCLK送至FPGA；在这个过程中CPLD监测FPGA的DONE引脚，如果DONE引脚变为高电平，则说明FPGA加载成功，如果DONE为低电平，则重复上面的步骤，直至本片FPGA加载成功。Step 4. The CPLD first pulls down the PROG_B pin of the FPGA to start the configuration process; when PROG_B is pulled down, the FPGA starts to clear its own internal RAM. During this process, the FPGA sets the INIT_B pin low. The pin becomes high; CPLD monitors the INIT_B pin as an input, and when the pin becomes high, the CPLD sends the image file to be configured to the DIN pin of the FPGA, and at the same time sends the corresponding clock CCLK to the FPGA; During this process, the CPLD monitors the DONE pin of the FPGA. If the DONE pin becomes high, it means that the FPGA is loaded successfully. If the DONE is low, repeat the above steps until the FPGA is loaded successfully.

步骤5.POWERPC进程管理会检查是否还有FPGA需要加载，如果有，则重复步骤3和步骤4。Step 5. The POWERPC process management will check whether there are FPGAs to be loaded, and if so, repeat steps 3 and 4.

步骤6.无FPGA需要加载，则所有的FPGA都加载完成。Step 6. If no FPGA needs to be loaded, all FPGAs are loaded.

本方法采用Nor flash和TCP/IP网络技术，通过CPLD逻辑实现FPGA代码自动加载。The method adopts Nor flash and TCP/IP network technology, and realizes automatic loading of FPGA code through CPLD logic.

Claims (3)

1. an auto-loading system of FPGA, is characterized in that: comprise Nor flash, CPLD, POWERPC, FPGA; Nor flash is connected with CPLD bi-directional data, and CPLD is connected with POWERPC bi-directional data; CPLD is connected with FPGA bi-directional data, and POWERPC is connected with Ethernet interface bi-directional data.

2. an automatic loading method of the FPGA based on said system, is characterized in that: adopt Nor flash and TCP/IP network technology, PowerPC loads automatically by a plurality of FPGA codes of CPLD logic realization inside of base station;

Comprise two processes of automatic loading that by network, FPGA code write to Norflash and realize FPGA by CPLD; From device server, a plurality of FPGA codes are downloaded to the Norflash designated storage location of base station equipment; When base station starts again, POWERPC reads FPGA image configuration file by CPLD from the memory location of Nor flash appointment, enters loading procedure.

3. the automatic loading method of a kind of FPGA according to claim 2, is characterized in that: comprises the following steps,

Step 1, the FPGA image file that needs are reloaded are stored on server;

Step 2, the FPGA image file of needs being upgraded by TCP/IP network technology send to assigned ip address device, POWERPC in equipment determines whether to deliver to this machine data by IP address in message, if met, receive data, POWERPC wipes Nor flash associated storage after receiving data, and the configuration file of receiving is write to Nor flash designated storage location;

Step 3, in device start process, POWERPC controls the loading process of multiple FPGA by CPLD, from the memory location of Nor flash appointment, read and need to load FPGA image configuration file;

First step 4, CPLD drag down the PROG_B pin of FPGA, start layoutprocedure; When PROG_B drags down, FPGA starts to remove self internal RAM, and in this process, FPGA joins INIT_B pin low, and after RAM has removed, INIT_B pin uprises; CPLD is using INIT_B pin as Input Monitor Connector, and when this pin becomes after high level, CPLD just delivers to the image file that will configure the DIN pin of FPGA, corresponding clock CCLK is delivered to FPGA simultaneously; In this process, the DONE pin of CPLD monitoring FPGA, if DONE pin becomes high level, illustrates that FPGA loads successfully, if DONE is low level, repeating step 3 and this step 4, until this film FPGA loads successfully;

Whether step 5, POWERPC management of process inspection also have FPGA to need to load, if had, and repeating step 3 and step 4;

Step 6, without FPGA, need to load, all FPGA have loaded.