技术领域technical field
本发明大致上是关于一种鳍部场效晶体管(fin FET)装置及形成该鳍部场效晶体管的方法，尤是关于一种具有体接触的鳍部FET装置及形成具有该体接触的该鳍部FET装置的方法。The present invention generally relates to a fin field effect transistor (fin FET) device and method of forming the same, and more particularly to a fin FET device having a body contact and forming the fin FET device having the body contact. A method for fin FET devices.
背景技术Background technique
晶体管(例如，金属氧化物半导体场效晶体管(MOSFET)或就只是场效晶体管(FET))为绝大多数的半导体集成电路(IC)的核心建构方块。FET包含源极和漏极区域，电流可在其间流动通过信道，该信道受到施加在该信道上面的栅极电极的偏压所影响。有一些半导体IC(例如，高效能微处理器)可包含数以百万个FET。就这种IC而言，减少晶体管尺寸并因此增加晶体管密度，一直以来都是半导体制造工业的最高优先事项。然而，半导体效能必需予以维持，即使该晶体管尺寸减少亦然。Transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) or just field effect transistors (FETs), are the core building blocks of most semiconductor integrated circuits (ICs). A FET contains source and drain regions between which current can flow through a channel affected by a bias voltage applied to a gate electrode over the channel. Some semiconductor ICs (eg, high performance microprocessors) can contain millions of FETs. For such ICs, reducing transistor size, and thus increasing transistor density, has long been a top priority for the semiconductor manufacturing industry. However, semiconductor performance must be maintained even as the transistor size decreases.
鳍部场效晶体管(fin FET)是晶体管的一种类型，这种类型可提供其自身既能减少晶体管尺寸、又能维持晶体管效能的双重目标。该鳍部FET是一种形成在薄鳍部中的三维晶体管，该薄鳍部从半导体衬底向上延伸。晶体管效能通常是由测量其互导(transconductance)而决定，并且该互导与该晶体管信道的宽度成比例。在鳍部FET中，该晶体管信道是沿着该鳍部的垂直侧壁所形成或者是形成在该鳍部的垂直侧壁和顶水平平面上，因此，可达成宽信道和高效能，而不必实质上增加该晶体管所要求的衬底表面的面积。Fin Field Effect Transistors (fin FETs) are a type of transistor that may serve its own dual purpose of reducing transistor size while maintaining transistor performance. The FinFET is a three-dimensional transistor formed in a thin fin extending upward from a semiconductor substrate. Transistor performance is usually determined by measuring its transconductance, which is proportional to the width of the transistor channel. In FinFETs, the transistor channel is formed along the vertical sidewalls of the fin or is formed on the vertical sidewalls and top horizontal plane of the fin, thus, wide channel and high performance can be achieved without having to Substantially increases the area of the substrate surface required for the transistor.
鳍部FET由于其优良的短信道效应控制和调整尺寸能力，因此是小线宽工艺(例如，大约22奈米及更低)的最有潜力的选项。为了有利于一般目的的应用，希望鳍部FET具有可用于不同电路功能的不同临界电压(Vt)。然而，制造具有不同临界电压的鳍部FET是困难的。由于该信道或"鳍部"宽度的等级为5-20奈米，因此，这个尺寸会使其没有办法通过改变信道掺杂浓度而有效地调整Vt。此外，信道掺杂会劣 化迁移率，并且因此会影响鳍部FET效能。一种得到具有不同Vt的鳍部FET的可能方式为在高-K-金属-栅极鳍部FET工艺中，利用不同的栅极堆栈材料。然而，生产具有不同Vt的鳍部FET所需的多栅极堆栈制程在该制造制程中是复杂且昂贵的。得到不同Vt的另一个方式是通过体偏压(body bias)。举例来说，在传统的表面信道nFET中，负体偏压会增加Vt，但正体偏压则会降低Vt。Fin FETs are the most potential option for small linewidth processes (eg, around 22nm and below) due to their excellent short channel effect control and sizing capabilities. To facilitate general purpose applications, it is desirable that the FinFETs have different threshold voltages (Vt) that can be used for different circuit functions. However, it is difficult to fabricate finFETs with different threshold voltages. Since the channel or "fin" width is on the order of 5-20nm, this dimension makes it impossible to effectively tune Vt by changing the channel doping concentration. Furthermore, channel doping degrades mobility and thus finFET performance. One possible way to get finFETs with different Vt is to use different gate stack materials in the high-K-metal-gate finFET process. However, the multiple gate stack process required to produce finFETs with different Vts is complex and expensive in the fabrication process. Another way to get a different Vt is through body bias. For example, in a conventional surface-channel nFET, negative body bias increases Vt, but positive body bias decreases Vt.
已经提出数种将体接触引入鳍部FET结构的方法。然而，这些方法不是太复杂、在制造上不切实际，不然就是该鳍部FET装置特性会受到严重的影响。举例来说，已提出使用硅磊晶(silicon epitaxy)来将半导体衬底的块体硅(bulk silicon)连接至多栅极(polygate)，且鳍部在该多栅极处形成覆盖在该半导体衬底的该块体硅上面。然而，这种方法与替换性金属栅极(RMG)工艺不匹配，因此需要硅磊晶与该半导体衬底的该块体硅的该多栅极的接触区域隔离，并且该体接触也要与该鳍部实体地隔离，而没有与该鳍部直接接触。先前针对鳍部FET形成体接触的努力，已经避免因掺杂该鳍部以形成该鳍部FET的源极和漏极区域，而在该鳍部上形成该体接触的情形，这是因为该体接触不能既与该鳍部FET的源极和漏极区域直接实体接触，而又能维持操作性。Several methods have been proposed for introducing body contact into finFET structures. However, these methods are not too complicated to be manufactured impractical, or else the FinFET device characteristics will be severely affected. For example, it has been proposed to use silicon epitaxy to connect bulk silicon of a semiconductor substrate to a polygate at which fins are formed overlying the semiconductor substrate. bottom of the bulk silicon above. However, this approach is not compatible with a replacement metal gate (RMG) process, thus requiring that the epitaxial silicon be isolated from the contact area of the multi-gate of the bulk silicon of the semiconductor substrate, and that the bulk contact also be separated from The fin is physically isolated without direct contact with the fin. Previous efforts to form body contacts for fin FETs have avoided forming the body contacts on the fins by doping the fins to form the source and drain regions of the fin FETs because the The body contacts cannot make direct physical contact with the source and drain regions of the FinFET and still maintain operability.
因此，希望提供鳍部FET装置和形成这种鳍部FET装置的方法。也希望提供鳍部FET装置和形成鳍部FET装置的方法，该鳍部FET装置和其形成方法可避免和在鳍部上形成体接触所相关的复杂性，其中，该鳍部等同与该体接触电性相通的晶体管。此外，从接下来对发明的详细描述及附随的权利要求，并且一同参照所附的图式和本发明的这个背景技术，本发明的其它希望的特征和特性将变得明显。Accordingly, it is desirable to provide finFET devices and methods of forming such finFET devices. It is also desirable to provide fin FET devices and methods of forming fin FET devices that avoid the complexities associated with forming body contacts on fins that are identical to the body Contact transistors that are electrically connected. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken together with the accompanying drawings and this background of the invention.
发明内容Contents of the invention
此处提供鳍部场效晶体管装置及形成该鳍部场效晶体管装置的方法。在实施例中，鳍部场效晶体管装置包含具有鳍部的半导体衬底。栅极电极结构覆盖在该鳍部上面。源极和漏极环状及/或延伸区域及磊晶生长的源极区域和漏极区域形成在该鳍部中或该鳍部上，并且邻近该栅极电极结构而设置。体接触设置在该鳍部的接触表面上，并且该 体接触与该环状及/或延伸区域及该磊晶生长的源极区域和漏极区域分离地隔开。FinFET devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially grown source and drain regions are formed in or on the fin and are disposed adjacent to the gate electrode structure. A body contact is provided on the contact surface of the fin, and the body contact is spaced separately from the ring and/or extension region and the epitaxially grown source and drain regions.
在另一个实施例中，鳍部场效晶体管装置包含具有鳍部的半导体衬底。第一绝缘体层覆盖在该半导体衬底上面，并且具有小于该鳍部的高度的厚度。该鳍部延伸穿过并且突出超过该第一绝缘体层，以提供暴露的鳍部部分。栅极电极结构覆盖在该暴露的鳍部部分上面，并且藉由栅极绝缘层而与该鳍部电性绝缘。源极和漏极环状及/或延伸区域及磊晶生长的源极区域和漏极区域形成在该暴露的鳍部部分中或在该暴露的鳍部部分上，并且邻近该栅极电极结构而设置。体接触设置在该暴露的鳍部部分的接触表面上。该体接触与该磊晶生长的源极区域和漏极区域分离地隔开，并且复与该环状及/或延伸区域分离地隔开。该体接触包含偏压该场效晶体管的临界电压的掺质浓度。接触绝缘层设置在该暴露的鳍部部分上方，该体接触与该环状及/或延伸区域之间。接触覆盖层设置在该体接触和该接触绝缘层上方。In another embodiment, a FinFET device includes a semiconductor substrate having a fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than the height of the fin. The fin extends through and protrudes beyond the first insulator layer to provide an exposed fin portion. A gate electrode structure overlies the exposed fin portion and is electrically insulated from the fin by a gate insulating layer. source and drain halo and/or extension regions and epitaxially grown source and drain regions formed in or on the exposed fin portion and adjacent to the gate electrode structure And set. A body contact is provided on the contact surface of the exposed fin portion. The body contact is spaced separately from the epitaxially grown source and drain regions, and from the ring and/or extension region. The body contact contains a dopant concentration that biases the threshold voltage of the field effect transistor. A contact insulating layer is disposed over the exposed fin portion, between the body contact and the ring and/or extension region. A contact covering layer is disposed over the body contact and the contact insulating layer.
在另一个实施例中，形成鳍部场效晶体管装置的方法包含提供具有鳍部的半导体衬底。栅极电极结构形成覆盖在该鳍部上面。在该鳍部的一部分上方和该栅极电极结构上方图案化布植掩膜层，以暴露该鳍部邻近该栅极电极结构的源极/漏极部分，源极和漏极区域形成在该源极/漏极部分内。离子布植至该鳍部的该暴露的源极/漏极部分内，以形成邻近该栅极电极结构的源极和漏极环状及/或延伸区域。选择性移除该布植掩膜层，并且在选择性移除该布植掩膜层后，形成接触绝缘层在该鳍部上方。在该接触绝缘层上方图案化接触图案层，以暴露该接触绝缘层的接触部分。选择性蚀刻该接触绝缘层的该接触部分，从而暴露该鳍部的接触表面。该体接触形成在该鳍部的该接触表面上，并且该体接触与该环状及/或延伸区域分离地隔开。源极区域和漏极区域在该源极和漏极环状及/或延伸区域上方磊晶地生长。In another embodiment, a method of forming a FinFET device includes providing a semiconductor substrate having a fin. A gate electrode structure is formed overlying the fin. patterning an implant mask layer over a portion of the fin and over the gate electrode structure to expose a source/drain portion of the fin adjacent to the gate electrode structure where source and drain regions are formed within the source/drain section. Ions are implanted into the exposed source/drain portion of the fin to form source and drain halos and/or extension regions adjacent to the gate electrode structure. The implant mask layer is selectively removed, and after the implant mask layer is selectively removed, a contact insulating layer is formed over the fin. A contact pattern layer is patterned over the contact insulating layer to expose a contact portion of the contact insulating layer. The contact portion of the contact insulating layer is selectively etched, thereby exposing the contact surface of the fin. The body contact is formed on the contact surface of the fin, and the body contact is spaced separately from the ring and/or extension region. Source and drain regions are epitaxially grown over the source and drain halo and/or extension regions.
附图说明Description of drawings
该等不同的实施例将连同接下来的图式予以描述，其中，相同的标号代表相同的组件，其中：These different embodiments will be described in conjunction with the following figures, wherein like reference numerals refer to like components, wherein:
图1为半导体衬底包含形成于其内的鳍部及在该鳍部上面的栅极 电极结构的部分的透视图；以及1 is a perspective view of a portion of a semiconductor substrate including a fin formed therein and a gate electrode structure over the fin; and
图2-图12为图1的该半导体衬底沿着图1的线A-A的剖面侧视图，以例示依据实施例用以制作包含体接触的鳍部FET装置的范例方法，其中，该体接触设置在鳍部上，该鳍部等同与该体接触电性相通的晶体管。2-12 are cross-sectional side views of the semiconductor substrate of FIG. 1 along line A-A of FIG. 1 to illustrate an exemplary method for fabricating a FinFET device including a body contact according to an embodiment, wherein the body contact disposed on a fin equivalent to a transistor in electrical communication with the body contact.
具体实施方式detailed description
接下来的详细描述在本质上仅作为范例之用，而不打算用来限制该等不同的实施例、或其应用和用途。此外，没有意图被先前的背景技术和接下来的详细说明中所出现的任何理论约束。The following detailed description is exemplary in nature only and is not intended to limit the various embodiments, or their application and uses. Furthermore, there is no intention to be bound by any theory presented in the preceding background and the following detailed description.
此处提供鳍部场效晶体管(fin FET)装置及形成该鳍部FET装置的方法，该鳍部FET装置致能晶体管的临界电压(Vt)，该临界电压(Vt)可视需要而通过偏压体接触来加以修正。尤其是，该鳍部FET装置包含体接触，该体接触设置在鳍部上，该鳍部等同与该体接触电性相通的晶体管，但维持该晶体管的操作性。此处所描述的方法即使在奈米-等级尺寸限制下，亦可藉由防止该体接触与该晶体管的源极和漏极区域之间的直接实体接触，而致能该体接触的有效形成。因为该体接触可有效地形成在鳍部上，而该鳍部等同与该体接触电性相通的晶体管，并且，又能维持该晶体管的操作性，因此，该晶体管的该Vt可视需要而藉由偏压该体接触来加以修正。Provided herein are fin field effect transistor (fin FET) devices and methods of forming the fin FET devices that enable a threshold voltage (Vt) of a transistor that can be optionally controlled by biasing Press body contact to be corrected. In particular, the FinFET device includes a body contact disposed on the fin that is identical to a transistor in electrical communication with the body contact, but maintains operability of the transistor. The methods described herein enable efficient formation of the body contact even under nano-scale size constraints by preventing direct physical contact between the body contact and the source and drain regions of the transistor. Because the body contact can be effectively formed on a fin that is identical to a transistor in electrical communication with the body contact and maintains operability of the transistor, the Vt of the transistor can be adjusted as desired. This is corrected by biasing the body contact.
参照图1，依据用以形成鳍部FET装置的方法的范例实施例，提供具有鳍部12形成于其中或其上的半导体衬底10。虽然没有显示，但应体会到该半导体衬底10可依据传统的鳍部FET工艺，而包含复数个鳍部12。没有打算限制，尽管此处所描述的该鳍部FET装置和方法并不受限于任何特别的尺寸约束，该鳍部12可具有奈米等级的宽度，例如从大约5至大约20奈米。如此处所使用的，"半导体衬底”这个术语将用来涵盖传统上使用在半导体工业中的半导体材料。“半导体材料”包含单晶硅材料(例如，半导体工业所通常使用的相对纯或轻度掺杂掺质的单晶硅材料)连同多晶硅材料，以及与其它元素(例如，锗、碳、及类似者)混合的硅。此外，“半导体材料”涵盖其它材料，例如，相对纯和掺杂掺质的锗、砷化镓、氧化锌、玻璃、及类似者。在图1 所显示的实施例中，该半导体衬底10为块体硅晶圆，具有该鳍部12形成在该块体硅晶圆中。然而，将体会到在其它实施例中，虽然没有在图式中显示，该半导体衬底10可包含设置在绝缘材料上的含硅材料，通称为绝缘体上硅(SOI)结构，其接着被支持衬底所支持。为了例示的目的，图1中只显示该半导体衬底10的一部分14。在实施例中，该鳍部12是掺杂有选自P-型掺质或N-型掺质的掺质。举例来说，在实施例中，该半导体衬底10的该部分14和该鳍部12是掺杂有P-型掺质，例如但不限于可预期形成N-型金属氧化物半导体(NMOS)鳍部FET的硼、铝、镓、铟、BF2及其组合，。然而，虽然没有显示，但应体会到该半导体衬底的其它部分也可掺杂N-型掺质，例如但不限于可预期形成P-型金属氧化物半导体(PMOS)鳍部FET的磷、砷、锑、及其组合。关于这方面，此处所描述的方法适合用来形成NMOS鳍部FET或PMOS鳍部FET，视用来形成个别鳍部FET的特微所采用的材料而定。如果被制作的该鳍部FET装置是互补式MOS集成电路(CMOS IC)，则该半导体衬底10的至少一部分和鳍部12是掺杂有N-型掺质，而该半导体衬底的至少一部分是掺杂有P-型掺质。举例来说，在该鳍部12包含该掺质的情况下，该半导体衬底10的该部分可在该鳍部12形成在该半导体衬底10中或该半导体衬底上之前或之后，藉由离子布植来加以掺杂。可使用多离子布植步骤，以达成希望的掺质浓度和分布。该掺质分布可作为达成所制作的特定鳍部FET的希望临界电压的一个变量。Referring to FIG. 1 , in accordance with an example embodiment of a method for forming a finFET device, a semiconductor substrate 10 having a fin 12 formed therein or thereon is provided. Although not shown, it should be appreciated that the semiconductor substrate 10 may include a plurality of fins 12 according to conventional fin FET processes. Without intending to be limiting, although the FinFET devices and methods described herein are not limited to any particular dimensional constraints, the fin 12 may have a width on the nanometer scale, eg, from about 5 to about 20 nanometers. As used herein, the term "semiconductor substrate" shall be used to encompass semiconductor materials traditionally used in the semiconductor industry. "Semiconductor material" includes single crystal silicon materials (e.g., relatively pure or lightly doped single crystal silicon materials commonly used in the semiconductor industry) as well as polycrystalline silicon materials, as well as materials with other elements (such as germanium, carbon, and the like) or) mixed silicon. Furthermore, "semiconductor material" encompasses other materials such as relatively pure and doped germanium, gallium arsenide, zinc oxide, glass, and the like. In the embodiment shown in FIG. 1 , the semiconductor substrate 10 is a bulk silicon wafer with the fins 12 formed in the bulk silicon wafer. However, it will be appreciated that in other embodiments, although not shown in the drawings, the semiconductor substrate 10 may comprise a silicon-containing material disposed on an insulating material, commonly referred to as a silicon-on-insulator (SOI) structure, which is then supported supported by the substrate. For illustration purposes, only a portion 14 of the semiconductor substrate 10 is shown in FIG. 1 . In an embodiment, the fin portion 12 is doped with dopants selected from P-type dopants or N-type dopants. For example, in an embodiment, the portion 14 of the semiconductor substrate 10 and the fin portion 12 are doped with P-type dopants, such as but not limited to N-type metal oxide semiconductor (NMOS) can be expected to form Boron, aluminum, gallium, indium, BF2 and combinations thereof for fin FETs. However, although not shown, it should be appreciated that other portions of the semiconductor substrate may also be doped with N-type dopants such as, but not limited to, phosphorous, which are expected to form P-type metal-oxide-semiconductor (PMOS) fin FETs. Arsenic, antimony, and combinations thereof. In this regard, the methods described herein are suitable for forming NMOS FinFETs or PMOS FinFETs, depending on the materials used for the nanoscale used to form the individual FinFETs. If the fin FET device being fabricated is a complementary MOS integrated circuit (CMOS IC), at least a portion of the semiconductor substrate 10 and the fin 12 are doped with N-type dopants, and at least part of the semiconductor substrate A part is doped with P-type dopant. For example, where the fin 12 includes the dopant, the portion of the semiconductor substrate 10 may be formed before or after the fin 12 is formed in or on the semiconductor substrate 10 by Doping is done by ion implantation. Multiple ion implantation steps can be used to achieve the desired dopant concentration and distribution. The dopant profile can be used as a variable to achieve the desired threshold voltage for the particular finFET being fabricated.
如图1所显示的，栅极电极结构20设置在该鳍部12上方。举例来说，在实施例中，第一绝缘体层16覆盖在该半导体衬底10上面，且具有小于该鳍部12的高度的厚度，以致于该鳍部12延伸穿过并且突出超过该第一绝缘体层16，以提供暴露的鳍部部分18。该第一绝缘体层16并没有特别的限制，并且可包含氧化物，例如，硅氧化物。该栅极电极结构20覆盖在该鳍部12上面，更特定言之，在该暴露的鳍部部分18上面。该栅极电极结构20藉由栅极绝缘层22而与该鳍部12电性绝缘。该栅极电极结构20可通过传统工艺(例如，栅极先置或栅极后置、多晶硅/SiON或高-K/金属-栅极工艺)而形成在该鳍部12上方。举例来说，并且如图1所显示的，氮化物帽(nitride cap)24可设置在该栅极电极结构20上面，以促进该栅极电极结构20的形成，并 且在形成该鳍部FET装置的期间，提供保护给该栅极电极结构20。该氮化物帽24可从任意氮化物(例如，硅氮化物)加以形成。在实施例中，并且如图1所显示的，依据传统的鳍部FET工艺，该栅极电极结构20在鳍部部分18的三个侧面上绕着该暴露的鳍部部分18的周围。图2例示图1的该半导体衬底10的该部分14沿着线A-A的剖面图，其目的在于例示形成该鳍部FET装置的范例方法。As shown in FIG. 1 , a gate electrode structure 20 is disposed above the fin 12 . For example, in an embodiment, the first insulator layer 16 overlies the semiconductor substrate 10 and has a thickness less than the height of the fin 12 such that the fin 12 extends through and protrudes beyond the first Insulator layer 16 to provide exposed fin portion 18 . The first insulator layer 16 is not particularly limited, and may include oxide, for example, silicon oxide. The gate electrode structure 20 overlies the fin 12 , more particularly, the exposed fin portion 18 . The gate electrode structure 20 is electrically insulated from the fin portion 12 by a gate insulating layer 22 . The gate electrode structure 20 may be formed over the fin 12 by a conventional process (eg, gate-first or gate-last, polysilicon/SiON or high-K/metal-gate process). For example, and as shown in FIG. 1 , a nitride cap (nitride cap) 24 may be disposed over the gate electrode structure 20 to facilitate the formation of the gate electrode structure 20 and to facilitate the formation of the finFET device. During the period, protection is provided to the gate electrode structure 20 . The nitride cap 24 may be formed from any nitride such as silicon nitride. In an embodiment, and as shown in FIG. 1 , the gate electrode structure 20 wraps around the exposed fin portion 18 on three sides of the fin portion 18 in accordance with conventional finFET processing. 2 illustrates a cross-sectional view of the portion 14 of the semiconductor substrate 10 of FIG. 1 along line A-A for the purpose of illustrating an example method of forming the FinFET device.
在实施例中，并且如图3所显示的，第二绝缘体层26形成在该暴露的鳍部部分18和该氮化物帽24上方。该第二绝缘体层26可从氮化物加以形成，该氮化物例如为与用来形成该氮化物帽24的相同氮化物，或为用来形成低-k薄膜(SiCON或SiCN)的相同氮化物。该第二绝缘体层26设置在该栅极电极结构20的侧壁上的部分至终仍然存在，以作为该鳍部FET装置中的第一侧壁间隔件26，如下文中所详细描述的。更特定言之，如图4所显示的，使用适合的蚀刻剂(例如，氮蚀刻剂)来蚀刻该第二绝缘体层设置在水平表面上的部分，而该第二绝缘体层26设置在该栅极电极结构20的侧壁上的部分则仍作为第一侧壁间隔件26。In an embodiment, and as shown in FIG. 3 , a second insulator layer 26 is formed over the exposed fin portion 18 and the nitride cap 24 . The second insulator layer 26 may be formed from a nitride such as the same nitride used to form the nitride cap 24, or the same nitride used to form a low-k film (SiCON or SiCN). . The portion of the second insulator layer 26 disposed on the sidewalls of the gate electrode structure 20 remains eventually to serve as the first sidewall spacers 26 in the FinFET device, as described in detail below. More specifically, as shown in FIG. 4, the portion of the second insulator layer disposed on the horizontal surface and the portion of the second insulator layer 26 disposed on the gate is etched using a suitable etchant (eg, nitrogen etchant). The portion on the sidewall of the pole electrode structure 20 is still used as the first sidewall spacer 26 .
参照图5，在实施例中，第一掩膜层28形成在该栅极电极结构20和该暴露的鳍部部分18上方，其目的在于在离子布植30该半导体衬底未显示的部分的期间，遮蔽该半导体衬底10显示于图5中的该部分14中的该暴露的鳍部部分18。举例来说，在实施例中，并且如图5所显示的，该半导体衬底10的该部分14掺杂有可预期形成NMOS鳍部FET的P-型掺质，而可采用图5所显示的该离子布植30，以形成PMOS鳍部FET在该半导体衬底10未显示的其它部分上的延伸及/或环状区域(未显示)。然而，将体会到该第一掩膜层28可视情况形成，并且该第一掩膜层28的形成与将形成的鳍部FET的类型有关。在实施例中，该第一掩膜层28是从某种材料形成，该种材料可从该栅极电极结构20和该半导体衬底10的该部分14上方选择性移除。“选择性移除”是指一种材料在特别的蚀刻剂中较另一种材料具有较高的蚀刻率。或者，该第一掩膜层28的该材料可在从下方的结构移除最小材料的情况下予以移除。举例来说，在实施例中，该第一掩膜层28是从抗蚀材料加以形成，例如光阻(photoresist)。在完成离子布植30后，以适当的蚀 刻剂(例如，氧化物蚀刻剂)来蚀刻并选择性移除该第一掩膜层28，而该栅极电极结构20和该半导体衬底10的该部分14则通过传统的工艺来选择性清洗。Referring to FIG. 5 , in an embodiment, a first masking layer 28 is formed over the gate electrode structure 20 and the exposed fin portion 18 for the purpose of ion implanting 30 the portion of the semiconductor substrate not shown. Meanwhile, the exposed fin portion 18 of the semiconductor substrate 10 in the portion 14 shown in FIG. 5 is masked. For example, in an embodiment, and as shown in FIG. 5, the portion 14 of the semiconductor substrate 10 is doped with a P-type dopant expected to form an NMOS fin FET, and the The ion implant 30 is used to form extensions and/or ring regions (not shown) of PMOS fin FETs on other parts of the semiconductor substrate 10 not shown. However, it will be appreciated that the first masking layer 28 can be optionally formed and that the formation of the first masking layer 28 is related to the type of finFET to be formed. In an embodiment, the first mask layer 28 is formed from a material that is selectively removable from over the gate electrode structure 20 and the portion 14 of the semiconductor substrate 10 . "Selective removal" means that one material has a higher etch rate in a particular etchant than another material. Alternatively, the material of the first mask layer 28 may be removed with minimal material removal from the underlying structure. For example, in an embodiment, the first mask layer 28 is formed from a resist material, such as a photoresist. After the ion implantation 30 is completed, the first mask layer 28 is etched and selectively removed with a suitable etchant (for example, an oxide etchant), and the gate electrode structure 20 and the semiconductor substrate 10 The portion 14 is selectively cleaned by conventional techniques.
在实施例中，并且如图6所显示的，在选择性移除该第一掩膜层及选择性清洗后，在该半导体衬底10的该部分14上方(包含该暴露的鳍部部分18上方)以及该第一侧壁间隔件26和该栅极电极结构20上方图案化布植掩膜层32，以暴露该暴露的鳍部部分18邻近该栅极电极结构20的源极/漏极部分，而该鳍部FET的源极和漏极区域将形成在该源极/漏极部分内。该布植掩膜层32与该第一掩膜层可由相同的材料来加以形成，以使该布植掩膜层32得以被选择性移除。如下文中所详细描述的，该布植掩膜层32通常是设置在该暴露的鳍部部分18中将形成体接触的部分上方，并且遮蔽该部分。以这种方式，藉由隔离紧紧邻近该第一侧壁间隔件26的部分而形成的该半导体衬底10的该源极和漏极区域与，可有效地维持该体接触与该源极和漏极区域的隔离，即使在该暴露的鳍部部分18上形成该体接触时亦然。离子布植34可接着在紧紧邻近该第一侧壁间隔件26实行而布植到该暴露的鳍部部分18中，以通过传统的离子布植工艺来形成邻近该第一侧壁间隔件26的源极和漏极环状及/或延伸区域38。为了简化起见，图6只大致上例示形成在该半导体衬底10中的环状及/或延伸区域38，虽然将体会到特定的环状及/或延伸区域38的组构是动态的，并且会随特别鳍部FET装置的效能考量而变化。该布植掩膜层32隔离该环状及/或延伸区域38与该半导体衬底10的特定部分的形成，该特别部分暴露在该布植掩膜层32的图案中。在完成离子布植34后，选择性移除该布植掩膜层32，并且通过传统工艺来选择性清洗该栅极电极结构20和该半导体衬底10的该部分14。In an embodiment, and as shown in FIG. 6 , after the selective removal of the first mask layer and selective cleaning, over the portion 14 of the semiconductor substrate 10 (including the exposed fin portion 18 above) and the first sidewall spacer 26 and the gate electrode structure 20 above the patterned implant mask layer 32 to expose the source/drain of the exposed fin portion 18 adjacent to the gate electrode structure 20 part, and the source and drain regions of the finFET will be formed within the source/drain part. The implant mask layer 32 and the first mask layer can be formed of the same material so that the implant mask layer 32 can be selectively removed. As described in detail below, the implant mask layer 32 is generally disposed over and masks portions of the exposed fin portion 18 where body contacts are to be formed. In this way, by isolating the source and drain regions of the semiconductor substrate 10 formed immediately adjacent to the first sidewall spacer 26, the body contact and the source can be effectively maintained. isolation from the drain region even when the body contact is formed on the exposed fin portion 18 . Ion implantation 34 may then be performed immediately adjacent to the first sidewall spacer 26 into the exposed fin portion 18 to form adjacent to the first sidewall spacer by a conventional ion implantation process. 26 source and drain halos and/or extension regions 38 . For simplicity, FIG. 6 only generally illustrates the ring and/or extension regions 38 formed in the semiconductor substrate 10, although it will be appreciated that the configuration of a particular ring and/or extension region 38 is dynamic, and Varies with performance considerations for a particular FinFET device. The implant mask layer 32 isolates the annular and/or extension region 38 from the formation of specific portions of the semiconductor substrate 10 that are exposed in the pattern of the implant mask layer 32 . After the ion implantation 34 is completed, the implantation mask layer 32 is selectively removed, and the gate electrode structure 20 and the portion 14 of the semiconductor substrate 10 are selectively cleaned by conventional processes.
在实施例中，并且如图7所显示的，在形成该环状及/或延伸区域38并且移除该布植掩膜层32后，接触绝缘层37形成在该半导体衬底10的该部分14上方(包含在该暴露的鳍部部分18上方)以及该第一侧壁间隔件26上方、该环状及/或延伸区域38和该闸极电极结构20上方。该接触绝缘层37与该第二绝缘体层26可由相同的材料加以形成。在实施例中，并且如图8所显示的，在该接触绝缘层37上方图案化接 触图案层40，以暴露该接触绝缘层37的接触部分，该接触部分覆盖在接触表面42上面，而体接触则形成在该接触表面42上。就这点而言，为了维持该体接触与该环状及/或延伸区域38的间隔，该接触图案层40完全地覆盖该暴露的鳍部部分18的先前暴露的部分(该环状及/或延伸区域38是形成在该部分内)，并且另覆盖该暴露的鳍部部分18与该环状及/或延伸区域38紧紧邻近的部分，如图8所显示的。该接触图案层40与该第一掩膜层和该布植掩膜层可由相同的材料来加以形成，以使该接触图案层40得以被选择性移除。一旦图案化之后，该接触图案层40中的该图案可使该接触绝缘层37的该接触部分(其由该接触图案层40所暴露)得以被选择性移除，从而暴露该暴露的鳍部部分18的该接触表面42，该体接触将形成在该接触表面42上。可以适合的氮化物蚀刻剂(例如但非限定为CF4)，通过反应式离子蚀刻(RIE)，来蚀刻该接触绝缘层37的该接触部分。在选择性蚀刻该接触绝缘层37的该接触部分后，选择性移除该接触图案层40，并且通过传统工艺来选择性清洗该接触绝缘层37。In an embodiment, and as shown in FIG. 7, after forming the ring and/or extension region 38 and removing the implant mask layer 32, a contact insulating layer 37 is formed on the portion of the semiconductor substrate 10. 14 (including over the exposed fin portion 18 ) and over the first sidewall spacer 26 , the ring and/or extension region 38 and the gate electrode structure 20 . The contact insulating layer 37 and the second insulator layer 26 can be formed of the same material. In an embodiment, and as shown in FIG. 8, the contact pattern layer 40 is patterned over the contact insulating layer 37 to expose the contact portion of the contact insulating layer 37, which covers the contact surface 42, while the bulk Contacts are then formed on this contact surface 42 . In this regard, in order to maintain the spacing of the body contacts from the ring and/or extension region 38, the contact pattern layer 40 completely covers the previously exposed portion of the exposed fin portion 18 (the ring and/or extension region 38). or extension region 38 is formed in this portion), and additionally covers the portion of the exposed fin portion 18 immediately adjacent to the annular and/or extension region 38, as shown in FIG. 8 . The contact pattern layer 40 can be formed of the same material as the first mask layer and the implant mask layer, so that the contact pattern layer 40 can be selectively removed. Once patterned, the pattern in the contact pattern layer 40 allows the contact portion of the contact insulating layer 37 (which is exposed by the contact pattern layer 40 ) to be selectively removed, thereby exposing the exposed fin. The contact surface 42 of the portion 18 on which the body contact will be formed. The contact portion of the contact insulating layer 37 can be etched by reactive ion etching (RIE) with a suitable nitride etchant (such as but not limited to CF4). After selectively etching the contact portion of the contact insulating layer 37, the contact pattern layer 40 is selectively removed, and the contact insulating layer 37 is selectively cleaned by a conventional process.
在实施例中，并且如图9所显示的，该体接触44是形成在该暴露的鳍部部分18的该接触表面42上。尤其是，该体接触44是通过在该暴露的鳍部部分18的该接触表面42上磊晶生长半导体材料而形成的，并且该体接触44只形成在该暴露的鳍部部分18的该接触表面42上，而没有形成在该接触绝缘层37上。虽然没有显示，但将体会到该暴露的鳍部部分18的该接触表面42可在形成该体接触44之前先行蚀刻，从而将该体接触44凹陷在该暴露的鳍部部分18中。此外，由于存在有设置在该环状及/或延伸区域38上方及该暴露的鳍部部分18紧紧邻近该环状及/或延伸区域38的部分上方的该接触绝缘层37，因此，该体接触44与该环状及/或延伸区域38以适合的方式分离地隔开。“分离地隔开”意指该体接触44没有接触该环状及/或延伸区域38，尽管就装置操作而言，该体接触大致上靠近该环状及/或延伸区域38，以达成低串联电阻。该接触绝缘层37最终仍设置在该体接触44与该环状及/或延伸区域38之间的该暴露的鳍部部分18上方，以将该体接触与该环状及/或延伸区域38电性绝缘。用于形成该体接触44的适合半导体材料包含以上针对该半导体衬底10所揭露的那些半导体材料。在实 施例中，该体接触44与该半导体衬底10的该部分14及该鳍部12(广义言之)掺杂有相同类型的掺质，不是N-型、就是P-型。举例来说，如果该半导体衬底10的该部分14掺杂有P-型掺质，则该体接触也掺杂有P-型掺质，该半导体衬底10的该部分14所掺杂的P-型掺质与该体接触所掺杂的P-型掺质可为相同或不同的掺质类型，例如硼。就另一个例子而言，如果该半导体衬底10的该部分14掺杂有N-型掺质，则该体接触也掺杂有N-型掺质，该半导体衬底10的该部分14所掺杂的N-型掺质与该体接触所掺杂的N-型掺质可为相同或不同的N-型掺质，例如碳。举例来说，在实施例中，该体接触44可从N-型或P-型半导体形成，视该半导体衬底10的该部分14是从N-型或P-型材料形成而定。作为一个特定的例子，就P-型体接触44而言，可使用硅锗化物。如以上所略为提及的，该鳍部FET的该Vt可藉由体偏压来加以调整，而体偏压可通过建立从该体接触44至装置信道的高导电性来加以完成。该体接触44的低接触电阻可通过适当的掺杂来加以完成。就这点而言，可形成具有掺质浓度的该体接触，该掺质浓度在适合的低等级，建立该接触电阻。较高的掺质浓度通常会减少该体接触44的串联电阻。In an embodiment, and as shown in FIG. 9 , the body contact 44 is formed on the contact surface 42 of the exposed fin portion 18 . In particular, the body contact 44 is formed by epitaxially growing semiconductor material on the contact surface 42 of the exposed fin portion 18, and the body contact 44 is only formed at the contact of the exposed fin portion 18. Surface 42, but not formed on the contact insulating layer 37. Although not shown, it will be appreciated that the contact surface 42 of the exposed fin portion 18 may be etched prior to forming the body contact 44 , thereby recessing the body contact 44 in the exposed fin portion 18 . Furthermore, due to the presence of the contact insulating layer 37 disposed over the ring and/or extension region 38 and over the portion of the exposed fin portion 18 immediately adjacent to the ring and/or extension region 38, the The body contact 44 is suitably separated from the annular and/or extension region 38 . "Separately spaced" means that the body contact 44 does not contact the annular and/or extension region 38, although in terms of device operation, the body contact is substantially adjacent to the annular and/or extension region 38 to achieve low Series resistance. The contact insulating layer 37 is ultimately still disposed over the exposed fin portion 18 between the body contact 44 and the ring and/or extension region 38 to contact the body contact with the ring and/or extension region 38 Electrically insulated. Suitable semiconductor materials for forming the body contact 44 include those disclosed above for the semiconductor substrate 10 . In an embodiment, the body contact 44 is doped with the same type of dopant as the portion 14 of the semiconductor substrate 10 and the fin 12 (broadly speaking), either N-type or P-type. For example, if the portion 14 of the semiconductor substrate 10 is doped with P-type dopants, the body contact is also doped with P-type dopants, and the portion 14 of the semiconductor substrate 10 doped The P-type dopant doped with the body contact can be the same or different dopant type, such as boron. As another example, if the portion 14 of the semiconductor substrate 10 is doped with N-type dopants, the body contact is also doped with N-type dopants, and the portion 14 of the semiconductor substrate 10 is The doped N-type dopant and the doped N-type dopant of the body contact may be the same or different N-type dopant, such as carbon. For example, in an embodiment, the body contact 44 may be formed from N-type or P-type semiconductor, depending on whether the portion 14 of the semiconductor substrate 10 is formed from N-type or P-type material. As a specific example, for the P-type body contact 44, silicon germanide may be used. As mentioned briefly above, the Vt of the FinFET can be adjusted by body biasing, which can be accomplished by establishing high conductivity from the body contact 44 to the device channel. A low contact resistance of the body contact 44 can be achieved by appropriate doping. In this regard, the body contact can be formed with a dopant concentration at a suitably low level that establishes the contact resistance. Higher dopant concentrations generally reduce the series resistance of the body contact 44 .
在实施例中，并且参照图10-12，在形成该体接触44后，暴露该环状及/或延伸区域38，以在该环状及/或延伸区域38上方致能磊晶生长的源极区域和漏极区域的形成。然而，在其它实施例中，虽然没有显示，将体会到磊晶生长的源极区域和漏极区域可在形成该体接触44之前，形成在该环状及/或延伸区域38上方。更进一步言之，将体会到特定的体接触可较特定的磊晶生长的源极区域和漏极区域更早形成。举例来说，在实施例中，PFET的磊晶生长的源极区域和漏极区域可在NFET的磊晶生长的源极区域和漏极区域形成前便已形成。因此，NFET的体接触可在NFET的磊晶生长的源极区域和漏极区域形成前就已形成。此外，在这个实施例中，PFET的体接触可在PFET的磊晶生长的源极区域和漏极区域形成后才形成。In an embodiment, and with reference to FIGS. 10-12 , after forming the body contact 44 , the ring and/or extension region 38 is exposed to enable a source of epitaxial growth over the ring and/or extension region 38 . formation of electrode and drain regions. However, in other embodiments, although not shown, it will be appreciated that epitaxially grown source and drain regions may be formed over the ring and/or extension region 38 prior to forming the body contact 44 . Still further, it will be appreciated that specific body contacts may be formed earlier than specific epitaxially grown source and drain regions. For example, in an embodiment, the epitaxially grown source and drain regions of the PFET may be formed before the epitaxially grown source and drain regions of the NFET are formed. Thus, the body contacts of the NFET can be formed before the epitaxially grown source and drain regions of the NFET are formed. Furthermore, in this embodiment, the body contact of the PFET may be formed after the epitaxially grown source and drain regions of the PFET are formed.
在实施例中，并且如图10所显示的，接触覆盖层48形成在该体接触44和该接触绝缘层37上方。该接触覆盖层48主要是在磊晶生长该源极区域和漏极区域期间形成，以屏蔽该体接触44。该接触覆盖层 48与该第二绝缘体层26和该接触绝缘层37可以相同材料形成，以使接触覆盖层48和该接触绝缘层37得以用相同蚀刻剂移除。在实施例中，并且如图11所显示的，在该接触覆盖层48上方图案化帽图案层50，以暴露该接触覆盖层48覆盖在该环状及/或延伸区域38上面的部分，而部分的该接触覆盖层48仍然在该体接触44和该接触绝缘层37上方。该帽图案层50可与该第一掩膜层、第二布植层及/或接触图案层以相同材料形成，以使该帽图案层50得以从该接触覆盖层48选择地移除。该帽图案层50中的图案使该接触覆盖层48中由该帽图案层50所暴露的部分得以选择性移除。由于该接触覆盖层48与该接触绝缘层37可由相同材料形成，因此，在该接触覆盖层48下面的该接触绝缘层37也可选择性移除，从而暴露该环状及/或延伸区域38中将要形成该磊晶生长的源极区域和漏极区域的表面。该接触绝缘层37和该接触覆盖层48覆盖在该栅极电极结构20上面的部分也在选择性蚀刻期间移除，而该接触绝缘层37和该接触覆盖层48设置在垂直表面上(例如，在该第一侧壁间隔件26上)的部分则仍留下。在选择性蚀刻该接触覆盖层48由该帽图案层50所暴露的该部分后，并且在进一步蚀刻该接触绝缘层37的下面部分后，该帽图案层50是选择性从该下面的接触覆盖层48移除，并且暴露的接触覆盖层48是通过传统工艺而选择性清洗。In an embodiment, and as shown in FIG. 10 , a contact covering layer 48 is formed over the body contact 44 and the contact insulating layer 37 . The contact capping layer 48 is mainly formed during the epitaxial growth of the source region and the drain region to shield the body contact 44 . The contact covering layer 48 can be formed of the same material as the second insulator layer 26 and the contact insulating layer 37, so that the contact covering layer 48 and the contact insulating layer 37 can be removed with the same etchant. In an embodiment, and as shown in FIG. 11 , a cap pattern layer 50 is patterned over the contact cover layer 48 to expose the portion of the contact cover layer 48 overlying the annular and/or extension region 38 , while Part of the contact covering layer 48 remains above the body contact 44 and the contact insulating layer 37 . The cap pattern layer 50 can be formed of the same material as the first mask layer, the second implant layer and/or the contact pattern layer, so that the cap pattern layer 50 can be selectively removed from the contact covering layer 48 . The pattern in the cap pattern layer 50 enables selective removal of the portion of the contact cover layer 48 exposed by the cap pattern layer 50 . Since the contact covering layer 48 and the contact insulating layer 37 can be formed of the same material, the contact insulating layer 37 under the contact covering layer 48 can also be selectively removed, thereby exposing the annular and/or extension region 38 The surfaces of the source and drain regions where the epitaxial growth will be formed. The portion of the contact insulating layer 37 and the contact covering layer 48 covering the gate electrode structure 20 is also removed during selective etching, while the contact insulating layer 37 and the contact covering layer 48 are disposed on vertical surfaces (eg , on the first sidewall spacer 26) remains. After selectively etching the portion of the contact covering layer 48 exposed by the cap pattern layer 50, and after further etching the lower portion of the contact insulating layer 37, the cap pattern layer 50 is selectively covered from the lower contact. Layer 48 is removed, and the exposed contact capping layer 48 is selectively cleaned by conventional processes.
在实施例中，并且如图12所显示的，磊晶生长的源极区域54和漏极区域56是形成在该环状及/或延伸区域38上方。尤其是，该磊晶生长的源极区域54和漏极区域56可藉由在该鳍部12上(更特定言之，在该环状及/或延伸区域38的该表面52上)磊晶生长半导体材料，而与该体接触44以实质相同的方式所形成。在实施例中，该磊晶生长的源极区域54和漏极区域56只形成在该环状及/或延伸区域38的该表面52上，而没有形成在仍在该体接触44上方的该接触覆盖层48上。以这种方式，该体接触44也与该磊晶生长的源极区域54和漏极区域56分离地隔开。虽然没有显示，但将体会到该环状及/或延伸区域38的该表面52可在形成该磊晶生长的源极区域54和漏极区域56前就被蚀刻，从而将该磊晶生长的源极区域54和漏极区域56凹陷在该环状及/或延伸区域38和该暴露的鳍部部分18中。此外，该接触覆盖层48可至终仍然设置在该体接触44和该接触绝缘层37上方，并且该接触覆盖层48在该体接触44与该磊晶生长的源极区域54和漏极区域56之间仍然维持适当的间隔。用于形成该磊晶生长的源极区域54和漏极区域56的适合材料包含以上针对该半导体衬底10和针对该体接触44所揭露的那些材料。此外，该磊晶生长的源极区域54和漏极区域56与该体接触44和该半导体衬底10的该部分14是相反类型，不是N-型、就是P-型。举例来说，如果该半导体衬底10的该部分14掺杂P-型掺质或由P-型半导体材料形成，则该磊晶生长的源极区域54和漏极区域56掺杂N-型掺质或由N-型半导体材料形成。In an embodiment, and as shown in FIG. 12 , epitaxially grown source regions 54 and drain regions 56 are formed over the ring and/or extension regions 38 . In particular, the epitaxially grown source region 54 and drain region 56 may be obtained by epitaxially growing on the fin 12 (more particularly, on the surface 52 of the ring and/or extension region 38). The semiconductor material is grown and formed in substantially the same manner as the body contact 44 . In an embodiment, the epitaxially grown source region 54 and drain region 56 are formed only on the surface 52 of the ring and/or extension region 38 and not on the still overlying body contact 44. Contact cover layer 48. In this way, the body contact 44 is also separated from the epitaxially grown source region 54 and drain region 56 . Although not shown, it will be appreciated that the surface 52 of the ring and/or extension region 38 may be etched prior to the formation of the epitaxially grown source region 54 and drain region 56 such that the epitaxially grown Source region 54 and drain region 56 are recessed in the ring and/or extension region 38 and the exposed fin portion 18 . In addition, the contact covering layer 48 may still be disposed over the body contact 44 and the contact insulating layer 37 eventually, and the contact covering layer 48 is between the body contact 44 and the epitaxially grown source region 54 and drain region 56 still maintain an appropriate interval. Suitable materials for forming the epitaxially grown source region 54 and drain region 56 include those disclosed above for the semiconductor substrate 10 and for the body contact 44 . Furthermore, the epitaxially grown source region 54 and drain region 56 are of the opposite type to the body contact 44 and the portion 14 of the semiconductor substrate 10 , either N-type or P-type. For example, if the portion 14 of the semiconductor substrate 10 is doped with P-type dopants or formed of a P-type semiconductor material, the epitaxially grown source region 54 and drain region 56 are doped with N-type The dopant may be formed from N-type semiconductor material.
虽然至少一个范例实施例已经呈现在本发明先前的详细描述中，但应体会到存在为数甚多的变体。也应体会到范例实施例只是例子而已，而并不打算以任何方式来限制本发明的范围、应用性或组构。反而是，该先前的详细描述将提供本领域的熟习技术者方便的引导方针，以实作本发明的范例实施例。了解到可对范例实施例中所描述的组件的功能和配置作出各种改变，而不致于偏离本发明在附随权利要求中所设定的范围。While at least one example embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the example embodiments are examples only, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient guideline for implementing an exemplary embodiment of the invention. It being understood that various changes may be made in the function and arrangement of components described in an example embodiment without departing from the scope of the invention as set forth in the appended claims.
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| US201361799049P | 2013-03-15 | 2013-03-15 | |
| US61/799,049 | 2013-03-15 | ||
| US14/176,767US9142674B2 (en) | 2013-03-15 | 2014-02-10 | FINFET devices having a body contact and methods of forming the same |
| US14/176,767 | 2014-02-10 |
| Publication Number | Publication Date |
|---|---|
| CN104051538A CN104051538A (en) | 2014-09-17 |
| CN104051538Btrue CN104051538B (en) | 2017-08-29 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410095458.XAExpired - Fee RelatedCN104051538B (en) | 2013-03-15 | 2014-03-14 | The fin FET devices contacted with body and the method for forming the fin FET devices contacted with the body |
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| CN (1) | CN104051538B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227202A (en)* | 2012-01-31 | 2013-07-31 | 台湾积体电路制造股份有限公司 | FinFET body contact and method of making same |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227202A (en)* | 2012-01-31 | 2013-07-31 | 台湾积体电路制造股份有限公司 | FinFET body contact and method of making same |
| Publication number | Publication date |
|---|---|
| CN104051538A (en) | 2014-09-17 |
| Publication | Publication Date | Title |
|---|---|---|
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