技术领域technical field
本发明涉及一种显示面板(DISPLAY PANEL)，特别涉及一种显示面板的栅极驱动器。The present invention relates to a display panel (DISPLAY PANEL), in particular to a gate driver of the display panel.
背景技术Background technique
近来，各种液晶显示器的产品已经相当地普及，为了有效地提升液晶显示器的可视面积，适用于窄边框的显示面板技术不断地被提出。Recently, various liquid crystal display products have been quite popular. In order to effectively increase the viewing area of the liquid crystal display, display panel technologies suitable for narrow bezels have been continuously proposed.
然而，随着显示器的分辨率不断提升，栅极驱动器可驱动显示面板进行充电的时间越来越短。为了维持一定的像素充电率，栅极驱动器中多个晶体管的尺寸必定需要增加。如此，会使栅极驱动器动态功耗与电路布局面积增加，反而更难以适用于窄边框的应用。However, as the resolution of the display continues to increase, the time that the gate driver can drive the display panel to charge becomes shorter and shorter. In order to maintain a certain pixel charging rate, the size of the multiple transistors in the gate driver must increase. In this way, the dynamic power consumption of the gate driver and the layout area of the circuit will be increased, and it is more difficult to apply to the narrow frame application.
因此，如何能有效降低栅极驱动器的电路面积，并同时维持良好的像素充电率，实属当前重要研发课题之一，也成为当前相关领域亟需改进的目标。Therefore, how to effectively reduce the circuit area of the gate driver and at the same time maintain a good pixel charging rate is one of the current important research and development topics, and has also become an urgent need for improvement in related fields.
发明内容Contents of the invention
为了解决上述的问题，本发明提供了一种显示面板。显示面板包含多条栅极线与栅极驱动器。栅极驱动器包含多个串接的驱动级，其中每个驱动级用来输出栅极驱动信号到与其相应的栅极线，驱动级中的第N级驱动级包含输入单元、驱动单元与下拉单元。输入单元用来将第N-1级驱动级输出的栅极驱动信号传送到第一控制节点，其中N为正整数，且第N-1级驱动级输出的栅极驱动信号包含连续的第一脉冲与第二脉冲。驱动单元用来根据第一控制节点的电平电压而输出栅极驱动信号。下拉单元用来在第二脉冲的致能期间后将栅极驱动信号下拉至第一电压。其中在第一脉冲的致能期间内，输入单元将第一控制节点的电平电压上拉到第二电压，在第二脉冲的致能期间后，驱动单元将该第一控制节点的电平电压上拉到第三电压，且第三电压大于第二电压。In order to solve the above problems, the present invention provides a display panel. The display panel includes a plurality of gate lines and a gate driver. The gate driver includes a plurality of driver stages connected in series, each driver stage is used to output a gate drive signal to its corresponding gate line, and the Nth driver stage in the driver stage includes an input unit, a drive unit and a pull-down unit . The input unit is used to transmit the gate drive signal output by the N-1th driver stage to the first control node, where N is a positive integer, and the gate drive signal output by the N-1th driver stage contains consecutive first pulse and second pulse. The driving unit is used for outputting the gate driving signal according to the level voltage of the first control node. The pull-down unit is used for pulling down the gate driving signal to the first voltage after the enabling period of the second pulse. During the enabling period of the first pulse, the input unit pulls up the level voltage of the first control node to the second voltage, and after the enabling period of the second pulse, the driving unit pulls the level voltage of the first control node The voltage is pulled up to a third voltage, and the third voltage is greater than the second voltage.
本发明提供了另一种栅极驱动器。栅极驱动器包含多个串接的驱动级，且多个驱动级中任意一个驱动级包含输入单元、驱动单元以及下拉单元。输入单元包含第一输入端，第二输入端与输出端。输入单元的第一输入端用来接收前级栅极驱动信号，输入单元的第二输入端用来接收第一频率信号，且输入单元的输出端电性耦接控制节点。驱动单元包含第一输入端，第二输入端与输出端。驱动单元的第一输入端电性耦接控制节点，驱动单元的第二输入端用来接收第二频率信号，且驱动单元的输出端用来输出本级栅极驱动信号，其中第一频率信号与第二频率信号为反相。下拉单元包含第一开关、第二开关、第三开关、第四开关、第五开关与第六开关。第一开关具有第一端、第二端以及控制端，其中第一开关的控制端用来接收第一频率信号，第一开关的第一端电性耦接第一开关的控制端。第二开关具有第一端、第二端以及控制端，其中第二开关的控制端电性连接第一开关的控制端，且第二开关的第一端电性连接第一开关的第一端。第三开关具有第一端、第二端以及控制端，其中第三开关的控制端用来接收前级栅极驱动信号，第三开关的第一端电性耦接第一开关的第二端，且第三开关的第二端用来接收第一电压。第四开关具有第一端、第二端以及控制端，其中第四开关的控制端用来接收前级栅极驱动信号，第四开关的第一端电性耦接第二开关的第二端，且第四开关的第二端用来接收第一电压。第五开关具有第一端、第二端以及控制端，其中第五开关的控制端电性耦接第二开关的第二端，第五开关的第一端电性耦接控制节点，且第五开关的第二端电性耦接驱动单元的输出端。第六开关具有第一端、第二端以及控制端，其中第六开关的控制端电性耦接第二开关的第二端，第六开关的第一端电性耦接驱动单元的输出端，且第六开关的第二端用来接收第一电压。The present invention provides another gate driver. The gate driver includes a plurality of driving stages connected in series, and any one of the driving stages includes an input unit, a driving unit and a pull-down unit. The input unit includes a first input terminal, a second input terminal and an output terminal. The first input end of the input unit is used to receive the front-stage gate driving signal, the second input end of the input unit is used to receive the first frequency signal, and the output end of the input unit is electrically coupled to the control node. The driving unit includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the driving unit is electrically coupled to the control node, the second input terminal of the driving unit is used to receive the second frequency signal, and the output terminal of the driving unit is used to output the gate driving signal of the current stage, wherein the first frequency signal It is anti-phase with the second frequency signal. The pull-down unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch. The first switch has a first terminal, a second terminal and a control terminal, wherein the control terminal of the first switch is used to receive the first frequency signal, and the first terminal of the first switch is electrically coupled to the control terminal of the first switch. The second switch has a first terminal, a second terminal and a control terminal, wherein the control terminal of the second switch is electrically connected to the control terminal of the first switch, and the first terminal of the second switch is electrically connected to the first terminal of the first switch . The third switch has a first terminal, a second terminal and a control terminal, wherein the control terminal of the third switch is used to receive the previous gate driving signal, and the first terminal of the third switch is electrically coupled to the second terminal of the first switch , and the second end of the third switch is used to receive the first voltage. The fourth switch has a first terminal, a second terminal and a control terminal, wherein the control terminal of the fourth switch is used to receive the previous gate driving signal, and the first terminal of the fourth switch is electrically coupled to the second terminal of the second switch , and the second end of the fourth switch is used to receive the first voltage. The fifth switch has a first terminal, a second terminal and a control terminal, wherein the control terminal of the fifth switch is electrically coupled to the second terminal of the second switch, the first terminal of the fifth switch is electrically coupled to the control node, and the fifth switch The second terminal of the five switches is electrically coupled to the output terminal of the driving unit. The sixth switch has a first terminal, a second terminal and a control terminal, wherein the control terminal of the sixth switch is electrically coupled to the second terminal of the second switch, and the first terminal of the sixth switch is electrically coupled to the output terminal of the drive unit , and the second terminal of the sixth switch is used to receive the first voltage.
综上所述，本发明的技术方案与现有技术相比具有明显的优点和有益效果。根据上述技术方案的描述，本发明具有很大的技术进步，并具有产业上的广泛利用价值，本发明提供的显示面板与栅极驱动器可具有多种驱动方式，并可提供像素数组较高的充电率，进而可使显示面板的开口率提升，或是可使栅极驱动器的面积降低，以符合窄边框应用的需求。In summary, compared with the prior art, the technical solution of the present invention has obvious advantages and beneficial effects. According to the description of the above technical solution, the present invention has made great technological progress and has wide industrial application value. The display panel and gate driver provided by the present invention can have multiple driving methods, and can provide a higher pixel array. The charging rate can increase the aperture ratio of the display panel, or reduce the area of the gate driver to meet the requirements of narrow bezel applications.
附图说明Description of drawings
图1为本发明实施例一种显示面板的示意图；FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;
图2A为本发明实施例一种栅极驱动器的示意图；2A is a schematic diagram of a gate driver according to an embodiment of the present invention;
图2B为本发明实施例图2A所示的驱动级示意图；FIG. 2B is a schematic diagram of the driving stage shown in FIG. 2A according to an embodiment of the present invention;
图3为本发明实施例第N级驱动级的示意图；FIG. 3 is a schematic diagram of an Nth driver stage according to an embodiment of the present invention;
图4为本发明实施例图3的驱动级的操作信号时序示意图；FIG. 4 is a schematic diagram of a timing sequence of operation signals of the driving stage shown in FIG. 3 according to an embodiment of the present invention;
图5A为本发明实施例在时段T1内图3的驱动级中各开关的状态示意图；图5B为本发明实施例在时段T2内图3的驱动级中各开关的状态示意图；图5C为本发明实施例在时段T5内图3的驱动级中各开关的状态示意图；图6为本发明另一实施例图3中的驱动级的操作的信号时序示意图；5A is a schematic diagram of the state of each switch in the driving stage of FIG. 3 in the time period T1 of the embodiment of the present invention; FIG. 5B is a schematic diagram of the state of each switch in the driving stage of FIG. 3 in the time period T2 of the embodiment of the present invention; FIG. 5C is the present invention The embodiment of the invention is a schematic diagram of the state of each switch in the driving stage of FIG. 3 in the period T5; FIG. 6 is a schematic diagram of the signal timing sequence of the operation of the driving stage in FIG. 3 according to another embodiment of the present invention;
其中，附图标记：Among them, reference signs:
100 显示面板100 display panels
120 显示区120 display area
122 像素数组122 pixel array
124 像素124 pixels
140 源极驱动器140 source driver
160、200 栅极驱动器160, 200 gate drivers
GL1、GL2、GL3～GLN 栅极线GL1, GL2, GL3～GLN gate lines
DL1、DL2、DL3、DL4～DLN 数据线DL1, DL2, DL3, DL4~DLN data lines
200a、300 驱动级200a, 300 driver stages
XHC、HC 频率信号XHC, HC frequency signal
G[1]、G[2]～G[n-1]、G[n] 栅极驱动信号G[1], G[2]～G[n-1], G[n] gate drive signal
Din 初始脉冲Din initial pulse
220 输入单元220 input unit
240 驱动单元240 drive unit
260 下拉单元260 pull down unit
262 下拉控制电路262 pull-down control circuit
264 下拉电路264 pull-down circuit
A、B 控制节点A, B control nodes
VSS、V1、V2、V3、V4、ΔV 电压VSS, V1, V2, V3, V4, ΔV voltage
C 电容C capacitance
T1、T2、T3、T4、T5 时段T1, T2, T3, T4, T5 time slots
T11、T12、T21、T31、T32、T41、T42、T43、T44 开关T11, T12, T21, T31, T32, T41, T42, T43, T44 switches
具体实施方式detailed description
下面给出本发明的具体实施方式，结合图示对本发明做出了详细描述。但所提供的实施例并非用来限制本发明所涵盖的范围，而结构操作的描述不是用来限制其执行的顺序，任何由组件重新组合的结构，所产生具有均等功效的装置，都是本发明所涵盖的范围。此外，附图仅以说明为目的，并没有依照原尺寸作图。为了便于理解，下述说明中相同组件将以相同的符号标示来说明。Specific embodiments of the present invention are given below, and the present invention is described in detail in conjunction with the drawings. However, the provided embodiments are not used to limit the scope of the present invention, and the description of the structure and operation is not used to limit the order of its execution. Any structure recombined by components to produce a device with equivalent functions is the present invention. scope covered by the invention. In addition, the drawings are for illustration purposes only and are not drawn to original scale. For ease of understanding, the same components will be described with the same symbols in the following description.
关于本文中所使用的“第一”、“第二”、…等，并非特别指称次序或顺序的意思，也不是用来限定本发明，其仅仅是为了区别用相同技术用语描述的组件或操作而已。The terms "first", "second", ... etc. used herein do not specifically refer to a sequence or order, nor are they used to limit the present invention, but are only used to distinguish components or operations described with the same technical terms That's all.
关于本文中所使用的“约”、“大约”或“大致”一般通常系指数值的误差或范围约百分之二十以内，较好地是约百分之十以内，而更佳地则是约百分之五以内。文中若无明确说明，其所提及的数值都视作为近似值，即如“约”、“大约”或“大致”所表示的误差或范围。As used herein, "about", "approximately" or "approximately" generally means that the error or range of the value is within about 20%, preferably within about 10%, and more preferably It is within about five percent. If there is no explicit statement in the text, the numerical values mentioned are regarded as approximate values, that is, the error or range indicated by "about", "approximately" or "approximately".
另外，关于本文中所使用的“耦接”或“连接”，均可指二个或多个组件相互直接作实体或电性接触，或是相互间接作实体或电性接触，也可指二个或多个组件相互操作或动作。In addition, the "coupling" or "connection" used in this article can refer to two or more components that are in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two components. One or more components operate or act on each other.
图1是本发明提供的实施例中的一种显示面板100的示意图。如图1所示，显示面板100包括影像显示区120、源极驱动器140以与门极驱动器160。影像显示区120包括由多条数据线(如：N条数据线DL1～DLN)与多条栅极线(如：M条栅极线GL1～GLM)配置而形成的像素数组122以及多个像素124，且像素124配置于上述像素数组122中。FIG. 1 is a schematic diagram of a display panel 100 in an embodiment of the present invention. As shown in FIG. 1 , the display panel 100 includes an image display area 120 , a source driver 140 and a gate driver 160 . The image display area 120 includes a pixel array 122 formed by a plurality of data lines (such as N data lines DL1-DLN) and a plurality of gate lines (such as M gate lines GL1-GLM) and a plurality of pixels. 124 , and the pixels 124 are arranged in the above-mentioned pixel array 122 .
源极驱动器140耦接数据线DL1～DLN，通过数据线DL1～DLN输出数据信号到影像显示区120所对应的像素124，而栅极驱动器160耦接栅极线GL1～GLM，并用来依次输出栅极驱动信号到栅极线GL1～GLM，通过栅极线GL1～GLM传送到影像显示区120所对应的像素124。The source driver 140 is coupled to the data lines DL1-DLN, and outputs data signals to the pixels 124 corresponding to the image display area 120 through the data lines DL1-DLN, and the gate driver 160 is coupled to the gate lines GL1-GLM, and is used to sequentially output The gate driving signals are sent to the gate lines GL1 -GLM, and are transmitted to the corresponding pixels 124 of the image display area 120 through the gate lines GL1 -GLM.
图2A是本发明提供的实施例一种栅极驱动器200的示意图。如图2A所示，栅极驱动器200包含多级驱动级200a。每一驱动级200a彼此互相串接，且每一级驱动级200a用来输出栅极驱动信号G[n]到对应的栅极线GL1～GLM中。FIG. 2A is a schematic diagram of a gate driver 200 according to an embodiment of the present invention. As shown in FIG. 2A , the gate driver 200 includes a multi-level driving stage 200a. Each driving stage 200a is connected in series with each other, and each driving stage 200a is used to output the gate driving signal G[n] to the corresponding gate lines GL1 -GLM.
2B图是本发明提供的实施例图2A的驱动级200a的示意图。以第N级驱动级200a为例，第N级驱动级200a包含输入单元220、驱动单元240与下拉单元260，其中N为一正整数。FIG. 2B is a schematic diagram of the driving stage 200a of FIG. 2A according to the embodiment of the present invention. Taking the N-th driving stage 200a as an example, the N-th driving stage 200a includes an input unit 220 , a driving unit 240 and a pull-down unit 260 , wherein N is a positive integer.
输入单元220的第一输入端用来接收第N-1级栅极驱动信号G[n-1]或初始脉冲Din(当N＝1时)，输入单元220的第二输入端用来接收频率信号XHC，且输入单元220的输出端电性耦接控制节点A。The first input end of the input unit 220 is used to receive the N-1th level gate drive signal G[n-1] or the initial pulse Din (when N=1), and the second input end of the input unit 220 is used to receive the frequency signal XHC, and the output terminal of the input unit 220 is electrically coupled to the control node A.
驱动单元240的第一输入端电性耦接于控制节点A，驱动单元240的第二输入端用来接收频率信号HC，且驱动单元240的输出端用来输出本级栅极驱动信号G[n]。其中，上述的频率信号XHC与频率信号HC互为反相。The first input terminal of the driving unit 240 is electrically coupled to the control node A, the second input terminal of the driving unit 240 is used to receive the frequency signal HC, and the output terminal of the driving unit 240 is used to output the gate driving signal G[ n]. Wherein, the frequency signal XHC and the frequency signal HC mentioned above are opposite phases of each other.
以操作而言，输入单元220将第N-1级驱动级200a输出的栅极信号G[n-1]或初始脉冲Din(当N＝1时)传送到控制节点A，来调整控制节点A的电平电压。驱动单元240用来根据控制节点A的电平电压而输出本级栅极驱动信号G[n]。下拉单元260电性耦接输入单元220与驱动单元240。下拉单元260用来接收第N-1级驱动级200a输出的栅极信号G[n-1]或初始脉冲Din(当N＝1时)以及频率信号XHC，以将本级栅极驱动信号G[n]下拉到电压VSS。In terms of operation, the input unit 220 transmits the gate signal G[n-1] output by the N-1th driver stage 200a or the initial pulse Din (when N=1) to the control node A to adjust the control node A level voltage. The driving unit 240 is used for outputting the current-stage gate driving signal G[n] according to the level voltage of the control node A. Referring to FIG. The pull-down unit 260 is electrically coupled to the input unit 220 and the driving unit 240 . The pull-down unit 260 is used to receive the gate signal G[n-1] output by the N-1th driving stage 200a or the initial pulse Din (when N=1) and the frequency signal XHC, so as to convert the gate driving signal G of this stage to [n] Pulled down to voltage VSS.
此外，本发明提供的栅极驱动器200可产生不同类型的栅极驱动信号G[n]，而使显示数组122有不同的极性驱动方式(例如：点反转、图框反转、列反转、栏反转等等)。具体而言，图2A所示，第1级驱动级200a的输入单元220的第一输入端用来接收初始脉冲DIN，上述的不同的极性驱动方式可依据实际需求而通过初始脉冲DIN进行设定来完成。In addition, the gate driver 200 provided by the present invention can generate different types of gate driving signals G[n], so that the display array 122 has different polarity driving methods (for example: dot inversion, frame inversion, column inversion turn, column inversion, etc.). Specifically, as shown in FIG. 2A , the first input terminal of the input unit 220 of the first-level driver 200a is used to receive the initial pulse DIN, and the above-mentioned different polarity driving methods can be set through the initial pulse DIN according to actual needs. set to finish.
以下段落将提出各个实施例，来说明上述驱动级200a的功能与应用，但本发明并不仅限于以下所列的实施例。The following paragraphs will propose various embodiments to illustrate the functions and applications of the driver stage 200a, but the present invention is not limited to the following embodiments.
请参照图3，图3为根据本发明提供的实施例绘示的第N级驱动级300的示意图。如图3所示，输入单元220包含开关T11与开关T12。开关T11的控制端电性耦接输入单元220的第一输入端，以接收第N-1级驱动级200a输出的栅极驱动信号G[n-1]或初始脉冲Din(若N＝1时)，且开关T11的第一端电性耦接开关T11的控制端。开关T12的控制端电性耦接输入单元220的第二输入端，以接收频率信号XHC。开关T12的第一端电性耦接开关T11的第二端，开关T12的第二端电性耦接至输入单元220的输出端(也就是控制节点A)。如此，当开关T11与开关T12都导通时，第N-1级驱动级200a输出的栅极驱动信号G[n-1]可传送到控制节点A，以调整控制节点A的电平电压。Please refer to FIG. 3 . FIG. 3 is a schematic diagram of an Nth driver stage 300 according to an embodiment of the present invention. As shown in FIG. 3 , the input unit 220 includes a switch T11 and a switch T12 . The control end of the switch T11 is electrically coupled to the first input end of the input unit 220 to receive the gate drive signal G[n-1] or the initial pulse Din (if N=1) output by the N-1th driver stage 200a ), and the first terminal of the switch T11 is electrically coupled to the control terminal of the switch T11. The control end of the switch T12 is electrically coupled to the second input end of the input unit 220 to receive the frequency signal XHC. The first end of the switch T12 is electrically coupled to the second end of the switch T11 , and the second end of the switch T12 is electrically coupled to the output end of the input unit 220 (ie, the control node A). In this way, when both the switch T11 and the switch T12 are turned on, the gate driving signal G[n−1] outputted by the N−1th driving stage 200 a can be transmitted to the control node A to adjust the level voltage of the control node A.
再者，如图3所示，驱动单元240包含开关T21与电容C。开关T21的控制端电性耦接到驱动单元240的第一输入端(也就是控制节点A)，开关T21的第一端电性耦接驱动单元240的第二输入端，以接收频率信号HC，且开关T21的第二端电性耦接到驱动单元240的输出端，以输出本级栅极驱动信号G[n]。电容C电性耦接控制节点A与开关T21之间，以提供稳压作用。Furthermore, as shown in FIG. 3 , the driving unit 240 includes a switch T21 and a capacitor C. As shown in FIG. The control terminal of the switch T21 is electrically coupled to the first input terminal of the driving unit 240 (ie, the control node A), and the first terminal of the switch T21 is electrically coupled to the second input terminal of the driving unit 240 to receive the frequency signal HC , and the second terminal of the switch T21 is electrically coupled to the output terminal of the driving unit 240 to output the gate driving signal G[n] of the current stage. The capacitor C is electrically coupled between the control node A and the switch T21 to provide voltage stabilization.
下拉单元260包含下拉控制电路262与下拉电路264。下拉控制电路262用来根据第N-1级驱动级输出的栅极驱动信号G[n-1]或初始脉冲Din(若N＝1时)调整控制节点B的电平电压。下拉电路262电性耦接控制节点B，并用来根据控制节点B的电平电压而将本级栅极驱动信号G[n]下拉到电压VSS，其中电压VSS为低电平电压。The pull-down unit 260 includes a pull-down control circuit 262 and a pull-down circuit 264 . The pull-down control circuit 262 is used to adjust the level voltage of the control node B according to the gate driving signal G[n-1] output by the N-1th driving stage or the initial pulse Din (if N=1). The pull-down circuit 262 is electrically coupled to the control node B, and is used for pulling down the current-stage gate driving signal G[n] to the voltage VSS according to the level voltage of the control node B, wherein the voltage VSS is a low-level voltage.
具体而言，下拉控制电路262包含开关T41、开关T42、开关T43与开关T44。开关T41的控制端用来接收频率信号XHC，且开关T41的第一端电性耦接开关T41的控制端。开关T43的控制端电性耦接开关T41的第二端，开关T43的第一端电性耦接开关T41的第一端，且开关T43的第二端电性耦接控制节点B。开关T42的控制端用来接收第N-1级驱动级200a输出的栅极驱动信号G[n-1]或初始脉冲Din(若N＝1时)。开关T42的控制端用来接收第N-1级驱动级200a输出的栅极驱动信号G[n-1]或初始脉冲Din(若N＝1时)，开关T42的第一端电性耦接开关T41的第二端，且开关T42的第二端用来接收电压VSS。开关T44的控制端用来接收第N-1级驱动级200a输出的栅极驱动信号G[n-1]或初始脉冲Din(若N＝1时)，开关T44的第一端电性耦接控制节点B，且开关T44的第二端用来接收电压VSS。Specifically, the pull-down control circuit 262 includes a switch T41 , a switch T42 , a switch T43 and a switch T44 . The control end of the switch T41 is used to receive the frequency signal XHC, and the first end of the switch T41 is electrically coupled to the control end of the switch T41. The control terminal of the switch T43 is electrically coupled to the second terminal of the switch T41 , the first terminal of the switch T43 is electrically coupled to the first terminal of the switch T41 , and the second terminal of the switch T43 is electrically coupled to the control node B. The control end of the switch T42 is used to receive the gate driving signal G[n−1] or the initial pulse Din (if N=1) output by the N−1th driving stage 200a. The control end of the switch T42 is used to receive the gate drive signal G[n-1] output by the N-1th driver stage 200a or the initial pulse Din (if N=1), and the first end of the switch T42 is electrically coupled to The second end of the switch T41 and the second end of the switch T42 are used to receive the voltage VSS. The control end of the switch T44 is used to receive the gate drive signal G[n-1] output by the N-1th driver stage 200a or the initial pulse Din (if N=1), and the first end of the switch T44 is electrically coupled to The node B is controlled, and the second end of the switch T44 is used to receive the voltage VSS.
接着，如图3所示，下拉电路264包含开关T32与开关T31。开关T32的控制端电性耦接控制节点B，开关T32的第一端电性耦接控制节点A，且开关T32的第二端用来接收本级栅极驱动信号G[n]。开关T31的控制端电性耦接控制节点B，开关T31的第一端电性耦接开关T21的第二端，且开关T31的第二端用来接收电压VSS。Next, as shown in FIG. 3 , the pull-down circuit 264 includes a switch T32 and a switch T31 . The control end of the switch T32 is electrically coupled to the control node B, the first end of the switch T32 is electrically coupled to the control node A, and the second end of the switch T32 is used to receive the gate driving signal G[n] of the current stage. The control end of the switch T31 is electrically coupled to the control node B, the first end of the switch T31 is electrically coupled to the second end of the switch T21 , and the second end of the switch T31 is used to receive the voltage VSS.
图4根据本发明提供的实施例绘示图3中的驱动级300的操作的信号时序示意图。如图4所示，在此实施例中，初始脉冲Din设置具有连续的脉冲P1与脉冲P2。如此，可使显示数组122以点反转、列反转等驱动方式进行操作。FIG. 4 is a schematic diagram illustrating the signal timing of the operation of the driver stage 300 in FIG. 3 according to an embodiment of the present invention. As shown in FIG. 4 , in this embodiment, the initial pulse Din is set to have consecutive pulses P1 and P2 . In this way, the display array 122 can be operated in driving modes such as dot inversion and column inversion.
图5A是根据本发明提供的实施例绘示在时段T1内第3图的驱动级300中各开关的状态示意图。为了方便说明，请一并参照图4、图2B与图5A，驱动级300的操作将搭配上述图式一并说明。此外，下述将以第1级驱动级300为例进行说明。后续各级驱动级300的操作，可将下述说明的初始脉冲Din视为前级驱动级300所输出的栅极驱动信号G[n-1]而相应推得。FIG. 5A is a schematic diagram showing states of switches in the driver stage 300 of FIG. 3 during a time period T1 according to an embodiment of the present invention. For the convenience of description, please refer to FIG. 4 , FIG. 2B and FIG. 5A together, and the operation of the driver stage 300 will be described together with the above-mentioned figures. In addition, the description below will take the first-level driver stage 300 as an example. The operations of the subsequent driving stages 300 can be derived by considering the initial pulse Din described below as the gate driving signal G[n−1] output by the previous driving stage 300 .
如图4与图5A所示，在时段T1(也就是脉冲P1的致能期间)时，初始脉冲Din的脉冲P1输入到开关T11与开关T42，而导通开关T11、开关T42。由于此时的频率信号XHC为高电平电压，开关T12与开关T41因此导通，且开关T43与开关T44也因此导通。如此，控制节点B的电平电压可经由开关T44而被拉低到电压VSS，以关断开关T32与开关T31。输入单元220可传输初始脉冲Din到控制节点A，以将控制节点A的电平电压拉升到电压V1，进而导通开关T21。因此，开关T21可将具有低电平电压的频率信号HC输出为本级栅极驱动信号G[1]。As shown in FIG. 4 and FIG. 5A , during the time period T1 (that is, the enabling period of the pulse P1 ), the pulse P1 of the initial pulse Din is input to the switch T11 and the switch T42 to turn on the switch T11 and the switch T42 . Since the frequency signal XHC is at a high level voltage at this time, the switch T12 and the switch T41 are turned on, and the switch T43 and the switch T44 are also turned on. In this way, the level voltage of the control node B can be pulled down to the voltage VSS via the switch T44 to turn off the switch T32 and the switch T31 . The input unit 220 can transmit the initial pulse Din to the control node A, so as to pull up the level voltage of the control node A to the voltage V1, and then turn on the switch T21. Therefore, the switch T21 can output the frequency signal HC with a low-level voltage as the gate driving signal G[ 1 ] of the current stage.
值得注意的是，在本发明提供的各个实施例中，开关T32之间的电压差由控制节点A与本级栅极驱动信号G[1]的电平电压所决定。熟知的栅极驱动器多以控制节点A的电平电压与电压VSS决定下拉电路的开关的电压差，而本发明给出的内容所示的驱动极300可通过此种设置方式减小开关T32的第一端与第二端之间的电压差，使得开关T32的漏电流可明显减少，进而改善驱动级300的操作可靠度。It should be noted that, in various embodiments provided by the present invention, the voltage difference between the switches T32 is determined by the level voltage of the control node A and the gate driving signal G[1] of the current stage. The well-known gate driver mostly determines the voltage difference of the switch of the pull-down circuit by the level voltage of the control node A and the voltage VSS, and the driving electrode 300 shown in the content of the present invention can reduce the voltage difference of the switch T32 through this setting method. The voltage difference between the first terminal and the second terminal can significantly reduce the leakage current of the switch T32 , thereby improving the operation reliability of the driving stage 300 .
图5B是根据本发明提供的实施例绘示在时段T2内第3图的驱动级300中各开关的状态示意图。如图4与图5B所示，在时段T2(也就是脉冲P1的致能期间与脉冲P2的致能期间之间的时间)时，初始脉冲Din的脉冲P1进入禁能期间，且频率信号XHC也切换到低电平电压。因此，开关T11、开关T12、开关T41、开关T42、开关T43、开关T44、开关T32与开关T31都为关断。由于控制节点A的电平电压在先前时段T1内已被拉升到电压V1，所以开关T21仍可保持导通。如此一来，在时段T2内，频率信号HC切换到高电平电压，并经由开关T21而输出为具有高电平电压的本级栅极驱动信号G[1]，以让像素数组122进行预充电的操作。此外，本级栅极驱动信号G[1]会经由电容C而对控制节点A再次充电，而使控制节点A的电平电压上拉到电压V2。FIG. 5B is a schematic diagram illustrating the state of each switch in the driver stage 300 of FIG. 3 during the time period T2 according to an embodiment of the present invention. As shown in FIG. 4 and FIG. 5B , during the period T2 (that is, the time between the enable period of the pulse P1 and the enable period of the pulse P2), the pulse P1 of the initial pulse Din enters the disable period, and the frequency signal XHC also switches to a low level voltage. Therefore, the switch T11 , the switch T12 , the switch T41 , the switch T42 , the switch T43 , the switch T44 , the switch T32 and the switch T31 are all turned off. Since the level voltage of the control node A has been pulled up to the voltage V1 in the previous period T1, the switch T21 can still be kept on. In this way, in the period T2, the frequency signal HC is switched to a high-level voltage, and is output as a current-stage gate driving signal G[1] with a high-level voltage through the switch T21, so that the pixel array 122 performs pre-setting. Charging operation. In addition, the gate driving signal G[ 1 ] of the current stage will recharge the control node A through the capacitor C, so that the level voltage of the control node A is pulled up to the voltage V2 .
再者，如图4所示，在时段T3时，初始脉冲Din进入脉冲P2的致能期间，而频率信号XHC切换到高电平电压。此时，驱动级300的各个开关的状态会与先前图5A相同，也就是开关T11、开关T12、开关T2、开关T41、开关T42、开关T43与开关T44为导通，且开关T32与开关T31为关断。Furthermore, as shown in FIG. 4 , during the period T3 , the initial pulse Din enters the enabling period of the pulse P2 , and the frequency signal XHC switches to a high level voltage. At this time, the state of each switch of the driving stage 300 will be the same as that of the previous FIG. for shutdown.
同时，频率信号HC切换到低电平电压，而使控制节点A的电平电压经由驱动单元240下拉到电压V1。然而，实际操作中，由于控制节点A的电平电压在时段T2已经充电到较高的电压V2，因此在时段T3时，控制节点A的电平电压仅会下拉到电压V3，其中电压V3高于电压V1，且V3＝V1+ΔV。在各个实施例中，ΔV大约为1～3V。At the same time, the frequency signal HC is switched to a low level voltage, so that the level voltage of the control node A is pulled down to the voltage V1 via the driving unit 240 . However, in actual operation, since the level voltage of the control node A has been charged to a higher voltage V2 during the period T2, the level voltage of the control node A will only be pulled down to the voltage V3 during the period T3, where the voltage V3 is high At the voltage V1, and V3=V1+ΔV. In various embodiments, ΔV is about 1-3V.
请再次参照图4，在时段T4(也就是脉冲P2的致能期间后)时，初始脉冲Din切换到低电平电压，且频率信号XHC也切换到低电平电压。此时，驱动级300的各个开关的状态会与先前图5B相同，也就是开关T11、开关T12、开关T32、开关T31、开关T41、开关T42、开关T43与开关T44为关断，且开关T21为导通。此时，频率信号HC切换到高电平电压，并经由开关T21而输出为具有高电平电压的本级栅极驱动信号G[1]，以让像素数组122进行写入数据信号的操作。Referring to FIG. 4 again, during the time period T4 (that is, after the enabling period of the pulse P2 ), the initial pulse Din switches to a low-level voltage, and the frequency signal XHC also switches to a low-level voltage. At this time, the state of each switch of the driving stage 300 will be the same as that of FIG. for conduction. At this time, the frequency signal HC is switched to a high level voltage, and outputted as a current-stage gate driving signal G[1] with a high level voltage through the switch T21 , so that the pixel array 122 performs an operation of writing data signals.
同时，本级栅极驱动信号G[1]会再次经由电容C而对控制节点A充电，而使控制节点A的电平电压上拉到电压V2。如先前所述，实际操作中，由于控制节点A的电平电压在时段T3已经提升到较高的电压V3。因此，在相同的充电时间下，控制节点A的电平电压在时段T4可被拉升到更高的电压V4，也使得本级栅极驱动信号G[1]也随之提升，其中电压V4高于电压V2，且电压V4＝V2+ΔV。At the same time, the gate driving signal G[1] of the current stage will charge the control node A again through the capacitor C, so that the level voltage of the control node A is pulled up to the voltage V2. As mentioned earlier, in actual operation, since the level voltage of the control node A has been raised to a higher voltage V3 in the time period T3. Therefore, under the same charging time, the level voltage of the control node A can be pulled up to a higher voltage V4 in the period T4, and the gate drive signal G[1] of the current stage is also raised accordingly, where the voltage V4 It is higher than the voltage V2, and the voltage V4=V2+ΔV.
也就是说，驱动级300可在像素数组122进行写入数据信号的操作时(也就是时段T4)提供具有更高的电平电压的栅极驱动信号G[1]进行驱动，而使像素数组122中多个像素124可具有较好的充电率。因此，像素数组122中多个像素124的尺寸可以减小，以改善显示面板200的开口率(aperture ratio)。或者，可降低驱动级300中多个开关的尺寸，以使得栅极驱动器160的面积得以降低，以更符合窄边框应用的需求。That is to say, the driving stage 300 can provide the gate driving signal G[1] with a higher level voltage for driving when the pixel array 122 performs the operation of writing data signals (that is, the period T4), so that the pixel array A plurality of pixels 124 in 122 may have a better charge rate. Therefore, the size of the plurality of pixels 124 in the pixel array 122 can be reduced to improve the aperture ratio of the display panel 200 . Alternatively, the size of a plurality of switches in the driver stage 300 can be reduced, so that the area of the gate driver 160 can be reduced to better meet the requirements of narrow border applications.
图5C是根据本发明提供的实施例绘示在时段T5内图3的驱动级300中各开关的状态示意图。如图4与图5C所示，在时段T5时，初始脉冲Din与频率信号HC都为低电平电压，且频率信号XHC为高电平电压。因此，开关T12、开关T41、开关T43为导通，且开关T11、开关T42与开关T43为关断。频率信号XHC可经由开关T43而将控制节点B的电平电压拉升到高电平电压，进而导通开关T32与开关T31。如此，控制节点A的电平电压以及本级栅极驱动信号G[1]都被下拉到低电平电压(例如为电压VSS)。FIG. 5C is a schematic diagram illustrating states of switches in the driver stage 300 of FIG. 3 during the time period T5 according to an embodiment of the present invention. As shown in FIG. 4 and FIG. 5C , during the time period T5 , both the initial pulse Din and the frequency signal HC are at a low level voltage, and the frequency signal XHC is at a high level voltage. Therefore, the switch T12, the switch T41, and the switch T43 are turned on, and the switch T11, the switch T42, and the switch T43 are turned off. The frequency signal XHC can pull up the level voltage of the control node B to a high level voltage through the switch T43 , and then turn on the switch T32 and the switch T31 . In this way, the level voltage of the control node A and the gate driving signal G[ 1 ] of the current stage are both pulled down to a low level voltage (such as the voltage VSS).
图6是根据本发明内容提供的另一实施例绘示图3中的驱动级300的操作的信号时序示意图。如图4所示，在此实施例中，初始脉冲Din也可设置为仅具有单一的脉冲P1，如此可使显示数组122以图框反转、栏反转等驱动方式进行操作。在仅具有单一脉冲P1的操作，可参考前述实施例中时段T1与时段T2之间的操作说明，在此不再赘述。FIG. 6 is a schematic diagram of signal timing illustrating the operation of the driver stage 300 in FIG. 3 according to another embodiment of the disclosure. As shown in FIG. 4 , in this embodiment, the initial pulse Din can also be set to have only a single pulse P1 , so that the display array 122 can operate in frame inversion, column inversion and other driving modes. For the operation with only a single pulse P1, reference may be made to the description of the operation between the period T1 and the period T2 in the foregoing embodiments, and details will not be repeated here.
在本发明内容提供的各个实施例中，各个开关可为各类型的晶体管，例如为金属氧化物半导体场效晶体管(MOSFET)、底栅晶体管、顶栅型晶体管、薄膜晶体管等等。上述仅为例示，本发明并不以此为限。In various embodiments provided in the disclosure, each switch can be various types of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), bottom gate transistors, top gate transistors, thin film transistors and the like. The above are examples only, and the present invention is not limited thereto.
综上所述，本发明提供的显示面板与栅极驱动器可具有多种驱动方式，并可提供像素数组较高的充电率，进而可使显示面板的开口率提升，或是可使栅极驱动器的面积得以降低，以符合窄边框应用的需求。To sum up, the display panel and the gate driver provided by the present invention can have multiple driving methods, and can provide a higher charging rate of the pixel array, thereby increasing the aperture ratio of the display panel, or making the gate driver The area can be reduced to meet the needs of narrow bezel applications.
虽然本发明提供了以上实施方式，但这些实施方式并非用来限定本发明，本领域的技术人员，在不脱离权利要求书确定的本发明的精神和范围内，可以作各种的更动与润饰，因此本发明的保护范围应当由权利要求书的范围来确定。Although the present invention provides the above implementations, these implementations are not intended to limit the present invention. Those skilled in the art can make various modifications and changes without departing from the spirit and scope of the present invention defined by the claims. Modification, therefore, the protection scope of the present invention should be determined by the scope of the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103112319ATWI521490B (en) | 2014-04-02 | 2014-04-02 | Display panel and gate driver |
| TW103112319 | 2014-04-02 |
| Publication Number | Publication Date |
|---|---|
| CN104008738A CN104008738A (en) | 2014-08-27 |
| CN104008738Btrue CN104008738B (en) | 2016-10-19 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410211058.0AActiveCN104008738B (en) | 2014-04-02 | 2014-05-19 | Display Panel and Gate Driver |
| Country | Link |
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| CN (1) | CN104008738B (en) |
| TW (1) | TWI521490B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI533272B (en)* | 2014-09-26 | 2016-05-11 | 友達光電股份有限公司 | Display device and driving method thereof |
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