The application is that international filing date is the divisional application that is entitled as No. 200880003130.3rd, the patent application of " pre-distortion method of power amplifier time-delay invariant and device " on January 28th, 2008.
Female case of the application is that title is System and Method for Digital Memorized Predistortion for Wireless Communication, be filed in the U.S. Patent Application Serial Number 11/262 on October 27th, 2005, 079 part continuation application, this U.S. Patent application is again that title is the U.S. Patent Application Serial Number 10/137 of System and Method for Digital Memorized Predistortion for Wireless Communication, 556, it is now United States Patent (USP) the 6th, 985, the continuation application of No. 704, by reference these two applications are incorporated into this.The application requires the priority of aforementioned application and also requires the priority of following application: the U.S. Patent Application Serial Number 11/799 that is filed on April 30th, 2007,239 and relevant title be High Efficiency Linearization Power Amplifier For Wireless Communication, be filed in the U.S. Provisional Patent Application sequence number 60/795,820 on April 28th, 2006; Title is Power Amplifier Predistortion Methods and Apparatus, be filed in the U.S. Provisional Patent Application the 60/876th on December 22nd, 2006, No. 640 with the relevant non-interim U.S. Patent application 11/962,025 that is filed on December 20th, 2007; Title is Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus, be filed in the U.S. Provisional Patent Application sequence number 60/897,746 on January 26th, 2007; Title is Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus, be filed in the U.S. Provisional Patent Application sequence number 60/898 on January 29th, 2007, No. 312, by reference all these applications are incorporated into this.
Embodiment
In a kind of enforcement of the present invention, according to the U.S. Patent Application Serial Number 11/262 unsettled, that be filed on October 27th, 2005 being all incorporated into by reference this and attaching as appendix A and B, 079 and be filed in the technology of describing in the U.S. Patent Application Serial Number 11/799,239 on April 30th, 2007 and develop the entry for look-up table.It will be appreciated by those skilled in the art that the error range occurring is bounded in reality system; That is to say have and there is minimum value and peaked scope, and will drop within the scope of this at applicable correction factor of the time of any given sample in nearly all circumstances.By select the look-up table of suitable size and with as fill look-up table by the definite appropriate value of the method in above-mentioned patent (these values are to select) in the whole operation frequency spectrum of PA and associated system, being suitable for the correction factor that input signal respectively samples will be one of existing value in look-up table.Therefore,, once fully fill look-up table, correction factor of the present invention can temporal evolution; That is to say, they are time-independent.Although the size of look-up table can change significantly along with particular implementation and can be little as 16 entries for some systems, for more complicated enforcement, such as being suitable for the enforcement of wireless RF transmission system, it is 2 that this table will have rank12individual or more entry and can there is obviously more entry according to admissible power consumption, cost and relevant system factor.Implement for some, have been found that 212individual with 214table size between individual entry is acceptable.
In one is implemented, the look-up table of pre-distortion unit or predistorter carrys out addressing by the address set relevant with the time that can be constructed by shift register, although following stationery body discussion can implement in some versions like that parallel addressing.For current object, use shift register technology is described.The addressing of look-up table is based on following storage-compensation or memory-compensation principle, this principle by vector form in different time storage information and input vector is mapped to one of entry in look-up table.Addressing sets of entries in look-up table will obtain following output signal, and this output signal is the mapping function of corresponding input vector.Because Input Address vector comprises different time signal, so the output signal of look-up table is in fact relevant to different time information, comprise current demand signal and first top n transmitted signal, wherein N > 1 and N are integer.What result can be considered as the signal of storing in each entry of look-up table the combination of all transmitted signals in the past instead of current input signal only has a response.Conventionally, the bit length of the address vector in look-up table is determined the duration of time-delay signal to be covered.
Do not utilize latch or other auxiliary correcting circuit, pre-distortion algorithms to utilize function to be incorporated to time-delay signal combination in order to utilize look-up table unit to proofread and correct the non-linear of PA in time delay environment according to the present invention.Look-up table is stored the nonlinear transformations deriving from PA together with the time delay factor being caused by unlike signal transmission path.By in response to sample, look-up table suitably being carried out to addressing, look-up table provides and both comprises that suitable predistortion correction also comprises the correction factor of reasonable time delay compensation.The output of look-up table is the essentially no time delay error with combined this PA acquisition linearisation output so that input to be provided to PA of original input signal then.
Due to memory and the memory function of look-up table, the nonlinear characteristic of being proofreaied and correct by look-up table is not subject to time-based data limit by PA.The self-adaptive processing of look-up table and characteristic time-independent are benefits of the addressing of look-up table at least some enforcements of arranging.Implement the addressing of look-up table by comprising the collection of N bit vector data of current input signal and first top n input signal.Therefore, the address of look-up table is that length is the combination of the consecutive list entries of N.The address longer (therefore look-up table is larger) of look-up table, the scope duration wider, i.e. the admissible time delay effect of system of the time delay information that system can be held is longer.But although larger table can allow to store more information, entry a bit becomes repetition at certain, thereby larger table is given the marginal returns that successively decreases, waste memory resource and is unnecessarily increased power consumption.
The look-up table of predistortion processor is the storage-compensation principle based on input vector collection being mapped to actual signal output.Because the address packet of look-up table contains the input message from different time storage, so many signal combination of the each output signal being generated by look-up table and transmission are closely related.Therefore,, based on the layout of look-up table, it is also closely relevant with the combined information of the input signal from different time points storage that table upgrades entry.
Then with reference to Fig. 1, can understand particularly one embodiment of the present of invention.Particularly, illustrated embodiment comprises analog multiplier 11, and this multiplier receives the RF signal v of modulation from the radio frequency modulator part 10 of base stationrFand also receive predistortion correction signal v from look-up table and the relevant parts that can broadly be described as predistortion processor (below specifically discussing)p.Generally speaking, predistortion processor can be considered as ADC21 and 25 and DAC30 between all parts.The output of analogue amplifier 11 is as input Vinoffer power amplifier (PA) 12, this PA is again by output signal Vosend to antenna 13.Although the not inevitable quadrature modulator that is still generally of radio frequency modulator 10.May be embodied as by understanding multiplier 11 the multiple multipliers that are associated with one or more orthogonal signalling separately.
The modulator of input down-converter circuit 20 from base station receives Utopian reference signal VrFand setovered by local oscillator 40, thereby it will export Vdoffer AD converter 21.ADC21 is by signal Vdconvert digital form (as I and Q signal) to, wherein it offers digital predistortion processor and offers respectively particularly variable 22I and 22Q as a pair of input.
The feedback down-conversion converter circuit 26 of also being setovered by local oscillator 40 receives original feedback signal V from the output of PAo(t) and by feedback signal Vfoffer feedback ADC25.The numeral output of this ADC25 is then by the second input, feedback signal offers digital predistortion processor and offers particularly variable 24I and 24Q.Below digital output signal Vr is offered DAC30 by the concrete digital pre-distortion of discussing, and this DAC30 converts digital signal to analog form, wherein it in multiplier 11 with the RF signal combination of modulation.
As shown in fig. 1, address date shaper 32I-32Q receives input and is designed to generate the desired signal form for look-up table 33I/Q from ADC21I/Q.Data formation device 32I/Q carries out addressing to the mnemon in look-up table 33I/Q, and wherein independent I and Q output are offered adder 31 by look-up table.May be embodied as one or more look-up table by understanding look-up table 33.The address being provided by address shaper 32I-32Q can be considered as look-up table keyword or address.
Predistortion controller look-up table 33I-33Q is designed to the mnemon of storage for the linearizing pre-distorted signals of high power amplifier.Pre-distorted signals in table is based on passing through more satisfactory signal vdwith feedback signal vfthe error generating and the adaptive algorithm presenting.Be stored in the data of table in 33I-Q and can upgrade and form by adaptive iteration as mentioned below the data of the Numerical Index that reflects non-linearity of power amplifier characteristic.
By at idealized signal VrF(t) with feedback signal Vo(t) AM-AM between and the comparison of AM-PM information, digital predistortion processor is calculated the output signal V being caused by the nonlinear transmission characteristic of high power amplifier 12o(t) amplitude and the error of phase component.
Based on by aforementioned relatively obtain control information, predistortion processor is based at United States Patent (USP) the 6th, 985,704, AM-AM and AM-PM distortion that the compensating signal that in number, disclosed lookup table algorithm is calculated and generation has the characteristic contrary with the transforming function transformation function of PA12 is adaptively caused by PA12 with predistortion.
The output v of predistortion look-up table 33I-33Qpafter adder 31 and digital-to-analog converter 30, be fed to multiplier 11 to revise the RF signal from the modulation of modulator 10.The output of multiplier be in order to input to high power amplifier produce precompensation, its non-linear contrary required pre-distorted signals v non-linear and power amplifier 12in(k).
It will be appreciated by those skilled in the art that as ideal signal vrFwith feedback signal Vo(t) when these two signals arrive predistortion controller, between these signals, may there is signal difference.The time delay difference between two signals that cause in the different paths that time difference is advanced when going to controller by each leisure.This signal time postpones parameter and other environmental factor and changing randomly that can be based on circuit and parts.Result is to be difficult to estimate, to calculate and regulate signal difference such in on-the-spot applied environment.In order to overcome this problem, the present invention is by using by the United States Patent (USP) of previously having quoted the 6th, and a kind of algorithm of 985, No. 704 instructions regulates this time delay adaptively.
The use of look-up table 33 is allowed memory function to be incorporated at least some embodiment of the present invention.The look-up table of predistortion controller is the storage compensation principle based on input data set being mapped to numeral output and adaptive updates.Based on the function of storage, each output signal of look-up table in fact with current and previous transmitted signal all about, therefore there is following memory function: it not only compensates the non-linear of PA and has avoided for the needs such as normally used special time delay equalization circuit in prior art.
Based on the framework of predistortion shown in Fig. 1, the non-linear output signal v by predistortion processor of power amplifierpproofread and correct.Signal vpwith the input of the RF signal multiplication of modulating using generation pre-distorted signals as power amplifier.In fact, the input signal of power amplifier is can be aspect amplitude/envelope controlled and at complex gain signal adjustable aspect phase place.The relation of input and output can be described as following complex gain expression formula:
vin＝vRFvp＝vRFF(V) (1)
Wherein vpthat the predistortion processor being generated by the mapping function F of look-up table is exported.Conventionally, mapping function F is unknown and be difficult to express with mathematical way.But, can pass through according to the entry in adaptive algorithm renewal look-up table to realize and { 0,1}n→ vpf is determined in likely shining upon that these relations are corresponding adaptively.
Therefore look-up table is mapped to actual output v by each N position Input Address vector set Vp.In fact the transmitted signal sequence through power amplifier from current time to the first top n time that, the vector representative of N dimension address is expressed by following formula:
V(k)＝(d1(k)，d2(k)，...，dN(k))T (2)
The wherein each data d in above-mentioned vector Vibe be expressed as follows 1 or 0:
Di(k)=0 or 1, wherein 1≤i≤N (3)
In a kind of enforcement shown in Fig. 2, the serial shift register 205 that addressing is carried out by the each corresponding entry to look-up table during predistortion process in the address of look-up table 200 forms.Because the information of addressing is relevant with current and first top n transmitted signal, send the function of data, be therefore incorporated to time delay corrective element so the output signal 210 of look-up table can be considered as last N.Upgrade 220 and upgrade adaptively look-up table by combine adaptive error 215 and look-up table in combiner 225.Even presentative time late effect in the time that same signal passes different transmission path, the layout that is configured to the look-up table of predistortion processor still can be by the correction signal of combination systematically for the gamma correction of PA and the processing of time delay equalization.
Make to there is no need to use additional period delay disposal and relevant circuit to thering is the technology that look-up table that the predistortion of combination and time delay proofread and correct uses.Because the address packet of look-up table contains the control information of current and previous transmission, so be the many temporal informations combinations of enriching signal component that comprise from current time to the first top n time inherently from each output signal of look-up table.Result pre-distortion algorithms has the built-in mechanism in order to compensating signal late effect.This obtains a kind of than the obvious simpler and easy and more effective pre-distortion structure of traditional solution.
In the predistortion framework as shown in Figures 1 and 2 with look-up table, memory table is by its address register addressing.The figure place length of shift register is determined the size of look-up table and is therefore determined the time delay scope, the i.e. maximum constraints of time late effect that cover.Each data set of storing in look-up table has unique allocation index.This allocation index of data set is corresponding to the input data sampling time point of data set.Then utilize that allocation index calculates as non-linear error calibration for PA time calibration this purpose timestamp.In other words, at each predistortion point computing time, pre-distortion algorithms is selected from only data set of concrete addressing entry as the output of look-up table for the further non-linear error calibration processing of PA.If selected output signal is only relevant with current time transmitted signal and irrelevant with other transmitted signal, during pre-distortion, must consider by the time delay causing by the current transmitted signal of different transmission path to the accurate Signal Matching between reference and feedback signal is provided.
By relevant with the figure place of address register the time delay scope being covered by look-up table.For the look-up table with N bit address register, the size of lookup table entries is M=2n-1.This means that all data that have M entry and be stored in entry in look-up table are to cover the function of current time k to the address vector of a previous k-M+1 time.Input Address vector set A can be expressed as:
A＝{V(k)，V(k-1)，...，V(k-M+1)} (4)
Wherein V (k) is the Input Address vector at time k, and this vector recording needle may predistortion information to the nonlinear M of PA and signal and the time-delay signal component of the current transmission of each information recording.
Based on memory-compensation principle, the time delay look-up table configuration of combination relates to catch the simple and easy logical operation and the signal processing that postpone through the signal time of different transmission path.Particularly, due to the characteristic of time-delay invariant, this predistortion framework can be in wider dynamic range and is processed and to proofread and correct PA non-linear without adjunct circuit and algorithm.
Those skilled in the art also will understand for some embodiment, the normally larger and sample rate higher embodiment relatively of look-up table, can use parallel addressing scheme, than parallel addressing scheme as shown in Figure 3, this scheme is except being used to identical with Fig. 2 in fact the parallel input 300 of look-up table.If closely obtain together the data point (than faster sample rate) of sampling, thereby effectively become identical for the correction factor of sample t and sample t+1, can use parallel addressing mode to carry out addressing to look-up table.In certain embodiments, if the size of look-up table is large and meet computing capability and miscellaneous equipment problem fully, parallel addressing mode can be given compared with serial addressing mode and the performance of Yan Gengjia in the environment that uses very fast sample rate.
Describe particularly the present invention who comprises some embodiment and alternate embodiment completely, it will be appreciated by those skilled in the art that many other existing within the scope of the invention substitutes and equivalent embodiment.Therefore the present invention not will in fact only be limited by claims by foregoing description.