技术领域technical field
本发明实施例涉及计算机技术，尤其涉及一种压缩内存访问控制方法、装置及系统。The embodiments of the present invention relate to computer technology, and in particular to a compressed memory access control method, device and system.
背景技术Background technique
在计算机系统中，处理器访问内存的性能是计算机系统的一个重要性能指标，特别是随着多核处理器计算机技术的发展，内存的访问性能已成为制约计算机技术发展的关键因素之一。其中，采用内存压缩技术就是一种可提高处理器访问内存性能的一项技术，其是将数据以压缩的格式存储的内存中，当处理器需要读取数据时，可直接读取压缩的数据，这样，在读取同样长度数据的情况下，可节省访问内存的带宽，提高内存的访问效率，同时也可节约内存的物理存储空间。In computer systems, the performance of processor access to memory is an important performance index of computer systems, especially with the development of multi-core processor computer technology, memory access performance has become one of the key factors restricting the development of computer technology. Among them, the use of memory compression technology is a technology that can improve the performance of processor access to memory. It stores data in a compressed format in the memory. When the processor needs to read data, it can directly read the compressed data. , in this way, in the case of reading data of the same length, the bandwidth for accessing the memory can be saved, the access efficiency of the memory can be improved, and the physical storage space of the memory can also be saved.
现有的内存压缩技术中，通常是在内存控制器上集成数据压缩解压缩功能模块，这样，内存控制器通过内存总线从内存芯片上读取的压缩数据，可直接在内存控制器进行解压缩处理；同样地，写入内存中的数据也可在内存控制器中压缩后，再通过内存总线写入内存芯片。具体地，内存控制器上维护有压缩翻译表（Compression Translation Table，CTT），该CTT包括多个CTT项，每个CTT项有16个字节，记录了实际地址（即数据压缩前的地址）空间中1K数据在内存芯片的物理地址空间中的位置，且每个CTT项中包括四个指针，每个指针指向4个基本块，每个基本块对应于内存芯片上的256字节的物理地址空间，即内存芯片中存储的压缩数据是分布在各基本块上，当内存控制器需要读取数据时，可基于CTT来查找所要读取的实际地址对应的物理地址段，并将物理地址段内存储压缩数据读出，并利用内存控制器上的压缩解压缩模块进行解压缩处理后，提供给处理器。In the existing memory compression technology, the data compression and decompression function module is usually integrated on the memory controller, so that the compressed data read by the memory controller from the memory chip through the memory bus can be directly decompressed in the memory controller Similarly, the data written into the memory can also be compressed in the memory controller, and then written into the memory chip through the memory bus. Specifically, a compression translation table (Compression Translation Table, CTT) is maintained on the memory controller, and the CTT includes multiple CTT items, and each CTT item has 16 bytes, recording the actual address (that is, the address before data compression) The position of 1K data in the space in the physical address space of the memory chip, and each CTT item includes four pointers, each pointer points to 4 basic blocks, and each basic block corresponds to a 256-byte physical address on the memory chip The address space, that is, the compressed data stored in the memory chip is distributed on each basic block. When the memory controller needs to read data, it can find the physical address segment corresponding to the actual address to be read based on CTT, and the physical address The compressed data stored in the segment is read out, decompressed by the compression and decompression module on the memory controller, and provided to the processor.
但是，现有的内存压缩技术中，在读取数据时，每次均需要读取至少一个CTT项对应的物理地址空间，即不管处理器需要的数据是多大，例如1K字节中的100字节，也要将这1K字节对应的压缩数据从内存芯片的四个基本块中取出，从而使得读取内存的带宽被无用数据浪费，导致内存访问带宽浪费，进而降低内存访问性能。However, in the existing memory compression technology, when reading data, it is necessary to read the physical address space corresponding to at least one CTT item each time, that is, no matter how much data the processor needs, for example, 100 words in 1K bytes section, the compressed data corresponding to this 1K byte should also be taken out from the four basic blocks of the memory chip, so that the bandwidth for reading the memory is wasted by useless data, resulting in a waste of memory access bandwidth, thereby reducing memory access performance.
发明内容Contents of the invention
本发明实施例提供一种压缩内存访问控制方法、装置及系统，可克服现有压缩内存技术中访问压缩内存带来的带宽浪费问题，提高内存访问性能。Embodiments of the present invention provide a compressed memory access control method, device and system, which can overcome the problem of bandwidth waste caused by accessing compressed memory in the existing compressed memory technology, and improve memory access performance.
第一方面，本发明实施例提供一种压缩内存访问控制方法，包括：In a first aspect, an embodiment of the present invention provides a compressed memory access control method, including:
接收内存控制器发送的读请求消息，所述读请求消息包括待读数据的实际地址；receiving a read request message sent by the memory controller, where the read request message includes the actual address of the data to be read;
根据所述待读数据的实际地址，从内存映射关系表中查询得到所述实际地址对应的物理地址段，所述内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；According to the actual address of the data to be read, the physical address segment corresponding to the actual address is obtained by querying the memory mapping relationship table, and the corresponding relationship between the actual address and the physical address segment of the memory chip is recorded in the memory mapping relationship table;
从内存芯片中读取所述物理地址段存储的数据，获得与所述实际地址对应的所述待读数据；Reading the data stored in the physical address segment from the memory chip to obtain the data to be read corresponding to the actual address;
将所述待读数据返回至所述内存控制器。returning the data to be read to the memory controller.
第二方面，本发明实施例提供一种压缩内存访问控制方法，包括：In a second aspect, an embodiment of the present invention provides a compressed memory access control method, including:
接收内存控制器发送的写请求消息，所述写请求消息包括待写数据的实际地址；receiving a write request message sent by the memory controller, where the write request message includes the actual address of the data to be written;
根据所述待写数据的实际地址，从内存映射关系表中查询得到所述实际地址对应的物理地址段，所述内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；According to the actual address of the data to be written, the physical address segment corresponding to the actual address is obtained by querying the memory mapping relationship table, and the corresponding relationship between the actual address and the physical address segment of the memory chip is recorded in the memory mapping relationship table;
从内存芯片中读取所述物理地址段存储的原始数据，并将所述待写数据与所述原始数据合成，得到合成数据；reading the original data stored in the physical address segment from the memory chip, and synthesizing the data to be written with the original data to obtain synthetic data;
将所述合成数据写入所述内存芯片。writing the synthesized data into the memory chip.
第三方面，本发明实施例提供一种压缩内存访问控制装置，包括：In a third aspect, an embodiment of the present invention provides a compressed memory access control device, including:
读请求消息接收模块，用于接收内存控制器发送的读请求消息，所述读请求消息包括待读数据的实际地址；The read request message receiving module is used to receive the read request message sent by the memory controller, and the read request message includes the actual address of the data to be read;
物理地址查询模块，用于根据所述待读数据的实际地址，从内存映射关系表中查询得到所述实际地址对应的物理地址段，所述内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；The physical address query module is used to query the physical address segment corresponding to the actual address from the memory mapping relationship table according to the actual address of the data to be read, and the memory mapping relationship table records the actual address and the address of the memory chip Correspondence between physical address segments;
待读数据获取模块，用于从内存芯片中读取所述物理地址段存储的数据，获得与所述实际地址对应的所述待读数据；The data to be read acquisition module is used to read the data stored in the physical address segment from the memory chip, and obtain the data to be read corresponding to the actual address;
待读数据返回模块，用于将所述待读数据返回至所述内存控制器。The data to be read returning module is used to return the data to be read to the memory controller.
第四方面，本发明实施例提供一种压缩内存访问控制装置，包括：In a fourth aspect, an embodiment of the present invention provides a compressed memory access control device, including:
写请求信息接收模块，用于接收内存控制器发送的写请求消息，所述写请求消息包括待写数据的实际地址；The write request information receiving module is used to receive the write request message sent by the memory controller, and the write request message includes the actual address of the data to be written;
物理地址查询模块，用于根据所述待写数据的实际地址，从内存映射关系表中查询得到所述实际地址对应的物理地址段，所述内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；The physical address query module is used to query the physical address segment corresponding to the actual address from the memory mapping relationship table according to the actual address of the data to be written, and the memory mapping relationship table records the actual address and the address of the memory chip Correspondence between physical address segments;
数据合成模块，用于从内存芯片中读取所述物理地址段存储的原始数据，并将所述待写数据与所述原始数据合成，得到合成数据；A data synthesis module, configured to read the original data stored in the physical address segment from the memory chip, and synthesize the data to be written with the original data to obtain synthesized data;
数据写入模块，用于将所述合成数据写入所述内存芯片。a data writing module, configured to write the synthesized data into the memory chip.
第五方面，本发明实施例提供一种压缩内存访问控制系统，包括内存调度器和内存芯片，所述内存调度器上述本发明实施例提供的压缩内存访问控制装置。In a fifth aspect, an embodiment of the present invention provides a compressed memory access control system, including a memory scheduler and a memory chip, and the memory scheduler is the above-mentioned compressed memory access control device provided by the embodiment of the present invention.
本发明实施例可基于内存控制器发送的读请求消息中的实际地址，从内存映射关系表中获取与实际地址对应的物理地址段，从而可从内存芯片中获取该实际地址对应的待读数据，使得内存访问过程中，可获得所需的实际数据，可避免现有需要获取无用数据带来的带宽浪费问题，减少压缩内存访问的带宽资源占用率，提高内存访问性能。In the embodiment of the present invention, based on the actual address in the read request message sent by the memory controller, the physical address segment corresponding to the actual address can be obtained from the memory mapping relationship table, so that the data to be read corresponding to the actual address can be obtained from the memory chip , so that the required actual data can be obtained during the memory access process, which can avoid the bandwidth waste caused by the need to obtain useless data, reduce the bandwidth resource occupancy rate of compressed memory access, and improve memory access performance.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明实施例一提供的压缩内存访问控制方法的流程示意图;FIG. 1 is a schematic flowchart of a compressed memory access control method provided by Embodiment 1 of the present invention;
图2A为本发明实施例二提供的压缩内存访问控制方法的流程示意图;FIG. 2A is a schematic flowchart of a compressed memory access control method provided in Embodiment 2 of the present invention;
图2B为本发明实施例中内存映射关系表的索引关系示意图;FIG. 2B is a schematic diagram of the index relationship of the memory mapping relationship table in the embodiment of the present invention;
图3为本发明实施例三提供的压缩内存访问控制方法的流程示意图;FIG. 3 is a schematic flowchart of a compressed memory access control method provided by Embodiment 3 of the present invention;
图4为本发明实施例四提供的压缩内存访问控制方法的流程示意图；FIG. 4 is a schematic flowchart of a compressed memory access control method provided in Embodiment 4 of the present invention;
图5为本发明实施例五提供的压缩内存访问控制方法的流程示意图；FIG. 5 is a schematic flowchart of a compressed memory access control method provided in Embodiment 5 of the present invention;
图6为本发明实施例六提供的压缩内存访问控制方法的流程示意图；FIG. 6 is a schematic flowchart of a compressed memory access control method provided in Embodiment 6 of the present invention;
图7为本发明实施例七提供的压缩内存访问控制装置的结构示意图；FIG. 7 is a schematic structural diagram of a compressed memory access control device provided by Embodiment 7 of the present invention;
图8A为本发明实施例八提供的压缩内存访问控制装置的结构示意图；FIG. 8A is a schematic structural diagram of a compressed memory access control device provided in Embodiment 8 of the present invention;
图8B为本发明实施例中待读数据获取模块的结构示意图；FIG. 8B is a schematic structural diagram of a data acquisition module to be read in an embodiment of the present invention;
图9为本发明实施例九提供的压缩内存访问控制装置的结构示意图；FIG. 9 is a schematic structural diagram of a compressed memory access control device provided in Embodiment 9 of the present invention;
图10A为本发明实施例十提供的压缩内存访问控制装置的结构示意图；FIG. 10A is a schematic structural diagram of a compressed memory access control device provided in Embodiment 10 of the present invention;
图10B为本发明实施例中数据合成模块的结构示意图；FIG. 10B is a schematic structural diagram of a data synthesis module in an embodiment of the present invention;
图11为本发明实施例十一提供的压缩内存访问控制系统的结构示意图。FIG. 11 is a schematic structural diagram of a compressed memory access control system provided by Embodiment 11 of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are the Some, but not all, embodiments are invented. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本实施例提供的压缩内存访问控制方法可适用于压缩内存的访问控制中，其中，本实施例中所述的压缩内存访问控制系统包括内存调度器，该内存调度器与各内存芯片连接，用于管理各内存芯片；且该内存调度器还与内存控制器连接，可接收内存控制器发送的消息指令，对消息指令进行解析，并可基于该消息指令对内存芯片进行操作，例如读数据或写数据等。下面将会分别以读请求消息和写请求消息处理过程的具体实例，对本发明实施例对压缩内存的的访问控制进行说明。The compressed memory access control method provided in this embodiment is applicable to the access control of compressed memory, wherein the compressed memory access control system described in this embodiment includes a memory scheduler, which is connected to each memory chip for It is used to manage each memory chip; and the memory scheduler is also connected to the memory controller, which can receive the message instruction sent by the memory controller, analyze the message instruction, and operate the memory chip based on the message instruction, such as reading data or write data etc. In the following, the access control of the compressed memory in the embodiment of the present invention will be described with specific examples of the processing of the read request message and the write request message respectively.
图1为本发明实施例一提供的压缩内存访问控制方法的流程示意图。本实施例中方法可应用于上述的压缩内存访问控制系统中，其执行主体为压缩内存访问控制系统中的内存调度器，可对内存控制器发送的消息指令，本实施例中为读请求消息指令，进行处理，具体地，如图1所示，本实施例压缩内存访问控制方法包括：FIG. 1 is a schematic flowchart of a compressed memory access control method provided by Embodiment 1 of the present invention. The method in this embodiment can be applied to the above-mentioned compressed memory access control system, and its executive body is the memory scheduler in the compressed memory access control system, which can send message instructions to the memory controller, which is a read request message in this embodiment Instructions are processed, specifically, as shown in Figure 1, the compression memory access control method of this embodiment includes:
步骤101、接收内存控制器发送的读请求消息，该读请求消息包括待读数据的实际地址；Step 101, receiving a read request message sent by the memory controller, the read request message including the actual address of the data to be read;
步骤102、根据待读数据的实际地址，从内存映射关系表中查询得到实际地址对应的物理地址段，该内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；Step 102, according to the actual address of the data to be read, query the physical address segment corresponding to the actual address from the memory mapping relationship table, and the corresponding relationship between the actual address and the physical address segment of the memory chip is recorded in the memory mapping relationship table;
步骤103、从内存芯片中读取该物理地址段存储的数据，获得与实际地址对应的待读数据；Step 103, read the data stored in the physical address segment from the memory chip, and obtain the data to be read corresponding to the actual address;
步骤104、将待读数据返回至内存控制器。Step 104, return the data to be read to the memory controller.
本实施例中，内存控制器发送的读请求消息，是对处理器（CPU）发出的读请求以消息包的形式发送至内存控制系统中的内存调度器，内存调度器在接收到该读请求消息后，只需要获取与该实际地址对应的物理地址段，即可从内存芯片中获取与该实际地址对应的待读数据，在获取待读数据后，可将待读数据返回至内存控制器。In this embodiment, the read request message sent by the memory controller is to send the read request sent by the processor (CPU) to the memory scheduler in the memory control system in the form of a message packet, and the memory scheduler receives the read request After receiving the message, you only need to obtain the physical address segment corresponding to the actual address to obtain the data to be read corresponding to the actual address from the memory chip. After obtaining the data to be read, the data to be read can be returned to the memory controller .
本领域技术人员可以理解，上述的读请求消息中携带的待读数据的实际地址具体可以是指待读数据的起始地址和数据长度，或者，也可以是指待读数据的起始地址和结束地址的地址段。Those skilled in the art can understand that the actual address of the data to be read carried in the above-mentioned read request message may specifically refer to the start address and data length of the data to be read, or may also refer to the start address and the length of the data to be read. The address segment of the end address.
综上，本实施例提供的压缩内存访问控制方法，可基于内存控制器发送的读请求消息中的实际地址，从内存映射关系表中获取与实际地址对应的物理地址段，从而可从内存芯片中获取该实际地址对应的待读数据，使得内存访问过程中，可获得所需的实际数据，可避免现有需要获取无用数据带来的带宽浪费问题，减少压缩内存访问的带宽资源占用率，提高内存访问性能。To sum up, the compressed memory access control method provided by this embodiment can obtain the physical address segment corresponding to the actual address from the memory mapping relationship table based on the actual address in the read request message sent by the memory controller, so that the memory chip can Obtain the data to be read corresponding to the actual address in the process of memory access, so that the actual data required can be obtained during the memory access process, which can avoid the bandwidth waste caused by the need to obtain useless data, and reduce the bandwidth resource occupancy rate of compressed memory access. Improve memory access performance.
图2A为本发明实施例二提供的压缩内存访问控制方法的流程示意图。本实施例中，压缩内存访问控制系统中的内存调度器中记录的内存映射关系表可包括多个映射项，每个映射项记录有实际地址及其对应的内存芯片的物理地址段，每个映射项中的内存芯片的物理地址段对应于内存芯片中的一段存储数据，这样，内存访问控制器请求的待读数据较长时，可从多个物理地址段中获取其所请求的数据，从而可满足各种数据长度的读请求处理中，具体地，如图2A所示，本实施例压缩内存访问控制方法包括如下步骤：FIG. 2A is a schematic flowchart of a compressed memory access control method provided by Embodiment 2 of the present invention. In this embodiment, the memory mapping relationship table recorded in the memory scheduler in the compressed memory access control system may include a plurality of mapping items, and each mapping item records an actual address and the physical address segment of the corresponding memory chip. The physical address segment of the memory chip in the mapping item corresponds to a segment of stored data in the memory chip. In this way, when the data to be read requested by the memory access controller is long, the requested data can be obtained from multiple physical address segments. In this way, the processing of read requests with various data lengths can be satisfied. Specifically, as shown in FIG. 2A, the compressed memory access control method of this embodiment includes the following steps:
步骤201、接收内存控制器发送的读请求消息，该读请求消息包括待读数据的实际地址；Step 201, receiving a read request message sent by the memory controller, the read request message including the actual address of the data to be read;
步骤202、根据待读数据的实际地址，从内存映射关系表中查询记录有该实际地址中的任一地址段的各映射项；Step 202, according to the actual address of the data to be read, query from the memory mapping relationship table for each mapping item recorded with any address segment in the actual address;
步骤203、将各映射项中记录的内存芯片的物理地址段作为各分段物理地址段，并将各分段物理地址段组合起来作为实际地址对应的物理地址段；Step 203, using the physical address segment of the memory chip recorded in each mapping item as each segmented physical address segment, and combining each segmented physical address segment as the physical address segment corresponding to the actual address;
步骤204、判断各分段物理地址段存储的数据是否包括有压缩数据，是则执行步骤205，否则，执行步骤208；Step 204, judging whether the data stored in each segmented physical address segment includes compressed data, if so, execute step 205, otherwise, execute step 208;
步骤205、从内存芯片中读取各分段物理地址段存储的各分段数据；Step 205, reading each segmented data stored in each segmented physical address segment from the memory chip;
步骤206、将各分段数据的压缩数据解压缩，并组合起来得到组合数据；Step 206, decompressing the compressed data of each segmented data, and combining them to obtain combined data;
步骤207、从该组合数据中得到与实际地址对应的待读数据，执行步骤209；Step 207, obtain the data to be read corresponding to the actual address from the combined data, and execute step 209;
步骤208、直接从内存芯片中读取实际地址对应的待读数据；Step 208, directly read the data to be read corresponding to the actual address from the memory chip;
步骤209、将该待读数据返回至内存控制器。Step 209, returning the data to be read to the memory controller.
本实施例中，内存调度器中存储的内存映射关系表中记录有内存芯片的物理地址段存储的数据的压缩信息，这样，在执行步骤204时，就可以基于该内存映射关系表中记录的各物理地址段存储的数据的压缩信息，确定各物理地址段存储的数据是否为压缩数据；同时，在执行步骤206时，可对读出的数据进行解压缩处理，以获得所需的待读数据。本领域技术人员可以理解，所述的压缩信息具体可包括数据是否压缩，以及压缩所采用的算法等信息。In this embodiment, the memory mapping relationship table stored in the memory scheduler records the compression information of the data stored in the physical address segment of the memory chip, so that when step 204 is executed, the memory mapping relationship table can be based on the The compression information of the data stored in each physical address segment determines whether the data stored in each physical address segment is compressed data; at the same time, when step 206 is performed, the read data can be decompressed to obtain the required data to be read. data. Those skilled in the art can understand that the compression information may specifically include information such as whether data is compressed, an algorithm used for compression, and the like.
上述步骤204中，当各物理地址段存储的数据位未包括有压缩数据时，说明读请求信息所要读取的待读数据在内存芯片中是以非压缩形式存储的，该种情况下，实际地址实际上就是物理地址段，或物理地址段中的一段地址，此时可执行步骤208，直接从内存芯片中，读取物理地址段中，与实际地址对应的物理地址段所存储的数据。In the above-mentioned step 204, when the data bits stored in each physical address segment do not include compressed data, it means that the data to be read to be read by the read request information is stored in an uncompressed form in the memory chip. In this case, the actual The address is actually a physical address segment, or a segment of address in the physical address segment. At this time, step 208 can be executed to directly read the data stored in the physical address segment corresponding to the actual address in the physical address segment from the memory chip.
上述步骤209中，将待读数据返回至内存控制器时，可根据需要以压缩数据形式返回至内存控制器，或者以非压缩数据形式返回至内存控制器。实际应用中，内存控制器发送的读请求消息可包括读请求优先级，该读请求优先级为高优先级或低优先级，其中，高优先级表示读请求数据获取的实时性要求较高，而低优先级则表示对读请求数据获取的实时性要求较低，因此内存调度器在将待读数据返回至内存控制器时，具体可为：在读请求的优先级为低优先级时，将待读数据以压缩包的方式返回至内存控制器，而在读请求的优先级为高优先级时，可直接将获得的待读数据返回至内存控制器，避免读请求时间过长，提高读请求处理的实时性。In the above step 209, when the data to be read is returned to the memory controller, it may be returned to the memory controller in the form of compressed data or returned to the memory controller in the form of uncompressed data as required. In practical applications, the read request message sent by the memory controller may include the priority of the read request, and the priority of the read request is high priority or low priority, wherein the high priority indicates that the real-time requirement for data acquisition of the read request is high, The low priority means that the real-time requirements for the read request data acquisition are low. Therefore, when the memory scheduler returns the data to be read to the memory controller, it can be specifically: when the priority of the read request is low priority, the The data to be read is returned to the memory controller in the form of a compressed package, and when the priority of the read request is high, the obtained data to be read can be directly returned to the memory controller to avoid the long time of the read request and improve the read request rate. real-time processing.
上述步骤205，从内存芯片中读取各分段物理地址段存储的各分段数据之前，还可包括如下步骤：判断待读数据是否正好是物理地址段存储的数据，是则直接从内存芯片中读取物理地址段中的各分段物理地址段存储的数据，并将各分段物理地址段存储的数据组合起来，得到待读数据。实际应用中，若待读数据刚好是一个物理地址段，或多个物理地址段中存储的数据，那么只需要将各物理地址段的数据组合起来即可作为待读数据，返回至内存控制器，以提高读请求处理效率。本领域技术人员可以理解，在判断待读数据是否正好是物理地址段存储的数据时，可基于物理地址段中数据的压缩信息，确定存储的数据的长度，从而可与待读数据的数据长度，以及起始地址作比较，若完全相同，那么就说明待读数据正好是物理地址段存储的数据。Above-mentioned step 205, before reading each segmented data stored in each segmented physical address segment from the memory chip, the following steps can also be included: judging whether the data to be read is just the data stored in the physical address segment, if so, directly from the memory chip Read the data stored in each segmented physical address segment in the physical address segment, and combine the data stored in each segmented physical address segment to obtain the data to be read. In practical applications, if the data to be read is exactly one physical address segment, or the data stored in multiple physical address segments, then it is only necessary to combine the data of each physical address segment as the data to be read and return it to the memory controller , to improve read request processing efficiency. Those skilled in the art can understand that when judging whether the data to be read is just the data stored in the physical address segment, the length of the stored data can be determined based on the compression information of the data in the physical address segment, so that it can be compared with the data length of the data to be read , and the start address for comparison, if they are exactly the same, it means that the data to be read is exactly the data stored in the physical address segment.
为便于对本发明实施例的理解，下面对本发明实施例中内存映射关系表进行详细说明。To facilitate the understanding of the embodiment of the present invention, the memory mapping relationship table in the embodiment of the present invention will be described in detail below.
图2B为本发明实施例中内存映射关系表的索引关系示意图。本实施例的内存映射关系表为一映射索引表，映射索引表中包括页映射项，每个页映射项中包括多个映射项，每个映射项记录有实际地址、物理地址段、数据压缩前长度、数据压缩后长度以及数据压缩算法等信息，利用该映射索引表，其可以基于哈希（hash）算法，对某一实地址在该索引表中查询到与该实地址相关的各映射项。具体地，如图2B所示，内存调度器接收到内存控制器发送的读请求中的待读数据的实际地址后，首先对实际地址进行一个哈希运算得到访问映射索引表的索引值，访问映射索引表在该入口处的链表，找到记录该实际地址所属页面的页映射表，其中，页映射表是个映射项的数组，记录了实际地址所属页面的数据占用的物理地址的情况，每一项中的物理地址段记录了一段连续数据块，考虑到压缩效率，一个映射项记录的数据块最小为256Byte，一个页映射表最多需要16个映射项。其中，一个页映射表中不同映射项对应的物理地址可以分散在内存芯片中的任何地方，而不是局限在一段连续的物理地址空间中；映射索引表可以存储在内存芯片中一段特定的保留空间内，也可以存储在内存调度器专用的缓存中。FIG. 2B is a schematic diagram of the index relationship of the memory mapping relationship table in the embodiment of the present invention. The memory mapping relationship table of this embodiment is a mapping index table, including page mapping items in the mapping index table, including multiple mapping items in each page mapping item, and each mapping item records actual address, physical address segment, data compression Information such as the length before data compression, data compression algorithm and other information, using the mapping index table, it can be based on the hash (hash) algorithm, for a certain real address in the index table to find the mappings related to the real address item. Specifically, as shown in FIG. 2B, after the memory scheduler receives the actual address of the data to be read in the read request sent by the memory controller, it first performs a hash operation on the actual address to obtain the index value of the access mapping index table, and access The linked list of the mapping index table at the entry finds the page mapping table that records the page to which the actual address belongs. The page mapping table is an array of mapping items, which records the physical address occupied by the data of the page to which the actual address belongs. Each The physical address segment in the entry records a continuous data block. Considering the compression efficiency, the minimum data block recorded in a mapping entry is 256Byte, and a page mapping table requires a maximum of 16 mapping entries. Among them, the physical addresses corresponding to different mapping items in a page mapping table can be scattered anywhere in the memory chip, rather than being limited to a continuous physical address space; the mapping index table can be stored in a specific reserved space in the memory chip It can also be stored in a cache dedicated to the memory scheduler.
图3为本发明实施例三提供的压缩内存访问控制方法的流程示意图。本实施例以压缩内存的数据读取过程中，内存控制器与内存调度器的交互对压缩内存的访问控制进行详细说明，具体地，如图3所示，本实施例方法可包括如下步骤：FIG. 3 is a schematic flowchart of a compressed memory access control method provided by Embodiment 3 of the present invention. In this embodiment, during the data reading process of the compressed memory, the interaction between the memory controller and the memory scheduler is described in detail on the access control of the compressed memory. Specifically, as shown in FIG. 3 , the method of this embodiment may include the following steps:
步骤305、内存控制器接收处理器发出的读请求；Step 305, the memory controller receives the read request sent by the processor;
步骤310、内存控制器根据该读请求所要读取的待读数据的实际地址的起始地址、数据长度、延迟、优先级等参数，构造得到读请求消息包，发送至内存调度器；Step 310, the memory controller constructs a read request message packet according to the start address, data length, delay, priority and other parameters of the actual address of the data to be read to be read by the read request, and sends it to the memory scheduler;
步骤315、内存调度器接收到该读请求消息包后，根据该请求的实际地址的起始地址及数据长度，从内存映射关系表中查询与该读请求相关的各映射项；Step 315, after the memory scheduler receives the read request message packet, according to the start address and data length of the actual address of the request, query each mapping item related to the read request from the memory mapping table;
步骤320、内存调度器根据映射项的内容判断相关的各映射项的物理地址段中存储的数据的存储状态，即判断各映射项的物理地址段中存储的数据是否均以未压缩的形式存储在内存芯片中，是则执行步骤325，否则执行步骤330；Step 320, the memory scheduler judges the storage state of the data stored in the physical address segment of each mapping item according to the content of the mapping item, that is, judges whether the data stored in the physical address segment of each mapping item is stored in an uncompressed form In the memory chip, if yes, execute step 325, otherwise execute step 330;
步骤325、根据各映射项的物理地址段，以及待读数据的实际地址的起始地址和数据长度，从内存芯片中读取该待读数据并存入内存调度器，执行步骤345；Step 325, according to the physical address segment of each mapping item, and the start address and data length of the actual address of the data to be read, read the data to be read from the memory chip and store it in the memory scheduler, and execute step 345;
步骤330、内存调度器判断待读数据是否正好是映射表中的一个映射项的物理地址段中存储的数据，是则执行步骤355，否则执行步骤335；Step 330, the memory scheduler judges whether the data to be read is just the data stored in the physical address segment of a mapping item in the mapping table, if so, execute step 355, otherwise execute step 335;
步骤335、内存调度器在映射表中标出与读请求相关的各映射项，并从内存芯片中读取各映射项的物理地址段中存储的数据，也称映射项数据，并存入内存调度器；Step 335, the memory scheduler marks each mapping item related to the read request in the mapping table, and reads the data stored in the physical address segment of each mapping item from the memory chip, also called mapping item data, and stores it in the memory scheduling device;
步骤340、内存调度器对每一映射项数据进行解压缩处理，并根据待读数据的实际地址的起始地址以及数据长度，获得待读数据；Step 340, the memory scheduler decompresses the data of each mapping item, and obtains the data to be read according to the starting address and the data length of the actual address of the data to be read;
步骤345、根据读请求消息包中携带的读请求的优先级，判断读请求是否要求尽快返回数据，是则执行步骤350，否则执行步骤360；Step 345, according to the priority of the read request carried in the read request message packet, judge whether the read request requires returning data as soon as possible, if yes, execute step 350, otherwise execute step 360;
步骤350、内存调度器将从内存芯片中读取的数据构造成消息包，返回给内存控制器，执行步骤370；Step 350, the memory scheduler constructs the data read from the memory chip into a message packet, returns it to the memory controller, and executes step 370;
步骤355、内存调度器从内存芯片中读取该一个映射项的物理地址段中存储的数据，构造成消息包返回给内存控制器，执行步骤365；Step 355, the memory scheduler reads the data stored in the physical address segment of the mapping item from the memory chip, constructs a message packet and returns it to the memory controller, and executes step 365;
步骤360、内存调度器将从内存芯片读取的数据压缩，构造成消息包返回给内存控制器；Step 360, the memory scheduler compresses the data read from the memory chip, constructs a message packet and returns it to the memory controller;
步骤365，内存控制器接收到消息包后，将消息包中的数据解压缩，并将解压缩后的数据发送至处理器，结束；Step 365, after receiving the message packet, the memory controller decompresses the data in the message packet, and sends the decompressed data to the processor, and ends;
步骤370，内存控制器将消息包中的数据返回给处理器，结束。Step 370, the memory controller returns the data in the message packet to the processor, and the process ends.
本实施例中，内存调度器中的内存映射关系表的各映射项的内容包括与实际地址对应的物理地址段、物理地址段在内存芯片中存储的数据的压缩信息等。In this embodiment, the content of each mapping item in the memory mapping relationship table in the memory scheduler includes the physical address segment corresponding to the actual address, the compression information of the data stored in the memory chip in the physical address segment, and the like.
本实施例中，上述步骤330和步骤355是仅对非压缩数据，且待读数据与映射项的物理地址段存储的数据一致才直接从内存芯片中直接读取作为待读数据，实际应用中，即使为压缩数据时，同样可以做此处理，详细可见图2实施例说明。In this embodiment, the above steps 330 and 355 are only for uncompressed data, and the data to be read is consistent with the data stored in the physical address segment of the mapping item, and then directly read from the memory chip as the data to be read. In practical applications , even when the data is compressed, this processing can also be done, see the description of the embodiment in FIG. 2 for details.
本实施例中，内存控制器是与处理器直接相连的内存读取控制装置，其可以接收处理器发送的读请求或写请求，并可将读请求和写请求打包成消息包的形式，以消息包的方式发送至内存调度器；同时，其也可以具有压缩和解压缩功能，可将读请求返回的经过压缩的待读数据进行解压缩后，返回至处理器，同样，也可将待写数据压缩后，携带在消息包中发送至内存调度器。In this embodiment, the memory controller is a memory reading control device directly connected to the processor, which can receive a read request or a write request sent by the processor, and can package the read request and the write request into a message packet, in the form of Message packets are sent to the memory scheduler; at the same time, it can also have compression and decompression functions, which can decompress the compressed data to be read returned by the read request and return it to the processor. Similarly, the data to be written can also be After the data is compressed, it is carried in the message packet and sent to the memory scheduler.
图4为本发明实施例四提供的压缩内存访问控制方法的流程示意图。与上述图1-图3所示实施例不同的是，本实施例中，内存调度器可对内存控制器发送的写请求消息进行处理，具体地，如图4所示，本实施例压缩内存访问控制方法可包括：FIG. 4 is a schematic flowchart of a compressed memory access control method provided by Embodiment 4 of the present invention. The difference from the above-mentioned embodiments shown in FIGS. 1-3 is that in this embodiment, the memory scheduler can process the write request message sent by the memory controller. Specifically, as shown in FIG. 4 , this embodiment compresses the memory Access control methods may include:
步骤401、接收内存控制器发送的写请求消息，该写请求消息包括待写数据的实际地址；Step 401, receiving a write request message sent by the memory controller, the write request message including the actual address of the data to be written;
步骤402、根据待写数据的实际地址，从内存映射关系表中查询得到实际地址对应的物理地址段，该内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；Step 402, according to the actual address of the data to be written, query the physical address segment corresponding to the actual address from the memory mapping relationship table, and the corresponding relationship between the actual address and the physical address segment of the memory chip is recorded in the memory mapping relationship table;
步骤403、从内存芯片中读取物理地址段存储的原始数据，并将待写数据与原始数据合成，得到合成数据；Step 403, read the original data stored in the physical address segment from the memory chip, and synthesize the data to be written with the original data to obtain the synthesized data;
步骤404、将合成数据写入内存芯片。Step 404, writing the synthesized data into the memory chip.
本实施例中，内存控制器发送的写请求消息，是对处理器（CPU）发出的写请求以消息包的形式发送至内存控制系统中的内存调度器，内存调度器在接收到该写请求消息后，只需要获取与该实际地址对应的物理地址段，并与物理地址段中的原始数据进行合成后，即可完成数据的写请求处理。In this embodiment, the write request message sent by the memory controller is to send the write request sent by the processor (CPU) to the memory scheduler in the memory control system in the form of a message packet, and the memory scheduler receives the write request After receiving the message, it is only necessary to obtain the physical address segment corresponding to the actual address, and after synthesizing it with the original data in the physical address segment, the data write request processing can be completed.
图5为本发明实施例五提供的压缩内存访问控制方法的流程示意图。本实施例中，内存调度器中的记录的内存映射关系表可包括多个映射项，每个映射项记录有实际地址及其对应的内存芯片的物理地址段，每个映射项中的内存芯片的物理地址段对应于内存芯片中的一段存储数据，这样，内存访问控制器请求的待写数据较长时，可从多个物理地址段中获取其所请求的数据，从而可满足各种数据长度的写请求处理中，具体地，如图5所示，本实施例压缩内存访问控制方法可包括：；FIG. 5 is a schematic flowchart of a compressed memory access control method provided in Embodiment 5 of the present invention. In this embodiment, the memory mapping relationship table recorded in the memory scheduler may include a plurality of mapping items, each mapping item records the actual address and the physical address segment of the corresponding memory chip, and the memory chip in each mapping item The physical address segment of the memory chip corresponds to a segment of stored data in the memory chip. In this way, when the data to be written requested by the memory access controller is long, the requested data can be obtained from multiple physical address segments, thereby satisfying various data requirements. In the processing of the write request of length, specifically, as shown in FIG. 5 , the compressed memory access control method of this embodiment may include:
步骤501、接收内存控制器发送的写请求消息，该写请求消息包括待写数据的实际地址；Step 501, receiving a write request message sent by the memory controller, the write request message including the actual address of the data to be written;
步骤502、根据待写数据的实际地址，从内存映射关系表中查询记录有该实际地址中的任一地址段的各映射项；Step 502, according to the actual address of the data to be written, query from the memory mapping relationship table for each mapping item recorded with any address segment in the actual address;
步骤503、将各映射项中记录的内存芯片的物理地址段作为各分段物理地址段，并将各分段物理地址段组合起来作为实际地址对应的物理地址段；Step 503, using the physical address segment of the memory chip recorded in each mapping item as each segmented physical address segment, and combining each segmented physical address segment as the physical address segment corresponding to the actual address;
步骤504、从内存芯片读取各分段物理地址段存储的各分段数据；Step 504, reading each segmented data stored in each segmented physical address segment from the memory chip;
步骤505、将各分段数据中为压缩数据的分段数据进行解压缩，并将解压缩后的各分段数据进行组合得到组合数据；Step 505, decompressing the segmented data that is compressed data among the segmented data, and combining the decompressed segmented data to obtain combined data;
步骤506、将组合数据与待写数据合成得到合成数据；Step 506, combining the combined data and the data to be written to obtain synthesized data;
步骤507、将合成数据写入内存芯片。Step 507, write the synthesized data into the memory chip.
本实施例中，写请求消息中还可包括待写数据的压缩信息，上述步骤506中，将组合数据与待写数据合成得到合成数据具体可包括：In this embodiment, the write request message may also include compression information of the data to be written. In the above step 506, combining the combined data and the data to be written to obtain the synthesized data may specifically include:
步骤5061、根据待请求信息中待写数据的压缩信息，判定待写数据是否为压缩数据；Step 5061, according to the compression information of the data to be written in the information to be requested, determine whether the data to be written is compressed data;
步骤5062、在待写数据为压缩数据时，对待写数据进行解压缩；Step 5062, when the data to be written is compressed data, decompress the data to be written;
步骤5063、将组合数据与解压缩后的待写数据合成得到合成数据。Step 5063: Synthesize the combination data and the decompressed data to be written to obtain composite data.
本实施例中，在上述步骤502和步骤503，根据待写数据的实际地址，从内存映射关系表中查询得到实际地址对应的物理地址段之前还可包括：判断内存映射表中是否记录有待写数据的实际地址，以便在判断内存映射表中记录有实际地址时，从内存映射表中查询得到实际地址对应的物理地址段。In this embodiment, in the above step 502 and step 503, according to the actual address of the data to be written, before the physical address segment corresponding to the actual address is obtained from the memory mapping table, it may also include: judging whether there is a record to be written in the memory mapping table The actual address of the data, so that when it is judged that the actual address is recorded in the memory mapping table, the physical address segment corresponding to the actual address can be obtained from the memory mapping table.
本实施例中，在内存映射表中未记录有所述实际地址时，可从内存芯片中为待请求数据分配一存储空间，以将待请求数据存储在该存储空间对应的物理地址段；同时，在内存映射关系表中记录待请求数据的实际地址与存储空间的物理地址段之间的对应关系。In this embodiment, when the actual address is not recorded in the memory mapping table, a storage space can be allocated for the data to be requested from the memory chip, so that the data to be requested is stored in the corresponding physical address segment of the storage space; at the same time , recording the corresponding relationship between the actual address of the data to be requested and the physical address segment of the storage space in the memory mapping relationship table.
本实施例中，将合成数据写入所述内存芯片具体可包括：在内存芯片中为合成数据分配一存储空间；将合成数据存储在该一存储空间，并在内存映射关系表中记录合成数据的实际地址与存储空间的物理地址段之间的映射关系。In this embodiment, writing the synthesized data into the memory chip may specifically include: allocating a storage space for the synthesized data in the memory chip; storing the synthesized data in the storage space, and recording the synthesized data in the memory mapping table The mapping relationship between the actual address and the physical address segment of the storage space.
图6为本发明实施例六提供的压缩内存访问控制方法的流程示意图。本实施例以压缩内存的写请求处理过程中，内存控制器与内存调度器的交互对压缩内存的访问控制进行说明，具体地，如图6所示，本实施例方法可包括如下步骤：FIG. 6 is a schematic flowchart of a compressed memory access control method provided in Embodiment 6 of the present invention. In this embodiment, the interaction between the memory controller and the memory scheduler in the process of processing the write request of the compressed memory is used to illustrate the access control of the compressed memory. Specifically, as shown in FIG. 6, the method of this embodiment may include the following steps:
步骤605、内存控制器接收处理器发出的写请求；Step 605, the memory controller receives the write request sent by the processor;
步骤610、内存控制器判断该写请求是否要求压缩写待写数据，是则执行步骤615，否则执行步骤620；Step 610, the memory controller judges whether the write request requires compression to write the data to be written, if yes, execute step 615, otherwise execute step 620;
步骤615、内存控制器压缩处理器发送的写请求的待写数据；Step 615, the memory controller compresses the data to be written in the write request sent by the processor;
步骤620、内存控制器根据写请求的待写数据的实际地址的起始地址、数据长度等参数构造得到写请求消息包，发送至内存调度器；Step 620, the memory controller constructs a write request message packet according to parameters such as the start address and data length of the actual address of the data to be written in the write request, and sends it to the memory scheduler;
步骤625、内存调度器接收到写请求消息包后，根据待写数据的实际地址的起始地址以及数据长度，在内存映射关系表中查询该写请求相关的各映射项；Step 625: After receiving the write request message packet, the memory scheduler queries the memory mapping table for each mapping item related to the write request according to the start address of the actual address of the data to be written and the data length;
步骤630、判断内存映射关系表中是否存在该写请求的相关映射项，是则执行步骤635，否则执行步骤640；Step 630, judging whether there is a relevant mapping item of the write request in the memory mapping relationship table, if yes, execute step 635, otherwise execute step 640;
步骤635、内存调度器在内存芯片上查找得到一段空闲存储空间，分配给待写数据，执行步骤660；Step 635, the memory scheduler finds a section of free storage space on the memory chip, allocates it to the data to be written, and executes step 660;
步骤640、内存调度器从内存芯片中读出与待写请求相关的各映射项的物理地址段中存储的原始数据，并将以压缩形式存储的数据解压缩；Step 640, the memory scheduler reads the original data stored in the physical address segment of each mapping item related to the request to be written from the memory chip, and decompresses the data stored in compressed form;
步骤645、判断待写数据是否已压缩，是则执行步骤650，否则执行步骤655；Step 645, judging whether the data to be written has been compressed, if yes, execute step 650, otherwise execute step 655;
步骤650、将待写数据进行解压缩处理；Step 650, decompressing the data to be written;
步骤655、内存调度器将待写数据与内存芯片中读取的各映射项的物理地址段中存储的数据合并，得到合成数据，执行步骤635；Step 655, the memory scheduler merges the data to be written with the data stored in the physical address segment of each mapping item read in the memory chip to obtain synthesized data, and executes step 635;
步骤660、内存调度器判断此时内存芯片上是否还有足够的空间存储压缩的数据，且实际剩余空间与可见剩余空间的比例小于一门槛值，是则执行步骤665，否则执行步骤670；Step 660, the memory scheduler determines whether there is enough space on the memory chip to store the compressed data at this time, and the ratio of the actual remaining space to the visible remaining space is less than a threshold value, if so, execute step 665, otherwise execute step 670;
步骤665、内存调度器将待写数据进行压缩；Step 665, the memory scheduler compresses the data to be written;
步骤670、内存调度器将待写数据写入内存芯片，并在内存映射关系表记录待写数据的实际地址与物理地址之间的对应关系，以及待写数据是否压缩的信息，结束。Step 670 , the memory scheduler writes the data to be written into the memory chip, and records the correspondence between the actual address and the physical address of the data to be written in the memory mapping table, as well as information about whether the data to be written is compressed, and ends.
上述步骤660中，所述的实际剩余空间就是指内存芯片的物理地址的大小，而可见剩余空间则是指待存储的数据的实际地址的大小，这样，只有他们之间的比例小于一定门槛值时，才可进行数据压缩，以压缩数据的形式存储，否则以非压缩形式存储。In the above step 660, the actual remaining space refers to the size of the physical address of the memory chip, and the visible remaining space refers to the size of the actual address of the data to be stored. In this way, only the ratio between them is less than a certain threshold value Only when , the data can be compressed and stored in the form of compressed data, otherwise it is stored in the form of uncompressed data.
图7为本发明实施例七提供的压缩内存访问控制装置的结构示意图。如图7所示，本实施例压缩内存访问控制装置包括读请求消息接收模块11、物理地址查询模块12、待读数据获取模块13和待读数据返回模块14，其中：FIG. 7 is a schematic structural diagram of a compressed memory access control device provided by Embodiment 7 of the present invention. As shown in FIG. 7 , the compressed memory access control device of this embodiment includes a read request message receiving module 11, a physical address query module 12, a data to be read acquisition module 13 and a data to be read return module 14, wherein:
读请求消息接收模块11，用于接收内存控制器发送的读请求消息，该读请求消息包括待读数据的实际地址；Read request message receiving module 11, for receiving the read request message that memory controller sends, and this read request message comprises the actual address of data to be read;
物理地址查询模块12，用于根据待读数据的实际地址，从内存映射关系表中查询得到实际地址对应的物理地址段，该内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；The physical address inquiry module 12 is used for according to the actual address of the data to be read, and obtains the corresponding physical address segment of the actual address from the memory mapping relational table, and the physical address segment of the actual address and the memory chip is recorded in the memory mapping relational table Correspondence;
待读数据获取模块13，用于从内存芯片中读取物理地址段存储的数据，获得与实际地址对应的待读数据；The data to be read acquisition module 13 is used to read the data stored in the physical address segment from the memory chip, and obtain the data to be read corresponding to the actual address;
待读数据返回模块14，用于将待读数据返回至内存控制器。The data to be read returning module 14 is used to return the data to be read to the memory controller.
本实施例内存压缩访问控制装置可作为上述压缩内存控制系统中的内存调度器，对内存控制器发送的读请求消息进行处理，其具体实现可参见上述本发明方法实施例一-三的说明。The memory compression access control device of this embodiment can be used as the memory scheduler in the above-mentioned compressed memory control system to process the read request message sent by the memory controller. For the specific implementation, please refer to the descriptions of the above-mentioned method embodiments 1-3 of the present invention.
图8A为本发明实施例八提供的压缩内存访问控制装置的结构示意图；图8B为本发明实施例中待读数据获取模块的结构示意图。本实施例中，内存映射关系表包括多个映射项，每个映射项记录有实际地址及其对应的内存芯片的物理地址段，每个映射项中的内存芯片的物理地址段对应于内存芯片中的一段存储数据，对应的，物理地址查询模块12具体可包括映射项查询单元121和物理地址获取单元122，其中：FIG. 8A is a schematic structural diagram of a compressed memory access control device provided in Embodiment 8 of the present invention; FIG. 8B is a schematic structural diagram of a module for acquiring data to be read in an embodiment of the present invention. In this embodiment, the memory mapping relationship table includes a plurality of mapping items, and each mapping item records an actual address and the corresponding physical address segment of the memory chip, and the physical address segment of the memory chip in each mapping item corresponds to the memory chip A segment of stored data in the corresponding, the physical address query module 12 may specifically include a mapping item query unit 121 and a physical address acquisition unit 122, wherein:
映射项查询单元121，用于根据待读数据的实际地址，从内存映射关系表中查询记录有实际地址中的任一地址段的各映射项；The mapping item query unit 121 is used to query each mapping item recorded with any address segment in the actual address from the memory mapping relationship table according to the actual address of the data to be read;
物理地址获取单元122，用于将各映射项中记录的内存芯片的物理地址段作为各分段物理地址段，并将各分段物理地址段组合起来作为实际地址对应的物理地址段。The physical address acquisition unit 122 is configured to use the physical address segment of the memory chip recorded in each mapping item as each segmented physical address segment, and combine the segmented physical address segments as the physical address segment corresponding to the actual address.
进一步地，本实施例中，内存映射关系表中还可记录有内存芯片的物理地址段存储的数据的压缩信息，相应的，如图8B所示，上述的待读数据获取模块13可包括第一判断单元131、分段数据获取单元132、数据组合单元133和第一待读数据获取单元134，其中：Further, in this embodiment, the memory mapping relationship table can also record the compression information of the data stored in the physical address segment of the memory chip. Correspondingly, as shown in FIG. 8B, the above-mentioned data acquisition module 13 to be read may include the first A judgment unit 131, segmented data acquisition unit 132, data combination unit 133 and the first data acquisition unit 134 to be read, wherein:
第一判断单元131，用于判断各分段物理地址段存储的数据是否包括有压缩数据；The first judging unit 131 is used to judge whether the data stored in each segmented physical address segment includes compressed data;
分段数据获取单元132，用于在各分段物理地址段中存储的数据包括有压缩数据时，从内存芯片中读取各分段物理地址段存储的各分段数据；Segmented data acquisition unit 132, for when the data stored in each segmented physical address segment includes compressed data, read each segmented data stored in each segmented physical address segment from the memory chip;
数据组合单元133，用于将各分段数据的压缩数据解压缩，并组合起来得到组合数据；A data combination unit 133, configured to decompress the compressed data of each segmented data and combine them to obtain combined data;
第一待读数据获取单元134，用于从组合数据中得到与实际地址对应的所述待读数据。The first data to be read obtaining unit 134 is configured to obtain the data to be read corresponding to the actual address from the combined data.
本实施例中，如图8B所示，上述的待读数据获取模块13还可包括第二待读数据获取单元135，用于在各分段物理地址段中存储的数据未包括有压缩数据时，直接从内存芯片中读取实际地址对应的待读数据。In this embodiment, as shown in FIG. 8B , the above-mentioned data-to-be-read acquisition module 13 may further include a second data-to-be-read acquisition unit 135 for when the data stored in each segmented physical address segment does not include compressed data , directly read the data to be read corresponding to the actual address from the memory chip.
更进一步地，本实施例中，如图8B所示，上述的待读数据获取模块13还可包括第二判断单元136和第三待读数据获取单元137，其中：Furthermore, in this embodiment, as shown in FIG. 8B , the above-mentioned data-to-be-read acquisition module 13 may further include a second judging unit 136 and a third data-to-be-read acquisition unit 137, wherein:
第二判断单元136，用于判断待读数据是否正好是物理地址段存储的数据；The second judging unit 136 is used to judge whether the data to be read is exactly the data stored in the physical address segment;
第三待读数据获取单元137，用于判断待读数据是否正好是物理地址段存储的数据时，直接从内存芯片中读取物理地址段中的各分段物理地址段存储的数据，并将各分段物理地址段存储的数据组合起来，得到待读数据。The third data to be read acquisition unit 137 is used to judge whether the data to be read is just the data stored in the physical address segment, directly read the data stored in each segmented physical address segment in the physical address segment from the memory chip, and The data stored in the physical address segments of each segment are combined to obtain the data to be read.
本实施例中，如图8A所示，上述读请求消息接收模块11接收的读请求消息还可包括有读请求优先级，该读请求优先级为高优先级或低优先级，相应地，如图8A所示，上述的待读数据返回模块14，具体可用于在读请求的优先级为低优先级时，将待读数据以压缩包的方式返回至内存控制器。In this embodiment, as shown in FIG. 8A, the read request message received by the above-mentioned read request message receiving module 11 may also include a read request priority, and the read request priority is high priority or low priority. Correspondingly, as As shown in FIG. 8A , the above-mentioned data-to-be-read returning module 14 can specifically be used to return the data to be read to the memory controller in compressed packets when the priority of the read request is low.
本实施例可基于上述图2或图3所示压缩内存访问控制方法步骤实现对压缩内存的读请求进行处理，其具体实现可参见上述本发明方法实施例的说明。This embodiment can process the read request of the compressed memory based on the steps of the compressed memory access control method shown in FIG. 2 or FIG. 3 above. For specific implementation, refer to the above description of the method embodiment of the present invention.
图9为本发明实施例九提供的压缩内存访问控制装置的结构示意图。如图9所示，本实施例压缩内存访问控制装置包括写请求信息接收模块21、物理地址查询模块22、数据合成模块23和数据写入模块24，其中：FIG. 9 is a schematic structural diagram of an apparatus for controlling access to compressed memory provided by Embodiment 9 of the present invention. As shown in FIG. 9 , the compressed memory access control device of this embodiment includes a write request information receiving module 21, a physical address query module 22, a data synthesis module 23 and a data writing module 24, wherein:
写请求信息接收模块21，用于接收内存控制器发送的写请求消息，该写请求消息包括待写数据的实际地址；A write request information receiving module 21, configured to receive a write request message sent by the memory controller, the write request message including the actual address of the data to be written;
物理地址查询模块22，用于根据待写数据的实际地址，从内存映射关系表中查询得到实际地址对应的物理地址段，该内存映射关系表中记录有实际地址与内存芯片的物理地址段的对应关系；The physical address query module 22 is used to query the physical address segment corresponding to the actual address from the memory mapping relationship table according to the actual address of the data to be written, and the memory mapping relationship table records the relationship between the actual address and the physical address segment of the memory chip Correspondence;
数据合成模块23，用于从内存芯片中读取物理地址段存储的原始数据，并将待写数据与所述原始数据合成，得到合成数据；The data synthesis module 23 is used to read the original data stored in the physical address segment from the memory chip, and synthesize the data to be written with the original data to obtain the synthesized data;
数据写入模块24，用于将合成数据写入内存芯片。The data writing module 24 is used for writing the synthesized data into the memory chip.
本实施例内存压缩访问控制装置可作为上述压缩内存控制系统中的内存调度器，对内存控制器发送的写请求消息进行处理，其具体实现可参见上述本发明方法实施例四-六的说明。The memory compression access control device of this embodiment can be used as the memory scheduler in the above-mentioned compressed memory control system to process the write request message sent by the memory controller. For the specific implementation, please refer to the above descriptions of the method embodiments 4-6 of the present invention.
图10A为本发明实施例十提供的压缩内存访问控制装置的结构示意图；图10B为本发明实施例中数据合成模块的结构示意图。本实施例中，内存映射关系表包括多个映射项，每个映射项记录有实际地址及其对应的内存芯片的物理地址段，每个映射项中的内存芯片的物理地址段对应于内存芯片中的一段存储数据，相应地，如图10A所示，上述的物理地址查询模块22具体可包括映射项查询单元221和物理地址获取单元222，其中：FIG. 10A is a schematic structural diagram of a compressed memory access control device provided in Embodiment 10 of the present invention; FIG. 10B is a schematic structural diagram of a data synthesis module in an embodiment of the present invention. In this embodiment, the memory mapping relationship table includes a plurality of mapping items, and each mapping item records an actual address and the corresponding physical address segment of the memory chip, and the physical address segment of the memory chip in each mapping item corresponds to the memory chip Correspondingly, as shown in FIG. 10A, the above-mentioned physical address query module 22 may specifically include a mapping item query unit 221 and a physical address acquisition unit 222, wherein:
映射项查询单元221，用于根据待读数据的实际地址，从内存映射关系表中查询记录有实际地址中的任一地址段的各映射项；The mapping item query unit 221 is used for querying each mapping item recorded with any address segment in the actual address from the memory mapping relationship table according to the actual address of the data to be read;
物理地址获取单元222，用于将各映射项中记录的内存芯片的物理地址段作为各分段物理地址段，并将各分段物理地址段组合起来作为实际地址对应的物理地址段。The physical address acquisition unit 222 is configured to use the physical address segment of the memory chip recorded in each mapping item as each segmented physical address segment, and combine the segmented physical address segments as the physical address segment corresponding to the actual address.
进一步地，上述的内存映射关系表中还可记录有内存芯片的物理地址段存储的数据的压缩信息，相应地，如图10B所示，上述的数据合成模块23具体可包括分段数据获取单元231、数据组合单元232和数据合成单元233，其中：Further, the above-mentioned memory mapping relationship table can also record the compression information of the data stored in the physical address segment of the memory chip. Correspondingly, as shown in FIG. 10B , the above-mentioned data synthesis module 23 can specifically include a segmented data acquisition unit 231, data combination unit 232 and data synthesis unit 233, wherein:
分段数据获取单元231，用于从内存芯片读取各分段物理地址段存储的各分段数据；Segmented data acquisition unit 231, used to read each segmented data stored in each segmented physical address segment from the memory chip;
数据组合单元232，用于将各分段数据中为压缩数据的分段数据进行解压缩，并将解压缩后的各分段数据进行组合得到组合数据；A data combination unit 232, configured to decompress the segmented data that is compressed data in each segmented data, and combine the decompressed segmented data to obtain combined data;
数据合成单元233，用于将组合数据与待写数据合成得到合成数据。The data combining unit 233 is configured to combine the combined data and the data to be written to obtain combined data.
进一步地，上述写请求信息接收模块21接收到的写请求消息中还可包括所述待写数据的压缩信息，相应地，如图10B所示，上述的数据合成单元233可包括判定子单元2331、解压缩子单元2332和数据合成子单元2333，其中：Further, the write request message received by the above write request information receiving module 21 may also include the compression information of the data to be written. Correspondingly, as shown in FIG. 10B , the above data synthesis unit 233 may include a determination subunit 2331 , decompression subunit 2332 and data synthesis subunit 2333, wherein:
判定子单元2331，用于根据待请求信息中待写数据的压缩信息，判定待写数据是否为压缩数据；The determination subunit 2331 is used to determine whether the data to be written is compressed data according to the compression information of the data to be written in the information to be requested;
解压缩子单元2332，用于在待写数据为压缩数据时，对待写数据进行解压缩；The decompression subunit 2332 is used to decompress the data to be written when the data to be written is compressed data;
数据合成子单元2333，用于将组合数据与解压缩后的待写数据合成得到合成数据。The data synthesizing subunit 2333 is used to synthesize the combined data and the decompressed data to be written to obtain the synthesized data.
此外，如图10A所示，本实施例压缩内存访问控制装置还可包括：判断模块25，用于判断内存映射表中是否记录有待写数据的实际地址，以便在判断内存映射表中记录有实际地址时，物理地址查询模块22从内存映射表中查询得到实际地址对应的物理地址段。In addition, as shown in FIG. 10A , the device for controlling access to compressed memory in this embodiment may further include: a judging module 25 for judging whether the actual address of the data to be written is recorded in the memory mapping table, so that the actual address of the data to be written is recorded in the judging memory mapping table. address, the physical address query module 22 queries the memory mapping table to obtain the physical address segment corresponding to the actual address.
进一步地，如图10A所示，本实施例压缩内存访问控制装置还可包括存储空间分配模块26、存储模块27和映射关系记录模块28，其中：Further, as shown in FIG. 10A, the compressed memory access control device of this embodiment may also include a storage space allocation module 26, a storage module 27, and a mapping relationship recording module 28, wherein:
存储空间分配模块26，用于在内存映射表中未记录有实际地址时，从内存芯片中为待请求数据分配一存储空间；The storage space allocation module 26 is configured to allocate a storage space from the memory chip for data to be requested when no actual address is recorded in the memory mapping table;
存储模块27，用于将待请求数据存储在存储空间对应的物理地址段；The storage module 27 is used to store the data to be requested in the physical address segment corresponding to the storage space;
映射关系记录模块28，用于在内存映射关系表中记录待请求数据的实际地址与存储空间的物理地址段之间的对应关系。The mapping relationship recording module 28 is configured to record the corresponding relationship between the actual address of the data to be requested and the physical address segment of the storage space in the memory mapping relationship table.
本实施例中，如图10A所示，上述的数据写入模块24可包括第一存储空间分配单元241和第一映射关系记录单元242，其中：In this embodiment, as shown in FIG. 10A, the above-mentioned data writing module 24 may include a first storage space allocation unit 241 and a first mapping relationship recording unit 242, wherein:
第一存储空间分配单元241，用于在内存芯片中为合成数据分配一存储空间；The first storage space allocation unit 241 is used to allocate a storage space for the synthesized data in the memory chip;
第一映射关系记录单元242，用于将合成数据存储在一存储空间，并在内存映射关系表中记录合成数据的实际地址与存储空间的物理地址段之间的映射关系。The first mapping relationship recording unit 242 is configured to store the synthesized data in a storage space, and record the mapping relationship between the actual address of the synthesized data and the physical address segment of the storage space in the memory mapping relationship table.
本实施例可基于图5或图6所示的压缩内存访问控制方法对内存控制器发送的写请求进行处理，具体实现可参见上述本发明方法实施例的说明。This embodiment can process the write request sent by the memory controller based on the compressed memory access control method shown in FIG. 5 or FIG. 6 . For specific implementation, refer to the above description of the method embodiment of the present invention.
图11为本发明实施例十一提供的压缩内存访问控制系统的结构示意图。如图11所示，本实施例压缩内存访问控制系统包括内存调度器10和内存芯片20，该内存调度器可包括图7-图11任一所示的压缩内存控制装置，或者，也可同时包括图7或图8A所示的装置，以及图9或图10A所示的装置。FIG. 11 is a schematic structural diagram of a compressed memory access control system provided by Embodiment 11 of the present invention. As shown in Figure 11, the compressed memory access control system of this embodiment includes a memory scheduler 10 and a memory chip 20, and the memory scheduler may include the compressed memory control device shown in any one of Figures 7-11, or may also be simultaneously Including the device shown in FIG. 7 or 8A, and the device shown in FIG. 9 or 10A.
本实施例中，如图11所示，压缩内存系统可与多核处理器30连接，用于对多核处理器30发送的读请求或写请求进行处理，其中，多核处理器30包括处理器301、命令总线302和内存控制器303，内存控制器303与内存调度器10之间通过消息通道40连接，内存调度器10和内存芯片20构成内存模块，其中，处理器301与内存控制器303之间，以及内存控制器303与内存调度器10之间均是通过消息包形式传输指令或数据。In this embodiment, as shown in FIG. 11 , the compressed memory system can be connected to a multi-core processor 30 for processing a read request or a write request sent by the multi-core processor 30, wherein the multi-core processor 30 includes a processor 301, The command bus 302 and the memory controller 303, the memory controller 303 and the memory scheduler 10 are connected through the message channel 40, the memory scheduler 10 and the memory chip 20 constitute a memory module, wherein, between the processor 301 and the memory controller 303 , and between the memory controller 303 and the memory scheduler 10, instructions or data are transmitted in the form of message packets.
本实施例中，上述的内存控制器303以及内存调度器10均可发送和接收消息包，并可具有压缩解压缩功能，即可对传输的数据进行压缩或解压缩处理。In this embodiment, the above-mentioned memory controller 303 and memory scheduler 10 can both send and receive message packets, and can have compression and decompression functions, that is, compress or decompress the transmitted data.
本实施例中，上述的内存控制器303以及内存调度器10之间采用消息包进行信息传输，支持可变粒度的数据压缩，提高压缩数据的灵活性。同时，由于消息包中可携带数据的压缩信息，方便内存控制器和内存调度器两端的配合。In this embodiment, the above-mentioned memory controller 303 and the memory scheduler 10 use message packets for information transmission, support variable granularity data compression, and improve the flexibility of compressed data. At the same time, since the compressed information of the data can be carried in the message packet, it is convenient for the cooperation between the two ends of the memory controller and the memory scheduler.
本实施例中，上述的内存控制器303以及内存调度器10在压缩数据时，可根据需要调整数据压缩解压缩比例，以提高内存资源的利用率。In this embodiment, when the above-mentioned memory controller 303 and memory scheduler 10 compress data, they can adjust the ratio of data compression and decompression according to needs, so as to improve the utilization rate of memory resources.
本实施例中，由于内存访问是基于消息包形式进行数据传输，因此，可支持可变延迟访存，实现压缩解压缩内存数据的透明，不管是访问内存芯片中的压缩数据还是未压缩的数据，只需要统一的访存指令即可。In this embodiment, since the memory access is based on data transmission in the form of message packets, it can support variable delay memory access and realize the transparency of compression and decompression of memory data, no matter whether it is accessing compressed data in the memory chip or uncompressed data , only a unified memory access instruction is required.
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the It includes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.
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