CN103854587A - Gate driving circuit, gate driving circuit unit and displayer - Google Patents

Abstract

Translated fromChinese

本申请公开了一种栅极驱动电路单元，以现有的栅极驱动电路单元为电路结构框架，包括驱动模块、低电平维持模块、第一输入模块和第二输入模块。通过对第一输入模块和第二输入模块的开关晶体管进行改进，额外增加晶体管及外接控制信号，从而实现了栅极驱动电路单元多扫描模式的切换，并且栅极驱动电路单元在不同的工作状态过程中，根据电路逻辑和公用的要求，最大程度地复用各电路模块，从而提高模块利用效率、节约硬件开销。基于上述的栅极驱动电路单元，本申请还公开了一种栅极驱动电路和一种显示器。

The present application discloses a gate drive circuit unit, which uses the existing gate drive circuit unit as a circuit structure frame, and includes a drive module, a low level maintenance module, a first input module and a second input module. By improving the switching transistors of the first input module and the second input module, additional transistors and external control signals are added, so that the switching of the multi-scanning mode of the gate drive circuit unit is realized, and the gate drive circuit unit is in different working states In the process, according to the circuit logic and public requirements, each circuit module is reused to the greatest extent, thereby improving the utilization efficiency of the module and saving hardware overhead. Based on the above gate drive circuit unit, the present application also discloses a gate drive circuit and a display.

Description

Translated fromChinese

栅极驱动电路及其单元和一种显示器Gate driving circuit and its unit and a display

技术领域technical field

本申请涉及电子领域，具体涉及一种显示器及其栅极驱动电路和栅极驱动单元电路。The present application relates to the field of electronics, in particular to a display and its gate drive circuit and gate drive unit circuit.

背景技术Background technique

薄膜晶体管（Thin Film Transistor,TFT）面板显示（Flat Panel Display，FPD）是当今显示技术的主流。近年来，采用TFT集成的栅极驱动电路设计(gate driverin array,GIA)开始被广泛地用于中小尺寸显示面板，甚至大尺寸显示面板中。通过合理的电路设计，即使采用a-Si TFT也可能得到性能良好的GIA电路，在电路响应速度、稳定性、功耗等方面满足显示应用的需求。集成了栅极驱动电路的显示面板具有窄边框、高分辨率、价格低廉等优势。Thin Film Transistor (TFT) panel display (Flat Panel Display, FPD) is the mainstream of display technology today. In recent years, the gate driver circuit design (gate driver in array, GIA) using TFT integration has begun to be widely used in small and medium-sized display panels, and even large-sized display panels. Through reasonable circuit design, even if a-Si TFT is used, it is possible to obtain a GIA circuit with good performance, which can meet the needs of display applications in terms of circuit response speed, stability, and power consumption. The display panel integrated with the gate driving circuit has the advantages of narrow frame, high resolution, and low price.

氧化物晶体管（IGZO TFT）具有高的迁移率，更好的稳定性而更适合于高分辨率、大面积的显示器应用，因此，IGZO TFT更有可能成为未来的主流TFT技术。基于IGZO TFT的新型高性能GIA电路的研制引起了研究者的极大关注。IGZO TFT由于迁移率高等优势能够大幅度地提高电路的性能。在a-Si或者有机TFT等场合，由于迁移率过低，许多电路技术的应用受到局限，例如反馈电路单元等因为速度过慢而无法体现应有的效用。而IGZO TFT的引入则可能以柔性或者透明显示面板为平台让更丰富的电路技术得以实施，使得显示面板系统(System on Paenl,SoP)更为智能。Oxide transistor (IGZO TFT) has high mobility, better stability and is more suitable for high-resolution, large-area display applications. Therefore, IGZO TFT is more likely to become the mainstream TFT technology in the future. The development of new high-performance GIA circuits based on IGZO TFT has attracted great attention of researchers. Due to the advantages of high mobility and other advantages, IGZO TFT can greatly improve the performance of the circuit. In the case of a-Si or organic TFT, due to the low mobility, the application of many circuit technologies is limited. For example, the feedback circuit unit cannot reflect the due effect because the speed is too slow. The introduction of IGZO TFT may use flexible or transparent display panels as a platform to implement richer circuit technologies, making the display panel system (System on Paenl, SoP) more intelligent.

近年来，具备多扫描模式特征的集成栅极驱动电路设计引起了TFT FPD产业界的关注。以双向扫描模式为例，在外围时钟信号配合下，栅极驱动电路不仅能够顺次地从小序号数的栅极线依次扫描到大序号数的栅极线，而且能够从大序号数的栅极线扫描到小序号数的栅极线。增加了双向扫描特征之后，TFTFPD获得如下好处：（1）当FPD在正向、反向扫描模式之间进行切换时，可以在垂直于栅线方向实现显示图像的镜像。这增强了FPD的操作性、趣味性和使用者的好感度。（2）显示面板的配置更加灵活，更方便地满足不同设计者的需求。In recent years, the design of integrated gate drive circuits with multi-scan mode features has attracted the attention of the TFT FPD industry. Taking the bidirectional scanning mode as an example, with the cooperation of the peripheral clock signal, the gate drive circuit can not only sequentially scan the gate lines with the small serial number to the gate lines with the large serial number, but also can scan from the gate line with the large serial number. Line scan to the gate line with a small sequence number. After adding the bidirectional scanning feature, TFTFPD obtains the following benefits: (1) When the FPD is switched between the forward and reverse scanning modes, the mirror image of the displayed image can be realized in the direction perpendicular to the grid lines. This enhances the operability, fun and user's favorability of the FPD. (2) The configuration of the display panel is more flexible, and it is more convenient to meet the needs of different designers.

现有技术中，实现双向集成栅极驱动电路一般有两种方法：一为设计两套扫描电路，分别用于实现正向、反向扫描；二为增加控制扫描方向的电信号。采用这两种方法来实现栅极驱动电路的效果均不理想。这是因为，第一种方法需采用复杂的电路结构，用到的TFT数量几乎为单向扫描栅极驱动电路中TFT数量的两倍。在任意工作时段，第一种栅极驱动电路中，几乎总是有一半的器件处于闲置状态。上述第二种方法能够减少TFT的数量，但是控制信号的数量却增加了，而且这些新增加的控制信号会增加栅极驱动电路中TFT的电压偏置时间，缩短了栅极驱动电路的使用寿命。In the prior art, there are generally two ways to implement a bidirectional integrated gate drive circuit: one is to design two sets of scanning circuits for forward and reverse scanning respectively; the other is to add electrical signals to control the scanning direction. The effect of using these two methods to realize the gate driving circuit is not ideal. This is because the first method needs to adopt a complicated circuit structure, and the number of TFTs used is almost twice the number of TFTs in the unidirectional scanning gate driving circuit. During any period of operation, half of the devices in the first type of gate drive circuit are almost always idle. The second method above can reduce the number of TFTs, but the number of control signals increases, and these newly added control signals will increase the voltage bias time of TFTs in the gate drive circuit, shortening the service life of the gate drive circuit .

综上所述，IGZO TFT更适于设计多模式的GIA电路。例如，IGZO TFT的泄露电流较小，在显示静态图像时候的，TFT面板阵列的刷新频率可以减小，这不仅可以减少TFT面板的功耗、延长移动TFT面板的电池续航时间，而且对于减少使用者的眼睛疲劳具有优势。于是IGZO TFT的GIA设计提出了新的要求：其一，要求IGZO TFT的GIA电路具有多种扫描模式；其二，既能够输出较高频率的扫描脉冲显示动态图像，又能够以较小的刷新频率来显示静态图像。但是，常规的GIA设计并不支持多扫描模式的功能。因此，需要研究新的IGZOTFT的GIA方案，使得其具有多扫描模式功能，而且电路结构较简单、外围连接线数量较少。In summary, IGZO TFT is more suitable for designing multi-mode GIA circuits. For example, the leakage current of IGZO TFT is small, and the refresh frequency of the TFT panel array can be reduced when displaying static images, which can not only reduce the power consumption of the TFT panel, prolong the battery life of the mobile TFT panel, but also reduce the use of Those with eyestrain have an advantage. Therefore, the GIA design of IGZO TFT puts forward new requirements: first, the GIA circuit of IGZO TFT is required to have multiple scanning modes; frequency to display static images. However, conventional GIA designs do not support the multi-scan mode functionality. Therefore, it is necessary to study the new GIA scheme of IGZOTFT, so that it has multi-scan mode function, and the circuit structure is relatively simple, and the number of peripheral connection lines is small.

发明内容Contents of the invention

本申请提供一种栅极驱动电路及其单元和一种显示器。The present application provides a gate driving circuit and its unit and a display.

根据本申请的第一方面，本申请提供一种栅极驱动电路单元，包括：According to the first aspect of the present application, the present application provides a gate drive circuit unit, including:

第一信号输入端，用于输入第一脉冲信号。The first signal input end is used for inputting the first pulse signal.

第二信号输入端，用于输入第二脉冲信号。The second signal input terminal is used for inputting the second pulse signal.

第一时钟信号输入端，用于输入第一时钟信号。The first clock signal input end is used for inputting the first clock signal.

信号输出端，用于输出脉冲驱动信号。The signal output terminal is used to output the pulse driving signal.

驱动模块，驱动模块耦合在第一时钟信号输入端和信号输出端之间，在其驱动控制端获得驱动电压后，将第一时钟信号传送到信号输出端，当第一时钟信号为高电平时，驱动模块对信号输出端上拉充电；当第一时钟信号为低电平时，驱动模块对信号输出端下拉放电。A drive module, the drive module is coupled between the first clock signal input terminal and the signal output terminal, and after the drive control terminal obtains the driving voltage, the first clock signal is transmitted to the signal output terminal, when the first clock signal is at a high level , the driving module pulls up and charges the signal output terminal; when the first clock signal is at a low level, the driving module pulls down and discharges the signal output terminal.

低电平维持模块，低电平维持模块耦合在信号输出端和低电平端之间；低电平维持模块响应第一时钟信号的高电平信号或第三时钟信号的高电平信号将信号输出端耦合至低电平端，维持信号输出端低电平电位。A low-level maintenance module, the low-level maintenance module is coupled between the signal output terminal and the low-level terminal; the low-level maintenance module responds to the high-level signal of the first clock signal or the high-level signal of the third clock signal. The output terminal is coupled to the low-level terminal to maintain the low-level potential of the signal output terminal.

第二输入模块，第二输入模块包括级联的至少一个第二开关晶体管，级联的至少一个第二开关晶体管耦合在第二信号输入端和驱动控制端之间，首级第二开关晶体管的第一极用于输入第二时钟信号，尾级第二开关晶体管的第二极耦合在驱动控制端，各第二开关晶体管的控制极耦合在第二信号输入端，用于输入第二脉冲信号；在反向扫描模式下，第二输入模块响应第二脉冲信号和第二时钟信号的高电平交叠期信号对驱动控制端充电；在正向扫描模式下，第二脉冲信号和第二时钟信号分别为高电平和低电平时，第二输入模块对驱动控制端放电。The second input module, the second input module includes at least one second switch transistor in cascade connection, the at least one second switch transistor in cascade connection is coupled between the second signal input terminal and the drive control terminal, and the first stage of the second switch transistor The first pole is used to input the second clock signal, the second pole of the second switching transistor in the tail stage is coupled to the drive control terminal, and the control poles of each second switching transistor are coupled to the second signal input terminal for inputting the second pulse signal ; In the reverse scan mode, the second input module charges the drive control terminal in response to the high-level overlap period signal of the second pulse signal and the second clock signal; in the forward scan mode, the second pulse signal and the second When the clock signal is at high level and low level respectively, the second input module discharges the drive control terminal.

第一输入模块，第一输入模块包括级联的至少一个第一开关晶体管，级联的至少一个第一开关晶体管耦合在第一信号输入端和驱动控制端之间，首级第一开关晶体管的第一极用于输入第四时钟信号，尾级第一开关晶体管的第二极耦合在驱动控制端，各第一开关晶体管的控制极耦合在第一信号输入端，用于输入第一脉冲信号；在正向扫描模式下，第一输入模块响应第一脉冲信号和第四时钟信号的高电平交叠期信号对驱动控制端充电；在反向扫描模式下，第一脉冲信号和第四时钟信号分别为高电平和低电平时，第一输入模块对驱动控制端放电。The first input module, the first input module includes at least one first switch transistor in cascade connection, the at least one first switch transistor in cascade connection is coupled between the first signal input terminal and the drive control terminal, and the first switch transistor of the first stage The first pole is used to input the fourth clock signal, the second pole of the first switching transistor in the tail stage is coupled to the drive control terminal, and the control poles of each first switching transistor are coupled to the first signal input terminal for inputting the first pulse signal ; In the forward scan mode, the first input module charges the drive control terminal in response to the high-level overlap period signal of the first pulse signal and the fourth clock signal; in the reverse scan mode, the first pulse signal and the fourth clock signal When the clock signal is at high level and low level respectively, the first input module discharges the drive control terminal.

第一输入模块还包括第十五晶体管，第十五晶体管的控制极用于输入控制信号，第一极耦合至首级第一开关晶体管的第二极，第二极耦合至低电平端；第十五晶体管在控制信号高电平信号控制下将首级第一开关晶体管的第二极耦合至低电平端，在控制信号低电平信号控制下第十五晶体管断开。The first input module also includes a fifteenth transistor, the control pole of the fifteenth transistor is used for inputting a control signal, the first pole is coupled to the second pole of the first switching transistor in the first stage, and the second pole is coupled to the low level terminal; The fifteenth transistor couples the second pole of the first switch transistor of the first stage to the low-level end under the control of the high-level control signal, and the fifteenth transistor is turned off under the control of the low-level control signal.

第一时钟信号与第三时钟信号互补。The first clock signal is complementary to the third clock signal.

根据本申请的第二方面，本申请提供另一种栅极驱动电路单元，包括：According to the second aspect of the present application, the present application provides another gate drive circuit unit, including:

第一信号输入端，用于输入第一脉冲信号。The first signal input end is used for inputting the first pulse signal.

第二信号输入端，用于输入第二脉冲信号。The second signal input terminal is used for inputting the second pulse signal.

第一时钟信号输入端，用于输入第一时钟信号。The first clock signal input end is used for inputting the first clock signal.

信号输出端，用于输出脉冲驱动信号。The signal output terminal is used to output the pulse driving signal.

驱动模块，驱动模块耦合在第一时钟信号输入端和信号输出端之间，在其驱动控制端获得驱动电压后，将第一时钟信号传送到信号输出端，当第一时钟信号为高电平时，驱动模块对信号输出端上拉充电；当第一时钟信号为低电平时，驱动模块对信号输出端下拉放电。A drive module, the drive module is coupled between the first clock signal input terminal and the signal output terminal, and after the drive control terminal obtains the driving voltage, the first clock signal is transmitted to the signal output terminal, when the first clock signal is at a high level , the driving module pulls up and charges the signal output terminal; when the first clock signal is at a low level, the driving module pulls down and discharges the signal output terminal.

低电平维持模块，低电平维持模块耦合在信号输出端和低电平端之间；低电平维持模块响应第一时钟信号的高电平信号或第三时钟信号的高电平信号将信号输出端耦合至低电平端，维持信号输出端低电平电位。A low-level maintenance module, the low-level maintenance module is coupled between the signal output terminal and the low-level terminal; the low-level maintenance module responds to the high-level signal of the first clock signal or the high-level signal of the third clock signal. The output terminal is coupled to the low-level terminal to maintain the low-level potential of the signal output terminal.

第一输入模块，第一输入模块包括级联的至少一个第一开关晶体管，级联的至少一个第一开关晶体管耦合在第一信号输入端和驱动控制端之间，首级第一开关晶体管的第一极用于输入第四时钟信号，尾级第一开关晶体管的第二极耦合在驱动控制端，各第一开关晶体管的控制极耦合在第一信号输入端，用于输入第一脉冲信号；在正向扫描模式下，第一输入模块响应第一脉冲信号和第四时钟信号的高电平交叠期信号对驱动控制端充电；在反向扫描模式下，第一脉冲信号和第四时钟信号分别为高电平和低电平时，第一输入模块对驱动控制端放电。The first input module, the first input module includes at least one first switch transistor in cascade connection, the at least one first switch transistor in cascade connection is coupled between the first signal input terminal and the drive control terminal, and the first switch transistor of the first stage The first pole is used to input the fourth clock signal, the second pole of the first switching transistor in the tail stage is coupled to the drive control terminal, and the control poles of each first switching transistor are coupled to the first signal input terminal for inputting the first pulse signal ; In the forward scan mode, the first input module charges the drive control terminal in response to the high-level overlap period signal of the first pulse signal and the fourth clock signal; in the reverse scan mode, the first pulse signal and the fourth clock signal When the clock signal is at high level and low level respectively, the first input module discharges the drive control terminal.

第二输入模块，第二输入模块包括级联的至少一个第二开关晶体管，级联的至少一个第二开关晶体管耦合在第二信号输入端和驱动控制端之间，首级第二开关晶体管的第一极用于输入第二时钟信号，尾级第二开关晶体管的第二极耦合在驱动控制端各第二开关晶体管的控制极耦合在第二信号输入端，用于输入第二脉冲信号；在反向扫描模式下，第二输入模块响应第二脉冲信号和第二时钟信号的高电平交叠期信号对驱动控制端充电；在正向扫描模式下，第二脉冲信号和第二时钟信号分别为高电平和低电平时，第二输入模块对驱动控制端放电。The second input module, the second input module includes at least one second switch transistor in cascade connection, the at least one second switch transistor in cascade connection is coupled between the second signal input terminal and the drive control terminal, and the first stage of the second switch transistor The first pole is used to input the second clock signal, and the second pole of the second switching transistor in the tail stage is coupled to the driving control terminal. The control poles of the second switching transistors are coupled to the second signal input terminal for inputting the second pulse signal; In the reverse scan mode, the second input module charges the drive control terminal in response to the high-level overlap period signal of the second pulse signal and the second clock signal; in the forward scan mode, the second pulse signal and the second clock signal When the signals are at high level and low level respectively, the second input module discharges the drive control terminal.

第二输入模块还包括第十六晶体管，第十六晶体管的控制极用于输入控制信号，第一极耦合至首级开关四晶体管的第二极，第二极耦合至低电平端；第十六晶体管在控制信号高电平信号控制下将首级第二开关晶体管的第二极耦合至低电平端，在控制信号低电平信号控制下第十六晶体管断开。The second input module also includes a sixteenth transistor, the control pole of the sixteenth transistor is used to input the control signal, the first pole is coupled to the second pole of the first stage switch four transistor, and the second pole is coupled to the low level terminal; the tenth The six transistors couple the second pole of the second switch transistor of the first stage to the low level terminal under the control of the high level signal of the control signal, and the sixteenth transistor is turned off under the control of the low level signal of the control signal.

第一时钟信号与第三时钟信号互补。The first clock signal is complementary to the third clock signal.

根据本申请的第三方面，本申请提供一种栅极驱动电路，包括：According to a third aspect of the present application, the present application provides a gate drive circuit, including:

N个级联的栅极驱动电路单元，其中，N为大于1的整数。其中，首级采用如上述第一方面提供的栅极驱动电路单元；尾级采用上述第二方面提供的栅极驱动电路单元。N cascaded gate drive circuit units, wherein N is an integer greater than 1. Wherein, the first stage adopts the gate drive circuit unit provided in the above first aspect; the tail stage adopts the gate drive circuit unit provided in the above second aspect.

根据本申请的第四方面，本申请提供一种显示器，包括：According to a fourth aspect of the present application, the present application provides a display, comprising:

显示面板，显示面板上制作有第一方向的栅极线和第二方向的数据线；A display panel, on which gate lines in the first direction and data lines in the second direction are fabricated;

上述栅极驱动电路，栅极驱动电路中栅极驱动单元的信号输出端耦合到与其对应的栅极线；In the above gate drive circuit, the signal output end of the gate drive unit in the gate drive circuit is coupled to the corresponding gate line;

时序产生电路，用于产生栅极驱动电路所需的各种控制信号；Timing generation circuit, used to generate various control signals required by the gate drive circuit;

数据驱动电路，用于产生图像数据信号，并将其输出到显示面板中与其对应的数据线上。The data driving circuit is used to generate image data signals and output them to corresponding data lines in the display panel.

本申请的有益效果是：本申请提供的栅极驱动单元电路中，通过在第一输入模块和第二输入模块中额外增加晶体管和一路控制信号的输入，从而实现了扫描模式和非扫描模式的控制，在扫描模式中也能够实现正向扫描模式和反向扫描模式的切换，并且，栅极驱动电路单元中的各个模块为两种扫描模式共用，提高了各模块的利用效率。The beneficial effects of the present application are: in the gate drive unit circuit provided by the present application, by additionally adding a transistor and an input of a control signal in the first input module and the second input module, the scanning mode and the non-scanning mode are realized. control, in the scanning mode, switching between the forward scanning mode and the reverse scanning mode can also be realized, and each module in the gate drive circuit unit is shared by the two scanning modes, which improves the utilization efficiency of each module.

本申请还采用上述移位寄存器单元构成栅极驱动电路，可以与像素TFT一起制作于显示面板上。采用一套电路实现多扫描模式集成栅极驱动电路的设计，元器件数量少、结构简单，合理利用各元器件，提高了集成化程度。The present application also adopts the above-mentioned shift register unit to form a gate driving circuit, which can be fabricated on a display panel together with pixel TFTs. A set of circuits is used to realize the design of the multi-scan mode integrated gate drive circuit, the number of components is small, the structure is simple, and the components are rationally used to improve the degree of integration.

此外，本申请提供的栅极驱动电路中改进的输入模块可以实现多输入的逻辑运算，电路结构简单，对晶体管的沟道宽长比依赖性小。In addition, the improved input module in the gate drive circuit provided by the present application can realize multi-input logic operations, has a simple circuit structure, and has little dependence on the channel width-to-length ratio of transistors.

附图说明Description of drawings

图1为本申请实施例一栅极驱动电路单元电路结构图；FIG. 1 is a circuit structure diagram of a gate drive circuit unit according toEmbodiment 1 of the present application;

图2为本申请实施例一栅极驱动电路单元正向扫描模式时序图；FIG. 2 is a timing diagram of a forward scanning mode of a gate drive circuit unit according to an embodiment of the present application;

图3(a)为本申请实施例一第一输入模块1的一种结构图，Fig. 3 (a) is a kind of structural diagram of thefirst input module 1 of embodiment one of the present application,

图3(b)为本申请实施例一第一输入模块1的另一种结构图；Fig. 3 (b) is another kind of structural diagram of thefirst input module 1 of embodiment one of the present application;

图4为本申请实施例二公开的一种栅极驱动电路；FIG. 4 is a gate drive circuit disclosed inEmbodiment 2 of the present application;

图5为本申请实施例二栅极驱动电路正向扫描模式输出的栅极扫描信号图；5 is a diagram of the gate scan signal output by the gate drive circuit in the second embodiment of the present application in the forward scan mode;

图6为本申请实施例二反向扫描模式输出的栅极扫描信号图；FIG. 6 is a diagram of the gate scan signal output in the reverse scan mode ofEmbodiment 2 of the present application;

图7为本申请实施例三第n级栅极驱动电路单元结构图；FIG. 7 is a structural diagram of an n-level gate drive circuit unit in Embodiment 3 of the present application;

图8为本申请实施例四首级栅极驱动电路单元结构图；FIG. 8 is a structural diagram of a first-stage gate drive circuit unit inEmbodiment 4 of the present application;

图9为本申请实施例四尾级栅极驱动电路单元结构图；FIG. 9 is a structural diagram of a four-tail gate drive circuit unit according to an embodiment of the present application;

图10为本申请实施例五公开的一种显示器结构图；FIG. 10 is a structural diagram of a display disclosed in Embodiment 5 of the present application;

图11为本申请实施例六公开的一种逻辑传输电路结构；FIG. 11 is a logic transmission circuit structure disclosed in Embodiment 6 of the present application;

图12为本申请实施例六公开的一种逻辑与传输电路结构；FIG. 12 is a logic and transmission circuit structure disclosed in Embodiment 6 of the present application;

图13为本申请实施例六公开的一种逻辑异或传输电路结构。FIG. 13 is a logic XOR transmission circuit structure disclosed in Embodiment 6 of the present application.

具体实施方式Detailed ways

本领域技术人员应该理解，本申请栅极驱动电路（单元）在电路结构上的改进点在于第一输入模块1和第二输入模块2，其它模块均可采用现有成熟的技术方案，而在现有技术中，其它模块难以在本申请中穷举。因此，以下实施例的其它模块都只能视为对本申请技术方案的一方面或多方面的示例性说明，而不能认定为本申请技术方案的全部内容。其中的一方面或多方面包括本申请技术方案的一个要素或多个要素。Those skilled in the art should understand that the improvement in the circuit structure of the gate drive circuit (unit) of this application lies in thefirst input module 1 and thesecond input module 2, and other modules can use existing mature technical solutions, while in In the prior art, it is difficult to exhaustively list other modules in this application. Therefore, other modules of the following embodiments can only be regarded as an exemplary description of one or more aspects of the technical solution of the present application, and cannot be regarded as the entire content of the technical solution of the present application. One or more of them include one or more elements of the technical solutions of the present application.

首先对本申请中的专业术语进行解释/定义。First, the technical terms in this application are explained/defined.

互补：当一种信号为高电平时，与之相对应的另一种信号为低电平；当一种信号为低电平时，与之相对应的另一种信号为高电平。需要说明的是，本实施例定义的互补仅在电平高低关系上予以限定，而对高低电平的幅值大小关系并未作严格的限定。Complementary: When one signal is high, the corresponding signal is low; when one signal is low, the other corresponding signal is high. It should be noted that the complementarity defined in this embodiment is only limited on the relationship between high and low levels, and there is no strict limitation on the relationship between the amplitudes of high and low levels.

本申请中的晶体管可以为双极型晶体管或场效应晶体管。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极。显示器中的晶体管通常为薄膜晶体管(TFT)。Transistors in this application may be bipolar transistors or field effect transistors. When the transistor is a bipolar transistor, its control pole refers to the base of the bipolar transistor, the first pole can be the collector or emitter of the bipolar transistor, and the corresponding second pole can be the base of the bipolar transistor. Emitter or collector; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first pole can be the drain or source of the field effect transistor, and the corresponding second pole can be a field effect transistor The source or drain of a transistor. Transistors in displays are typically thin film transistors (TFTs).

氧化物晶体管（Indium Gallium Zinc Oxide，IGZO TFT）因其具有高的迁移率，更好的稳定性而更适合于高分辨率、大面积的显示器应用，更有可能成为未来的主流TFT技术。采用IGZO TFT来设计GIA电路，可能将电路的速度进一步提高、稳定性进一步增强、功耗进一步减少。其是相比于硅基TFT，IGZO TFT的泄露电流较小，于是在显示静态图像时候的，TFT面板的刷新频率可以减小，从而减少TFT面板的功耗。Oxide transistors (Indium Gallium Zinc Oxide, IGZO TFT) are more suitable for high-resolution, large-area display applications because of their high mobility and better stability, and are more likely to become the mainstream TFT technology in the future. Using IGZO TFT to design the GIA circuit may further increase the speed of the circuit, further enhance the stability, and further reduce power consumption. Compared with silicon-based TFTs, IGZO TFTs have a smaller leakage current, so when displaying static images, the refresh frequency of the TFT panel can be reduced, thereby reducing the power consumption of the TFT panel.

相关研究表明，非晶或者C轴取向的晶态IGZO TFT的泄露电流可能小至10^-20A/um，这比硅基半导体器件小若干数量级。而且先进工艺制备的IGZO TFT的亚阈值斜率可以接近甚至突破硅基半导体器件的亚阈值斜率的极限值。换言之，IGZO TFT的重要特性之一是其能够较彻底地关断。利用IGZO TFT的优秀关断特性，TFT面板阵列的刷新频率可能减小，这可能在某些显示场合减少TFT面板的功耗、减少使用者的用眼疲劳。例如，对于彩色电子纸或者彩色电润湿显示器而言，当显示静态图像时，TFT面板的帧频可能减少到0.1Hz甚至更小；当显示动态彩色图像时，TFT面板的帧频则恢复到普通的60Hz或者更高一些。Related studies have shown that the leakage current of amorphous or C-axis-oriented crystalline IGZO TFTs may be as small as 10^-20 A/um, which is several orders of magnitude smaller than that of silicon-based semiconductor devices. Moreover, the sub-threshold slope of the IGZO TFT prepared by advanced technology can approach or even break through the limit value of the sub-threshold slope of silicon-based semiconductor devices. In other words, one of the important characteristics of the IGZO TFT is that it can be turned off relatively completely. Utilizing the excellent turn-off characteristics of IGZO TFT, the refresh frequency of the TFT panel array may be reduced, which may reduce the power consumption of the TFT panel and reduce the eye fatigue of users in some display occasions. For example, for color electronic paper or color electrowetting displays, when displaying static images, the frame rate of the TFT panel may be reduced to 0.1Hz or even less; when displaying dynamic color images, the frame rate of the TFT panel is restored to Ordinary 60Hz or higher.

鉴于此，本申请实施例以晶体管是IGZO TFT为例对本申请作进一步详细说明。需要说明的是，本申请的电路结构也适于采用其它氧化物晶体管或者其他的迁移率较高、关态电流较小的晶体管。In view of this, the embodiment of the present application will further describe the present application in detail by taking the transistor as an example of an IGZO TFT. It should be noted that the circuit structure of the present application is also suitable for using other oxide transistors or other transistors with high mobility and low off-state current.

请参考图1，本实施例中的栅极驱动单元电路包括：第一信号输入端、第二信号输入端、第一时钟信号输入端、信号输出端、驱动模块3、低电平维持模块5、第一输入模块1和第二输入模块2。Please refer to FIG. 1 , the gate drive unit circuit in this embodiment includes: a first signal input terminal, a second signal input terminal, a first clock signal input terminal, a signal output terminal, a driving module 3, and a low level maintaining module 5 , thefirst input module 1 and thesecond input module 2 .

第一信号输入端，用于输入第一脉冲信号V_I1。The first signal input terminal is used for inputting the first pulse signal V_I1 .

第二信号输入端，用于输入第二脉冲信号V_I2。The second signal input terminal is used for inputting the second pulse signal V_I2 .

第一时钟信号输入端，用于输入第一时钟信号V_A。The first clock signal input terminal is used for inputting the first clock signal V_A .

信号输出端，用于输出脉冲驱动信号V_O。The signal output terminal is used for outputting the pulse driving signal V_O .

驱动模块3耦合在第一时钟信号输入端和信号输出端之间。在其驱动控制端Q获得驱动电压后，将第一时钟信号V_A传送到信号输出端，当第一时钟信号V_A为高电平时，驱动模块3对信号输出端上拉充电；当第一时钟信号V_A为低电平时，驱动模块3对信号输出端V_O下拉放电。The driving module 3 is coupled between the first clock signal input terminal and the signal output terminal. After the driving control terminal Q obtains the driving voltage, the first clock signal V_A is transmitted to the signal output terminal, and when the first clock signal V_A is at a high level, the driving module 3 pulls up and charges the signal output terminal; When the clock signal V_A is at low level, the driving module 3 pulls down and discharges the signal output terminal V_O.

低电平维持模块5耦合在信号输出端和低电平端之间。低电平维持模块5响应第一时钟信号V_A的高电平信号或第三时钟信号V_C的高电平信号将信号输出端耦合至低电平端，维持信号输出端低电平电位。The low level maintaining module 5 is coupled between the signal output terminal and the low level terminal. The low-level maintaining module 5 responds to the high-level signal of the first clock signal_VA or the high-level signal of the third clock signal_VC to couple the signal output end to the low-level end, and maintain the low-level potential of the signal output end.

通常，为了抑制馈通效应，在一种实施例中，低电平维持模块5还可以包括低电平维持使能单元4，低电平维持使能单元4耦合在第一时钟信号输入端和低电平端，低电平维持使能单元4还耦合在信号输出端。在本级栅极驱动电路单元被选通阶段，低电平维持使能单元4响应脉冲驱动信号V_O将其低电平维持使能端P耦合到低电平端，输出低电平信号；在低电平维持阶段，低电平维持使能单元4在第一时钟信号V_A控制下低电平维持使能端P输出高电平信号。此时，低电平维持模块5响应低电平维持使能端P输出的高电平信号或第三时钟信号V_C的高电平信号将信号输出端耦合至低电平端，维持信号输出端低电平电位。Usually, in order to suppress the feed-through effect, in one embodiment, the low-level maintenance module 5 may further include a low-levelmaintenance enabling unit 4, and the low-levelmaintenance enabling unit 4 is coupled between the first clock signal input terminal and the At the low level end, the low level maintaining enablingunit 4 is also coupled to the signal output end. When the gate drive circuit unit of this stage is selected, the low-level maintenance enableunit 4 responds to the pulse drive signal V_O to couple its low-level maintenance enable terminal P to the low-level terminal, and outputs a low-level signal; In the low-level maintenance stage, the low-levelmaintenance enabling unit 4 outputs a high-level signal from the low-level maintenance enabling terminal P under the control of the first clock signal_VA . At this time, the low-level maintenance module 5 responds to the high-level signal output by the low-level maintenance enabling terminal P or the high-level signal of the third clock signal V_C to couple the signal output terminal to the low-level terminal to maintain the signal output terminal low level potential.

第一输入模块1包括级联的至少一个第一开关晶体管T11，级联的至少一个第一开关晶体管T11耦合在所述第一信号输入端和驱动控制端Q之间，首级第一开关晶体管T11的第一极（例如漏极）用于输入第四时钟信号V_D，尾级第一开关晶体管T11的第二极（例如源极）耦合在驱动控制端Q；各第一开关晶体管T11的控制极（例如栅极）耦合在第一信号输入端，用于输入第一脉冲信号V_I1。在正向扫描模式下，第一输入模块1响应第一脉冲信号V_I1和第四时钟信号V_D的高电平交叠期信号对驱动控制端Q充电；在反向扫描模式下，第一脉冲信号V_I1和第四时钟信号V_D分别为高电平和低电平时，第一输入模块1对驱动控制端Q放电；Thefirst input module 1 includes at least one first switch transistor T11 connected in cascade, the at least one first switch transistor T11 in cascade is coupled between the first signal input terminal and the drive control terminal Q, the first switch transistor The first pole (such as the drain) of T11 is used to input the fourth clock signal V_D , and the second pole (such as the source) of the first switching transistor T11 in the tail stage is coupled to the drive control terminal Q; each of the first switching transistors T11 The control electrode (eg gate) is coupled to the first signal input end for inputting the first pulse signal V_I1 . In the forward scan mode, thefirst input module 1 charges the drive control terminal Q in response to the high-level overlapping period signal of the first pulse signal V_I1 and the fourth clock signal V_D ; in the reverse scan mode, the first When the pulse signal V_I1 and the fourth clock signal V_D are at high level and low level respectively, thefirst input module 1 discharges the drive control terminal Q;

第二输入模块2包括级联的至少一个第二开关晶体管T14，级联的至少一个第二开关晶体管T14耦合在第二信号输入端和驱动控制端Q之间，首级第二开关晶体管T14的第一极（例如漏极）用于输入第二时钟信号V_B，尾级第二开关晶体管T14的第二极（例如源极）耦合在驱动控制端Q，各第二开关晶体管T14的控制极（例如栅极）耦合在第二信号输入端，用于输入第二脉冲信号V_I2。在反向扫描模式下，第二输入模块2响应第二脉冲信号V_I2和第二时钟信号V_B的高电平交叠期信号对驱动控制端Q充电；在正向扫描模式下，第二脉冲信号V_I2和第二时钟信号V_B分别为高电平和低电平时，第二输入模块2对驱动控制端Q放电。Thesecond input module 2 includes at least one second switch transistor T14 in cascade connection, and the at least one second switch transistor T14 in cascade connection is coupled between the second signal input terminal and the drive control terminal Q, and the first stage of the second switch transistor T14 The first pole (such as the drain) is used to input the second clock signal V_B , the second pole (such as the source) of the second switching transistor T14 in the tail stage is coupled to the drive control terminal Q, and the control poles of each second switching transistor T14 (for example, the gate) is coupled to the second signal input end for inputting the second pulse signal V_I2 . In the reverse scan mode, thesecond input module 2 charges the drive control terminal Q in response to the high-level overlap period signal of the second pulse signal V_I2 and the second clock signal V_B ; in the forward scan mode, the second When the pulse signal V_I2 and the second clock signal V_B are at high level and low level respectively, thesecond input module 2 discharges the driving control terminal Q.

在第一种栅极驱动电路单元电路结构中，第一输入模块1还包括第十五晶体管T15。第十五晶体管T15的控制极（例如栅极）用于输入控制信号V_CTR，第一极（例如漏极）耦合至首级第一开关晶体管T11的第二极（例如源极），第二极（例如源极）耦合至低电平端。第十五晶体管T15在控制信号V_CTR高电平信号控制下将首级第一开关晶体管T11的第二极（例如源极）耦合至低电平端，在控制信号V_CTR低电平信号控制下第十五晶体管T15断开。In the first gate drive circuit unit circuit structure, thefirst input module 1 further includes a fifteenth transistor T15. The control electrode (such as the gate) of the fifteenth transistor T15 is used to input the control signal V_CTR , the first electrode (such as the drain) is coupled to the second electrode (such as the source) of the first switch transistor T11 in the first stage, and the second Pole (such as source) is coupled to the low-level terminal. The fifteenth transistor T15 couples the second pole (such as the source₎ of the first switching transistor T11 to the low level terminal under the control of the high level signal V CTR, and under the control of the low level signal V_CTR The fifteenth transistor T15 is turned off.

在第二种栅极驱动电路单元电路结构中，第二输入模块2还包括第十六晶体管T16。第十六晶体管T16的控制极（例如栅极）用于输入控制信号V_CTR，第一极（例如漏极）耦合至首级开关四晶体管T14的第二极（例如源极），第二极（例如源极）耦合至低电平端。第十六晶体管T16在控制信号V_CTR高电平信号控制下将首级第二开关晶体管T14的第二极（例如源极）耦合至低电平端，在控制信号V_CTR低电平信号控制下第十六晶体管T16断开。In the second gate drive circuit unit circuit structure, thesecond input module 2 further includes a sixteenth transistor T16. The control pole (such as the gate) of the sixteenth transistor T16 is used to input the control signal V_CTR , the first pole (such as the drain) is coupled to the second pole (such as the source) of the first-stage switch transistor T14, and the second pole (such as source) coupled to the low-level terminal. The sixteenth transistor T16 couples the second pole (such as the source) of the second switching transistor T14 of the first stage to the low level terminal under the control of the high level signal of the control signal V_CTR , and under the control of the low level signal of the control signal V_CTR The sixteenth transistor T16 is turned off.

或者，进一步地，在第三种栅极驱动电路单元结构中，也可以同时构建上述两种栅极驱动电路单元电路结构，即第一输入模块1还包括第十五晶体管T15，第二输入模块2还包括第十六晶体管T16。此时，第十五晶体管T15和第十六晶体管T16的控制极（例如栅极）还可以共用控制信号V_CTR。Or, further, in the third gate drive circuit unit structure, the above two gate drive circuit unit circuit structures can also be constructed at the same time, that is, thefirst input module 1 also includes a fifteenth transistor T15, and thesecond input module 1 2 also includes a sixteenth transistor T16. At this time, the control electrodes (eg, gates) of the fifteenth transistor T15 and the sixteenth transistor T16 may also share the control signal V_CTR .

其中，第一时钟信号V_A与第三时钟信号V_C互补。Wherein, the first clock signal_VA is complementary to the third clock signal_VC .

进一步，在本实施例中，各时钟信号/脉冲信号之间应该满足如下关系：Further, in this embodiment, the following relationship should be satisfied between each clock signal/pulse signal:

第一脉冲信号V_I1和第二脉冲信号V_I2间隔一个时钟信号周期；The interval between the first pulse signal V_I1 and the second pulse signal V_I2 is one clock signal period;

第二时钟信号V_B与第四时钟信号V_D互补；The second clock signal V_B is complementary to the fourth clock signal V_D ;

在正向扫描模式下，第四时钟信号V_D滞后于第一脉冲信号V_I1一个相位，第一时钟信号V_A滞后于第四时钟信号V_D一个相位；In the forward scanning mode, the fourth clock signal V_D lags behind the first pulse signal V_I1 by one phase, and the first clock signal V_A lags behind the fourth clock signal V_D by one phase;

在反向扫描模式下，第二时钟信号V_B滞后于第二脉冲信号V_I2一个相位，第四时钟信号V_D滞后于第一时钟信号V_A一个相位。In the reverse scan mode, the second clock signal V_B lags behind the second pulse signal V_I2 by one phase, and the fourth clock signal V_D lags behind the first clock signal V_A by one phase.

其中，一个相位为为T/4，T为时钟信号的周期。Wherein, one phase is T/4, and T is a period of the clock signal.

下面将通过以下具体实施例对上述各模块进行阐述。The above-mentioned modules will be described below through the following specific embodiments.

实施例一：Embodiment one:

请参考图1，在一种具体实施例中：Please refer to Figure 1, in a specific embodiment:

驱动模块3包括第二晶体管T2和第一电容C1。第二晶体管T2的控制极耦合到驱动控制端Q，第一极耦合到第一时钟信号输入端，第二极耦合到信号输出端；第一电容C1的一端耦合到驱动控制端Q，另一端耦合到信号输出端。The driving module 3 includes a second transistor T2 and a first capacitor C1. The control pole of the second transistor T2 is coupled to the drive control terminal Q, the first pole is coupled to the first clock signal input terminal, and the second pole is coupled to the signal output terminal; one end of the first capacitor C1 is coupled to the drive control terminal Q, and the other end coupled to the signal output.

低电平维持模块5包括低电平维持使能单元4和第一低电平维持单元51。低电平维持使能单元4包括第六晶体管T6和第二电容C2。第六晶体管T6的控制极耦合到信号输出端，第一极耦合到低电平维持使能端P，第二极耦合到低电平端；第二电容C2的一端耦合到第一时钟信号输入端，另一端耦合到低电平维持使能端P。The low level maintaining module 5 includes a low level maintaining enablingunit 4 and a first lowlevel maintaining unit 51 . The low level maintaining enablingunit 4 includes a sixth transistor T6 and a second capacitor C2. The control pole of the sixth transistor T6 is coupled to the signal output terminal, the first pole is coupled to the low-level maintenance enabling terminal P, and the second pole is coupled to the low-level terminal; one end of the second capacitor C2 is coupled to the first clock signal input terminal , and the other end is coupled to the low-level maintenance enable end P.

第一低电平维持单元51包括：第四晶体管T4和第七晶体管T7。第四晶体管T4的控制极用于输入第三时钟信号V_C，第一极耦合到信号输出端，第二极耦合到低电平端；第七晶体管T7的控制极耦合到低电平维持使能端P，第一极耦合到信号输出端，第二极耦合到低电平端。The first lowlevel maintaining unit 51 includes: a fourth transistor T4 and a seventh transistor T7. The control pole of the fourth transistor T4 is used to input the third clock signal V_C , the first pole is coupled to the signal output terminal, and the second pole is coupled to the low-level terminal; the control pole of the seventh transistor T7 is coupled to the low-level maintenance enable Terminal P, the first pole is coupled to the signal output terminal, and the second pole is coupled to the low level terminal.

进一步，在另一种具体实施例中，低电平维持模块5还可以包括第二低电平维持单元52，第二低电平维持单元52包括第五晶体管T5。第五晶体管T5的控制极耦合到低电平维持使能端P，第一极耦合到驱动控制端Q，第二极耦合到低电平端。Further, in another specific embodiment, the low-level maintaining module 5 may further include a second low-level maintaining unit 52, and the second low-level maintaining unit 52 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is coupled to the low-level maintaining enabling terminal P, the first electrode is coupled to the driving control terminal Q, and the second electrode is coupled to the low-level terminal.

在其它实施例中，上述各模块/单元也可以采用现有的其它方案。In other embodiments, the above-mentioned modules/units may also adopt other existing solutions.

在一种具体实施例中，结合第一输入模块1和第二输入模块2，当控制信号V_CTR为低电平时，第十五晶体管T15和第十六晶体管T16关断，栅极驱动电路单元具有正常的正向/反向扫描模式功能。由于级联的第一开关晶体管T11的控制极（例如栅极）短接，因此，级联的第一开关晶体管T11可以等效为一个开关晶体管，并由第一脉冲信号V_I1控制其导通/断开；同样的，级联的第二开关晶体管T14也可以等效为一个开关晶体管，并由第二脉冲信号V_I2控制其导通/断开。In a specific embodiment, in combination with thefirst input module 1 and thesecond input module 2, when the control signal V_CTR is at a low level, the fifteenth transistor T15 and the sixteenth transistor T16 are turned off, and the gate drive circuit unit Has normal forward/reverse scan mode functionality. Since the control electrode (for example, the gate) of the cascaded first switching transistor T11 is short-circuited, the cascaded first switching transistor T11 can be equivalent to a switching transistor, and its conduction is controlled by the first pulse signal V_I1 Similarly, the cascaded second switching transistor T14 can also be equivalent to a switching transistor, and its on/off is controlled by the second pulse signal V_I2 .

当控制信号V_CTR为高平时，第十五晶体管T15/第十六晶体管T16导通，级联的第一开关晶体管T11与第十五晶体管T15互连的节点被钳置于低电平端，保持低电位；同样的，级联的第二开关晶体管T14与第十六晶体管T16互连的节点也被钳置于低电平端，保持低电位。因此，无论是正向或者反向扫描模式，驱动控制端Q的电位都无法上升到较高电位。栅极驱动电路单元均输出零电平，停止扫描功能。When the control signal V_CTR is high, the fifteenth transistor T15/the sixteenth transistor T16 is turned on, and the interconnection node of the cascaded first switching transistor T11 and the fifteenth transistor T15 is clamped at the low level end, keeping Low potential; similarly, the interconnection node of the second cascaded switch transistor T14 and the sixteenth transistor T16 is also clamped to the low level end to keep the low potential. Therefore, no matter in the forward or reverse scanning mode, the potential of the driving control terminal Q cannot rise to a higher potential. The gate driving circuit units all output zero level, and the scanning function is stopped.

下文将以第三种栅极驱动电路单元为例针对图1阐述本申请技术方案的工作过程。对于第一种和第二种栅极驱动电路单元工作过程，本领域技术人员可以很容易根据本实施例公开的内容分析得出，因此不再赘述。如图2所示为本实施例中移位寄存器单元正向扫描模式的时序图，对于反向扫描模式，原理相同，在此不再另绘时序图。该移位寄存器单元的工作过程可以分为五个阶段：（1）预充电阶段，（2）上拉阶段，（3）下拉阶段，（4）放电阶段，（5）低电平维持阶段。下面将详细说明这五个阶段的工作过程。The working process of the technical solution of the present application will be described below with reference to FIG. 1 by taking the third gate driving circuit unit as an example. Those skilled in the art can easily analyze the working process of the first and second gate drive circuit units based on the content disclosed in this embodiment, so details are not repeated here. As shown in FIG. 2 , the timing diagram of the forward scanning mode of the shift register unit in this embodiment is shown. For the reverse scanning mode, the principle is the same, and no further timing diagram is drawn here. The working process of the shift register unit can be divided into five stages: (1) pre-charging stage, (2) pull-up stage, (3) pull-down stage, (4) discharge stage, (5) low-level maintenance stage. The working process of these five stages will be described in detail below.

（1）预充电阶段t1(1) Precharge phase t1

在预充电阶段，第一输入模块1或第二输入模块2给驱动控制端Q充电提供高电平电压，驱动模块3在自举动作触发之前被预先打开。在此阶段，必须提供足够高的开启电压给驱动模块3，避免因驱动模块3的驱动能力不足，使后续的上拉/下拉过程中出现较严重的拖尾现象。In the pre-charging stage, thefirst input module 1 or thesecond input module 2 charges the drive control terminal Q to provide a high-level voltage, and the drive module 3 is pre-opened before the bootstrap action is triggered. At this stage, a sufficiently high turn-on voltage must be provided to the driving module 3 to avoid serious tailing phenomenon in the subsequent pull-up/pull-down process due to insufficient driving capability of the driver module 3 .

在此阶段，控制信号V_CTR为低电平，第十五晶体管T15和第十六晶体管T16被关断。在正向扫描模式情况下，第一脉冲信号V_I1和第四时钟信号V_D为高电平，于是级联的第一开关晶体管T11被导通，驱动控制端Q被充电到高电平状态；在反向扫描模式情况下，第二脉冲信号V_I2和第二时钟信号V_B为高电平，于是级联的第十四晶体管T14被导通，驱动控制端Q被充电到高电平状态。At this stage, the control signal V_CTR is at a low level, and the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. In the forward scanning mode, the first pulse signal V_I1 and the fourth clock signal V_D are at high level, so the cascaded first switching transistor T11 is turned on, and the drive control terminal Q is charged to a high level state ; In the case of reverse scan mode, the second pulse signal V_I2 and the second clock signal V_B are high level, so the fourteenth transistor T14 in cascade is turned on, and the drive control terminal Q is charged to high level state.

总之，无论是正向或者反向扫描，在预充电阶段t1，驱动控制端Q被充电到高电平状态，第二晶体管T2被充分打开。这为接下来的上拉阶段做好了准备。第二晶体管T2被打开的程度越充分，接下来的上拉/下拉阶段中，第二晶体管T2的驱动能力越强。In a word, regardless of forward scanning or reverse scanning, in the pre-charging phase t1, the driving control terminal Q is charged to a high level state, and the second transistor T2 is fully turned on. This sets the stage for the next pull-up phase. The more fully the second transistor T2 is turned on, the stronger the driving capability of the second transistor T2 will be in the subsequent pull-up/pull-down phase.

（2）上拉阶段t2(2) Pull-up phase t2

继预充电阶段t1之后是上拉阶段t2。在上拉阶段t2，第一时钟信号V_A为高电平，在第一时钟信号V_A的作用下，通过自举原理，驱动模块3以较强的驱动能力将信号输出端上拉到高电平。在扫描过程中，平板显示阵列中的开关器件的开启程度与扫描脉冲的幅度以及有效扫描脉冲时间密切相关。所以上拉阶段时，驱动模块3的响应速度必须足够快。Following the pre-charge phase t1 is the pull-up phase t2. In the pull-up phase t2, the first clock signal V_A is at a high level, and under the action of the first clock signal V_A , through the bootstrap principle, the driving module 3 pulls the signal output terminal to a high level with a strong driving capability level. During the scanning process, the turn-on degree of the switching devices in the flat panel display array is closely related to the amplitude of the scanning pulse and the effective scanning pulse time. Therefore, during the pull-up phase, the response speed of the driving module 3 must be fast enough.

在上拉阶段t2，第一脉冲信号V_I1和第二脉冲信号V_I2均为低电平，因此，与驱动控制端Q相连的第一开关晶体管T11和T14均处于断开状态。换言之，在上拉阶段t2，驱动控制端Q是一种悬浮的状态。In the pull-up phase t2, both the first pulse signal V_I1 and the second pulse signal V_I2 are at low level, therefore, the first switching transistors T11 and T14 connected to the driving control terminal Q are both in an off state. In other words, during the pull-up phase t2, the drive control terminal Q is in a suspended state.

此外，由于第二晶体管T2已经在预充电阶段t1被开启而处于闭合导通状态，而且驱动控制端Q几乎是悬浮的，故第二晶体管T2在上拉阶段保持为导通状态。由于第二晶体管T2已经在预充电阶段t1被开启而处于闭合状态，第二晶体管T2的C_GD2（第一极和控制极之间的电容，例如栅极-漏极电容）等于C_GS2（控制极和第二极之间的电容，例如栅极-源极电容），且均为栅极介质层电容的一半。且第二晶体管T2的第一极（例如漏极）耦合的第一时钟信号V_A变成高电平，此情况带来了下面两种变化：(1)第二晶体管T2的C_GD2将第一时钟信号V_A的高电平耦合到驱动控制端Q，驱动控制端Q上的电位因为耦合而迅速地抬高。因此，第二晶体管T2的控制极-第二极（例如栅极-源极）电压差增加，第二晶体管T2的上拉驱动能力增强。(2)较强的电流从处于高电平状态的第一时钟信号V_A通过保持闭合的第二晶体管T2流到栅极驱动电路单元的信号输出端。因此与信号输出端耦合的负载电容C_L上因为正电荷的积累，其上的电平被抬高。且驱动控制端Q上的电位也随着输出脉冲驱动信号V_O的电平抬高而上升。最终，输出脉冲驱动信号V_O被无电压损失地上拉到第一高电平电压V_H。上述过程即为电压自举效应。In addition, since the second transistor T2 has been turned on in the pre-charging phase t1 and is in the closed conduction state, and the driving control terminal Q is almost suspended, the second transistor T2 remains in the conduction state in the pull-up phase. Since the second transistor T2 has been turned on in the pre-charging phase t1 and is in the closed state, the C_GD2 (capacitance between the first electrode and the control electrode, such as gate-drain capacitance) of the second transistor T2 is equal to C_GS2 (control The capacitance between the pole and the second pole, such as the gate-source capacitance), is half of the capacitance of the gate dielectric layer. And the first clock signal V_A coupled to the first pole (for example, the drain) of the second transistor T2 becomes a high level, which brings about the following two changes: (1) C_GD2 of the second transistor T2 changes the first The high level of a clock signal V_A is coupled to the drive control terminal Q, and the potential on the drive control terminal Q rises rapidly due to the coupling. Therefore, the voltage difference between the control electrode and the second electrode (for example, the gate-source electrode) of the second transistor T2 increases, and the pull-up driving capability of the second transistor T2 is enhanced. (2) A strong current flows from the first clock signal V_A in a high level state to the signal output terminal of the gate drive circuit unit through the second transistor T2 kept closed. Therefore, the level of the load capacitor_CL coupled to the signal output terminal is raised due to the accumulation of positive charges. And the potential on the driving control terminal Q also rises as the level of the output pulse driving signal V_O rises. Finally, the output pulse driving signal V_O is pulled up to the first high-level voltage V_H without voltage loss. The above process is the voltage bootstrap effect.

（3）下拉阶段t3(3) Pull-down stage t3

继上拉阶段t2之后的是下拉阶段t3。在下拉阶段t3，信号输出端被下拉到低电平V_L。在下拉阶段结束时，信号输出端也应将保持低电平电压V_L不变。Following the pull-up phase t2 is a pull-down phase t3. In the pull-down phase t3, the signal output terminal is pulled down to a low level V_L . At the end of the pull-down phase, the signal output terminal should also keep the low-level voltage V_L unchanged.

在下拉阶段t3的开始时，第一时钟信号V_A变为低电平。第一脉冲信号V_I1和第二脉冲信号V_I2仍然保持为低电平，因此第一开关晶体管T11和T14仍然保持为断开状态。从而驱动控制端Q在下拉阶段仍然保持为悬浮状态，所以在下拉阶段t3半段，第二晶体管T2仍然保持为导通。而第一时钟信号V_A已经变成为低电平V_L，从而栅极驱动电路单元的信号输出端被下拉到低电平电压V_L。At the beginning of the pull-down period t3, the first clock signal V_A becomes low level. The first pulse signal V_I1 and the second pulse signal V_I2 are still kept at low level, so the first switching transistors T11 and T14 are still kept in an off state. Therefore, the driving control terminal Q remains suspended during the pull-down phase, so the second transistor T2 remains turned on during the half of the pull-down phase t3. However, the first clock signal V_A has changed to a low level V_L , so that the signal output end of the gate driving circuit unit is pulled down to a low level voltage V_L .

（4）放电阶段t4(4) Discharge stage t4

继下拉阶段t3之后的是放电阶段t4。在放电阶段t4，驱动控制端Q放电下拉到低电平状态。Following the pull-down phase t3 is the discharge phase t4. In the discharging phase t4, the driving control terminal Q is discharged and pulled down to a low level state.

在放电阶段t4，第一时钟信号V_A保持为低电平，因此，信号输出端也保持低电平电压V_L不变。在正向扫描模式的情况下，第二脉冲信号V_I2变为高电平，从而导通第二开关晶体管T14，而第二时钟信号V_B变为低电平，因此，驱动控制端Q由第二时钟信号V_B通过导通的第二开关晶体管T14放电下拉到低电平状态；在反向扫描模式的情况下，第一脉冲信号V_I1变为高电平，从而导通第一开关晶体管T11，而第四时钟信号V_D变为低电平，因此，驱动控制端Q由第四时钟信号V_D通过导通的第一开关晶体管T11放电下拉到低电平状态。In the discharge phase t4, the first clock signal V_A remains at a low level, therefore, the signal output terminal also maintains a low level voltage V_L unchanged. In the case of the forward scanning mode, the second pulse signal V_I2 becomes high level, thereby turning on the second switching transistor T14, and the second clock signal V_B becomes low level, therefore, the driving control terminal Q is controlled by The second clock signal V_B is pulled down to a low level state through the discharge of the turned-on second switch transistor T14; in the case of the reverse scan mode, the first pulse signal V_I1 becomes high level, thereby turning on the first switch Transistor T11, and the fourth clock signal V_D becomes low level, therefore, the drive control terminal Q is pulled down to a low level state by the fourth clock signal V_D through the first switching transistor T11 which is turned on.

总之，无论是正向或者反向扫描模式，在放电阶段t4，驱动控制端Q被放电下拉到低电平状态，第二晶体管T2被关断。In short, regardless of the forward or reverse scanning mode, in the discharge phase t4, the driving control terminal Q is discharged and pulled down to a low level state, and the second transistor T2 is turned off.

（5）低电平维持阶段t5(5) Low level maintenance stage t5

继放电阶段t4之后，栅极驱动电路单元进入低电平维持阶段t5。在低电平维持阶段t5，信号输出端应该保持为低电平电压V_L。只有当栅极驱动电路单元的信号输出端保持为低电平电压V_L，才能保证：(1)与栅极驱动电路单元的信号输出端耦合的栅极扫描线上的像素中开关薄膜晶体管保持为关闭状态，相应的像素中编程得到的像素电荷不会严重地泄露。(2)与本级栅极驱动电路单元相连的前后各级栅极驱动电路单元不会受到影响，相邻各级的驱动控制端Q不会受到本级栅极扫描信号的影响而导致错误地充电或者放电动作。Following the discharge phase t4, the gate drive circuit unit enters a low-level maintenance phase t5. In the low-level maintaining phase t5, the signal output terminal should maintain a low-level voltage V_L . Only when the signal output terminal of the gate drive circuit unit is maintained at the low-level voltage V_L can it be guaranteed that: (1) the switching thin film transistor in the pixel on the gate scanning line coupled with the signal output terminal of the gate drive circuit unit remains In the off state, the pixel charge programmed in the corresponding pixel will not be seriously leaked. (2) The front and rear gate drive circuit units connected to the gate drive circuit unit of this stage will not be affected, and the drive control terminals Q of adjacent stages will not be affected by the gate scan signal of this stage, resulting in incorrect charging or discharging action.

因此，本实施例中用到两路互补的时钟信号：第一时钟信号V_A和第三时钟信号V_C来交替地给信号输出端放电，保证信号输出端总是保持为低电平电位。Therefore, in this embodiment, two complementary clock signals are used: the first clock signal_VA and the third clock signal_VC to alternately discharge the signal output terminal to ensure that the signal output terminal is always kept at a low level potential.

在低电平维持阶段t5，无论正向或者反向扫描模式，当第三时钟信号V_C为高电平时，第四晶体管T4被导通，信号输出端通过第四晶体管T4被耦合到低电平端，其电位被下拉到低电平电压V_L；在第一时钟信号V_A为高电平时，低电平维持使能端P通过第二电容C2被耦合到高电平电压，于是第五晶体管T5导通，将信号输出端耦合到低电平端，其电位被下拉到低电平电压V_L。In the low-level maintenance phase t5, regardless of the forward or reverse scanning mode, when the third clock signal V_C is at a high level, the fourth transistor T4 is turned on, and the signal output terminal is coupled to a low level through the fourth transistor T4. flat terminal, its potential is pulled down to low level voltage V_L ; when the first clock signal V_A is high level, the low level maintenance enabling terminal P is coupled to the high level voltage through the second capacitor C2, so the fifth The transistor T5 is turned on, and the signal output terminal is coupled to the low-level terminal, and its potential is pulled down to the low-level voltage V_L .

在另一种实施例中，在第一时钟信号V_A为高电平时，低电平维持使能端P获得高电平电位后，还将第五晶体管T5打开，将驱动控制端Q耦合到低电平端，从而使得在低电平维持阶段t5，能够更好地将驱动控制端Q的电位维持在低电平电压V_L，有效地维持了驱动控制端Q的低电平电位。In another embodiment, when the first clock signal V_A is at a high level, after the low-level maintenance enabling terminal P obtains a high-level potential, the fifth transistor T5 is also turned on, and the driving control terminal Q is coupled to The low-level end, so that in the low-level maintaining phase t5, the potential of the driving control terminal Q can be better maintained at the low-level voltage V_L , effectively maintaining the low-level potential of the driving control terminal Q.

本实施例中，第六晶体管T6的作用在信号输出端为高电平时，将低电平维持使能端P下拉到低电平。可以有效地防止在信号输出端输出脉冲驱动信号V_O过程中，低电平维持使能端P不被期望地上拉升压，从而导致低电平维持模块5开始工作。In this embodiment, the function of the sixth transistor T6 is to pull down the low-level maintaining enabling terminal P to a low level when the signal output terminal is at a high level. It can effectively prevent the low-level maintaining enable terminal P from being pulled up unexpectedly during the process of outputting the pulse driving signal V_O at the signal output terminal, thereby causing the low-level maintaining module 5 to start working.

需要说明的是，在一种具体实施例中，级联的第一开关晶体管T11可以是1个、2个或者多个：It should be noted that, in a specific embodiment, there may be one, two or more cascaded first switch transistors T11:

请参考图3（a），为当级联的第一开关晶体管T11只有一个时第一输入模块1的结构图。该结构是一种分压结构，在第一脉冲信号V_I1和控制信号V_CTR同时为高电平时，第一开关晶体管T11和第十五晶体管T15均处于导通状态，于是驱动控制端Q的电位由第一开关晶体管T11和第十五晶体管T15的分压决定。在控制信号V_CTR为高电平时，希望驱动控制端Q处于低电平状态，才能使得驱动模块3处于非使能状态，输出信号端保持为低电平。因此为了使得第十五晶体管T15分得的电压足够小，必须使得第十五晶体管T15的导通能力远大于第一开关晶体管T11，换言之，第十五晶体管T15的尺寸应该取得足够大。这一方面会增加第十五晶体管T15占用的面积，增加控制信号V_CTR的负载量；另一方面，第十五晶体管T15的泄露电流将由于第十五晶体管T15尺寸的增加而增加。于是，尺寸过大的第十五晶体管T15可能会降低驱动控制端Q的电压幅度，从而影响扫描模式的正常工作。Please refer to FIG. 3( a ), which is a structural diagram of thefirst input module 1 when there is only one cascaded first switching transistor T11 . This structure is a voltage dividing structure. When the first pulse signal V_I1 and the control signal V_CTR are at high level at the same time, both the first switch transistor T11 and the fifteenth transistor T15 are in the conduction state, thus driving the control terminal Q The potential is determined by the voltage division of the first switching transistor T11 and the fifteenth transistor T15. When the control signal V_CTR is at a high level, it is hoped that the driving control terminal Q is at a low level state, so that the driving module 3 is in a non-enabled state, and the output signal terminal remains at a low level. Therefore, in order to make the voltage divided by the fifteenth transistor T15 small enough, the turn-on capability of the fifteenth transistor T15 must be much greater than that of the first switch transistor T11 . In other words, the size of the fifteenth transistor T15 should be sufficiently large. On the one hand, this will increase the area occupied by the fifteenth transistor T15 and increase the load of the control signal V_CTR ; on the other hand, the leakage current of the fifteenth transistor T15 will increase due to the increase in size of the fifteenth transistor T15 . Therefore, the oversized fifteenth transistor T15 may reduce the voltage amplitude of the driving control terminal Q, thereby affecting the normal operation of the scan mode.

请参考图3（b），为当级联的第一开关晶体管T11为两个时第一输入模块1的结构图。该结构是一种分流结构，在控制信号V_CTR为高电平时，第十五晶体管T15处于导通状态，于是在第一脉冲信号V_I1为高电平时，首级第一开关晶体管T11的输入电流通过第十五晶体管T15被旁路分流。即使尾级第一开关晶体管T11被开启，然而其第一极（例如漏极）因为分流的缘故电压较低，所以几乎没有充电电流经过尾级第一开关晶体管T11给驱动控制端Q充电。于是驱动控制端Q因为充电电流不足而维持在较低的水平。在这种分流结构中，第十五晶体管T15的尺寸不需要很大就可以有效地响应控制信号V_CTR，将驱动控制端Q维持在低电平。Please refer to FIG. 3( b ), which is a structural diagram of thefirst input module 1 when there are two cascaded first switching transistors T11 . This structure is a shunt structure. When the control signal V_CTR is at a high level, the fifteenth transistor T15 is in a conduction state, so when the first pulse signal V_I1 is at a high level, the input of the first switching transistor T11 The current is shunted through the fifteenth transistor T15. Even if the tail-stage first switch transistor T11 is turned on, its first electrode (such as the drain) has a lower voltage due to shunting, so almost no charging current passes through the tail-stage first switch transistor T11 to charge the drive control terminal Q. Therefore, the driving control terminal Q is maintained at a lower level due to insufficient charging current. In this shunt structure, the size of the fifteenth transistor T15 does not need to be very large to effectively respond to the control signal V_CTR and maintain the driving control terminal Q at a low level.

综上所述，图3(b)所示意的分流结构相比于图3(a)的分压结构，可能具有如下几项优势：(1)更有效地响应控制信号V_CTR的高电平，将驱动控制端Q稳定于更低电位，起到停止扫描的作用。(2)减少了由于第十五晶体管T15漏电等对于正常扫描功能的副作用。(3)减少了由于泄露电流而可能造成的栅极驱动电路单元级间噪声电压的逐级传递和累积。To sum up, compared with the voltage divider structure shown in Figure 3(a), the shunt structure shown in Figure 3(b) may have the following advantages: (1) It responds more effectively to the high level of the control signal V_CTR , to stabilize the drive control terminal Q at a lower potential to stop scanning. (2) The side effects on the normal scanning function caused by the leakage of the fifteenth transistor T15 are reduced. (3) The stage-by-stage transfer and accumulation of noise voltage between stages of gate drive circuit units that may be caused by leakage current is reduced.

在其它实施例中，级联的第一开关晶体管T11还可以是多个，但是输入路径上串联的晶体管数量更多。这样可能带来的弊端是输入路径上串联电阻太大，这样可能影响驱动控制端Q的充电效果，造成栅极驱动电路单元正常扫描功能的失效。此外，实际上，图3(b)的结构已经能够将自举阶段或者低电平维持阶段通过第一开关晶体管T11的泄漏电流抑制到较小的值，因此在输入路径上增加更多的晶体管反而会增加电路的复杂程度，而且影响正常扫描功能。In other embodiments, there may be multiple cascaded first switching transistors T11, but the number of transistors connected in series on the input path is larger. The possible disadvantage of this is that the series resistance on the input path is too large, which may affect the charging effect of the driving control terminal Q, resulting in failure of the normal scanning function of the gate driving circuit unit. In addition, in fact, the structure of Figure 3(b) has been able to suppress the leakage current through the first switching transistor T11 to a small value during the bootstrap phase or the low-level maintenance phase, so more transistors are added to the input path On the contrary, it will increase the complexity of the circuit and affect the normal scanning function.

因此，本实施例中，级联的第一开关晶体管T11个数为2。同样的，对于级联的第二开关晶体管T14也优选为2个。Therefore, in this embodiment, the number of cascaded first switch transistors T11 is two. Likewise, there are preferably two cascaded second switching transistors T14.

实施例二：Embodiment two:

请参考图4，本实施例公开了一种栅极驱动电路，包括：N个级联的上述栅极驱动电路单元，其中，N为大于1的整数。栅极驱动电路单元布置于显示面板的两侧A-A和B-B。在其它实施例中，也可以将栅极驱动电路单元布置于显示面板的一侧。将栅极驱动电路单元布置于显示面板的两侧，可以使得行线方向的近端和远端之间信号延迟带来的显示效果差别减少，此外，由于近邻的行线之间存在信号的耦合，因此分开之后可以更方便布线，从而减少版图面积，也能够使得显示面板两侧分布均匀，带来一定的美观效果。因此，本实施例优选地将栅极驱动电路单元布置于显示面板的两侧，一种优选的方式是：将奇数级栅极驱动电路单元布置在显示面板的一侧，偶数级的布置在显示面板的另一侧。Referring to FIG. 4 , this embodiment discloses a gate drive circuit, including: N cascaded gate drive circuit units, wherein N is an integer greater than 1. The gate driving circuit units are arranged on two sides A-A and B-B of the display panel. In other embodiments, the gate driving circuit unit can also be arranged on one side of the display panel. Arranging the gate drive circuit units on both sides of the display panel can reduce the difference in display effect caused by the signal delay between the near end and the far end of the row line direction. In addition, due to the coupling of signals between adjacent row lines , so that the wiring can be more convenient after separation, thereby reducing the layout area, and can also make the two sides of the display panel evenly distributed, bringing a certain aesthetic effect. Therefore, in this embodiment, it is preferable to arrange the gate drive circuit units on both sides of the display panel. A preferred method is to arrange the odd-numbered gate drive circuit units on one side of the display panel, and arrange the even-numbered gate drive circuit units on the display panel. the other side of the panel.

四路时钟信号线（CLK1、CLK2、CLK3、CLK4），用于分别向栅极驱动电路单元传输时钟信号（V_A、V_B、V_C和V_D），在正向扫描模式下，第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3和第四时钟信号线CLK4的时钟依次晚一个相位；在反向扫描模式下，第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3和第四时钟信号线CLK4的时钟依次早一个相位，其中，一个相位为T/4，T为时钟信号的周期。第4k+1级栅极驱动电路单元的第一时钟信号V_A、第二时钟信号V_B、第三时钟信号V_C和第四时钟信号V_D分别由第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3和第四时钟信号线CLK4提供；第4k+2级栅极驱动电路单元的第一时钟信号V_A、第二时钟信号V_B、第三时钟信号V_C和第四时钟信号V_D分别由第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4和第一时钟信号线CLK1提供；第4k+3级栅极驱动电路单元的第一时钟信号V_A、第二时钟信号V_B、第三时钟信号V_C和第四时钟信号V_D分别由第三时钟信号线CLK3、第四时钟信号线CLK4、第一时钟信号线CLK1和第二时钟信号线CLK2提供；第4k级栅极驱动电路单元的第一时钟信号V_A、第二时钟信号V_B、第三时钟信号V_C和第四时钟信号V_D分别由第四时钟信号线CLK4、第一时钟信号线CLK1、第二时钟信号线CLK2和第三时钟信号线CLK3提供，其中k为自然数。Four clock signal lines (CLK1, CLK2, CLK3, CLK4) are used to transmit clock signals (V_A , V_B , V_C and V_D ) to the gate drive circuit unit respectively. In the forward scanning mode, the first The clocks of the clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 are sequentially late by one phase; in the reverse scan mode, the first clock signal line CLK1, the second clock signal line The clocks of the line CLK2 , the third clock signal line CLK3 , and the fourth clock signal line CLK4 are sequentially earlier by one phase, wherein one phase is T/4, and T is the period of the clock signal. The first clock signal V_A , the second clock signal V_B , the third clock signal V_C and the fourth clock signal V_D of the 4k+1-th gate drive circuit unit are respectively transmitted by the first clock signal line CLK1 and the second clock signal line CLK1. The signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 provide; the first clock signal V_A , the second clock signal V_B , and the third clock signal V_C of the 4k+2th stage gate drive circuit unit and the fourth clock signal V_D are respectively provided by the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4 and the first clock signal line CLK1; A clock signal V_A , a second clock signal V_B , a third clock signal V_C and a fourth clock signal V_D are provided by the third clock signal line CLK3 , the fourth clock signal line CLK4 , the first clock signal line CLK1 and the fourth clock signal line respectively. The second clock signal line CLK2 is provided; the first clock signal V_A , the second clock signal V_B , the third clock signal V_C and the fourth clock signal V_D of the 4kth level gate drive circuit unit are respectively provided by the fourth clock signal line CLK4, the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 are provided, wherein k is a natural number.

第一信号启动线STV1和第二信号启动线STV2，第一信号启动线STV1耦合至第一级栅极驱动电路单元的第一信号输入端，用于向第一级栅极驱动电路单元提供第一脉冲信号V_I1；第二信号启动线STV2耦合至第二级栅极驱动电路单元的第一信号输入端，用于向第二级栅极驱动电路单元提供第一脉冲信号V_I1；第i级栅极驱动电路单元的信号输出端分别耦合至第i-2级栅极驱动电路单元的第二信号输入端，和第i+2级栅极驱动电路单元的第一信号输入端，i为大于等于3的整数；第一级栅极驱动电路单元的信号输出端耦合至第三级栅极驱动电路单元的第一信号输入端；第二级栅极驱动电路单元的信号输出端耦合至第四级栅极驱动电路单元的第一信号输入端。各级栅极驱动电路单元的信号输出端还用于提供栅极扫描信号V_Gⁿ，其中，V_Gⁿ是第n级栅极驱动电路单元的栅极扫描信号。The first signal activation line STV1 and the second signal activation line STV2, the first signal activation line STV1 is coupled to the first signal input terminal of the first-level gate drive circuit unit, and is used to provide the first-level gate drive circuit unit with the first A pulse signal V_I1 ; the second signal activation line STV2 is coupled to the first signal input terminal of the second-level gate drive circuit unit, and is used to provide the first pulse signal V_I1 to the second-level gate drive circuit unit; the i The signal output terminals of the level gate drive circuit unit are respectively coupled to the second signal input terminal of the i-2th level gate drive circuit unit, and the first signal input terminal of the i+2th level gate drive circuit unit, where i is An integer greater than or equal to 3; the signal output end of the first-level gate drive circuit unit is coupled to the first signal input end of the third-level gate drive circuit unit; the signal output end of the second-level gate drive circuit unit is coupled to the first The first signal input end of the four-level gate drive circuit unit. The signal output ends of the gate driving circuit units at each level are also used to provide the gate scanning signal V_Gⁿ , wherein V_Gⁿ is the gate scanning signal of the gate driving circuit unit of the nth level.

低电平线l-V_L，低电平线l-V_L耦合至各级栅极驱动电路单元的低电平端，用于向各级栅极驱动电路单元提供低电平信号V_L。The low-level line lV_L is coupled to the low-level terminals of the gate drive circuit units of each level, and is used to provide_the low-level signal V_L to the gate drive circuit units of each level.

控制信号线l-V_CTR，控制信号线l-V_CTR用于向栅极驱动电路传输控制信号V_CTR。The control signal line lV_CTR is used to transmit the control_{signal V CTRto} the gate drive circuit.

请参考图5，为本实施例栅极驱动电路在正向扫描模式下，第1-4级栅极驱动电路单元输出的栅极扫描信号图。与两两重叠的时钟信号对应，相邻的栅极驱动电路的输出信号两两重叠。正向扫描模式时，输出信号的相位先后关系依次是：V_G¹、V_G²、V_G³、V_G⁴；相应的，反向扫描模式时，输出信号的相位先后关系依次是：V_G⁴、V_G³、V_G²、V_G¹。无论正向、或反向扫描模式，位于面板一侧的奇数行信号V_G¹、V_G³是不交叠的；位于面板另一侧的偶数行信号V_G²、V_G⁴也是不交叠的。其余栅极驱动电路单元输出的栅极扫描信号亦可通过类似方法分析得出。Please refer to FIG. 5 , which is a diagram of the gate scan signals output by the gate drive circuit units of stages 1-4 in the forward scan mode of the gate drive circuit of this embodiment. Corresponding to the clock signals overlapping two by two, the output signals of adjacent gate drive circuits overlap by two. In the forward scanning mode, the phase sequence of the output signal is: V_G¹ , V_G² , V_G³ , V_G⁴ ; correspondingly, in the reverse scanning mode, the phase sequence of the output signal is: V_G⁴ , V_G³ , V_G² , V_G¹ . Regardless of the forward or reverse scanning mode, the odd line signals V_G¹ and V_G³ on one side of the panel are non-overlapping; the even line signals V_G² and V_G⁴ on the other side of the panel are also non-overlapping. Stacked. The gate scan signals output by other gate drive circuit units can also be analyzed and obtained by a similar method.

请参考图6，为本实施例栅极驱动电路在反向扫描模式下，扫描阶段和非扫描阶段的第1-4级栅极驱动电路单元输出的栅极扫描信号图。在控制信号V_CTR为低电平时，栅极驱动电路处于扫描阶段，在反向扫描模式下，栅极扫描信号依次输出V_G⁴、V_G³、V_G²、V_G¹；相应的，在正向扫描模式下，栅极扫描信号依次输出V_G¹、V_G²、V_G³、V_G⁴。在控制信号V_CTR为高电平时，栅极驱动电路处于非扫描阶段，各级栅极驱动电路单元输出信号均为低电平。Please refer to FIG. 6 , which is a diagram of gate scanning signals output by the gate driving circuit units of stages 1-4 in the scanning phase and the non-scanning phase in the reverse scanning mode of the gate driving circuit of this embodiment. When the control signal V_CTR is at low level, the gate drive circuit is in the scanning phase. In the reverse scanning mode, the gate scanning signal outputs V_G⁴ , V_G³ , V_G² , and V_G¹ in sequence; correspondingly, In the forward scanning mode, the gate scanning signal outputs V_G¹ , V_G² , V_G³ , and V_G⁴ sequentially. When the control signal V_CTR is at a high level, the gate driving circuit is in a non-scanning phase, and the output signals of the gate driving circuit units at all levels are all at a low level.

实施例三：Embodiment three:

本实施例公开的栅极驱动电路和实施例二不同之处在于，中间级的栅极驱动电路单元采用简化的电路结构。The difference between the gate driving circuit disclosed in this embodiment and the second embodiment is that the gate driving circuit unit of the intermediate stage adopts a simplified circuit structure.

请参考图7，图7所示为第n级栅极驱动电路单元电路结构图，其中n为整数，且2<n<N-1。具体简化的结构在于第一输入模块1和第二输入模块2，其中：Please refer to FIG. 7 . FIG. 7 shows a circuit structure diagram of an nth-level gate driving circuit unit, where n is an integer, and 2<n<N−1. The concrete simplified structure lies in thefirst input module 1 and thesecond input module 2, wherein:

第一输入模块1包括一个第一开关晶体管T11，第一开关晶体管T11的控制极（例如栅极）耦合至第一信号输入端，用于输入第一脉冲信号V_I1；第一极（例如漏极）用于输入第四时钟信号V_D；第二极耦合在驱动控制端Q。Thefirst input module 1 includes a first switch transistor T11, the control electrode (eg gate) of the first switch transistor T11 is coupled to the first signal input terminal for inputting the first pulse signal V_I1 ; the first electrode (eg drain pole) is used to input the fourth clock signal V_D ; the second pole is coupled to the drive control terminal Q.

第二输入模块2包括一个第二开关晶体管T14，第二开关晶体管T14的控制极（例如栅极）耦合至第一信号输入端，用于输入第二脉冲信号V_I2；第一极（例如漏极）用于输入第二时钟信号V_B；第二极耦合在驱动控制端Q。Thesecond input module 2 includes a second switch transistor T14, the control electrode (eg gate) of the second switch transistor T14 is coupled to the first signal input terminal for inputting the second pulse signal V_I2 ; the first electrode (eg drain pole) is used to input the second clock signal V_B ; the second pole is coupled to the drive control terminal Q.

相对于实施例二，本实施例第n级栅极驱动电路单元缩减了级联开关晶体管（T11、T14）的个数，还减少了第十五晶体管T15和第十六晶体管T16，并且，在本实施例中，第n级栅极驱动电路单元不需再输入控制信号V_CTR。本领域普通技术人员应该理解，第n级栅极驱动电路单元的第一信号输入端和第二信号输入端以及其它信号（端）的连接方式与实施例二相同。Compared withEmbodiment 2, the number of cascaded switching transistors (T11, T14) is reduced in the nth-level gate drive circuit unit of this embodiment, and the fifteenth transistor T15 and the sixteenth transistor T16 are also reduced, and, in In this embodiment, the gate driving circuit unit of the nth stage does not need to input the control signal V_CTR . Those of ordinary skill in the art should understand that the connection mode of the first signal input terminal, the second signal input terminal and other signals (terminals) of the nth-level gate drive circuit unit is the same as that of the second embodiment.

采用这种简化的电路结构是基于以下物理事实，根据栅极驱动电路逐级扫描的特点，无论是正向扫描模式还是反向扫描模式，各级栅极驱动电路单元是否工作依附于相邻级栅极驱动电路单元信号输出。决定栅极驱动电路是否开始工作的是首级栅极驱动电路单元或尾级栅极驱动电路单元。因此，对于第n级栅极驱动电路单元可以不必额外增设控制信号V_CTR，第n级栅极驱动电路单元只需等待相邻级栅极驱动电路单元的激励即可启动响应的扫描模式。The use of this simplified circuit structure is based on the following physical facts. According to the characteristics of the gate drive circuit scanning step by step, whether it is in the forward scanning mode or the reverse scanning mode, whether the gate drive circuit units of each level work depends on the adjacent gates. Pole drive circuit unit signal output. It is the first gate drive circuit unit or the tail gate drive circuit unit that determines whether the gate drive circuit starts to work. Therefore, there is no need to add additional control signal V_CTR for the gate driving circuit unit of the nth level, and the gate driving circuit unit of the nth level only needs to wait for the excitation of the gate driving circuit unit of the adjacent level to start the corresponding scanning mode.

实施例四：Embodiment four:

根据实施例三所阐述的物理事实，考虑到决定栅极驱动电路正向/反向扫描模式为首级/尾级栅极驱动电路单元。本实施例公开了另一种简化的栅极驱动电路。According to the physical facts described in the third embodiment, it is considered that the forward/reverse scanning mode of the gate driving circuit is determined as the first-level/tail-level gate driving circuit unit. This embodiment discloses another simplified gate driving circuit.

本实施例公开的栅极驱动电路与上述实施例不同之处在于，首级（第1级和第2级）栅极驱动电路单元采用了简化的电路结构，具体为，采用第一种栅极驱动电路单元结构。The difference between the gate drive circuit disclosed in this embodiment and the above-mentioned embodiments is that the gate drive circuit unit of the first stage (level 1 and level 2) adopts a simplified circuit structure, specifically, the first gate Drive circuit unit structure.

请参考图8，图8所示为第1级和第2级栅极驱动电路单元电路结构图，具体简化的结构在于第二输入模块2，第二输入模块2包括一个第二开关晶体管T14，第二开关晶体管T14的控制极（例如栅极）耦合至第二信号输入端，用于输入第二脉冲信号V_I2；第一极（例如漏极）用于输入第二时钟信号V_B；第二极耦合在驱动控制端Q。相对于上述实施例，本实施例第1级和第2级栅极驱动电路单元缩减了级联第二开关晶体管T14的个数，还减少了第十六晶体管T16，并且，在本实施例中，第1级和第2级栅极驱动电路单元的第二输入模块2不需再输入控制信号V_CTR。本领域普通技术人员应该理解，第1级和第2级栅极驱动电路单元的第一信号输入端和第二信号输入端以及其它信号（端）的连接方式与其它实施例相同。Please refer to FIG. 8. FIG. 8 shows the circuit structure diagram of the first-level and second-level gate drive circuit units. The specific simplified structure lies in thesecond input module 2. Thesecond input module 2 includes a second switching transistor T14. The control electrode (such as the gate) of the second switching transistor T14 is coupled to the second signal input terminal for inputting the second pulse signal V_I2 ; the first electrode (such as the drain) is used for inputting the second clock signal V_B ; The diode is coupled to the drive control terminal Q. Compared with the above-mentioned embodiments, the number of cascaded second switch transistors T14 and the sixteenth transistor T16 are reduced in the first-level and second-level gate drive circuit units of this embodiment, and, in this embodiment In other words, thesecond input module 2 of the first-level and second-level gate drive circuit units does not need to input the control signal V_CTR . Those of ordinary skill in the art should understand that the connection modes of the first signal input terminal and the second signal input terminal and other signals (terminals) of the first-level and second-level gate drive circuit units are the same as those in other embodiments.

在另一种实施例中，与上述实施例不同之处在于，尾级（第N-1级和第N级）栅极驱动电路单元采用了简化的电路结构，具体为，采用第二种栅极驱动电路单元结构。In another embodiment, the difference from the above-mentioned embodiment is that the tail-stage (N-1th and Nth-level) gate drive circuit units adopt a simplified circuit structure, specifically, the second gate Pole drive circuit unit structure.

请参考图9，图9所示为第N-1级和第N级栅极驱动电路单元电路结构图，具体简化的结构在于第一输入模块1，第一输入模块1包括一个第一开关晶体管T11，第一开关晶体管T11的控制极（例如栅极）耦合至第一信号输入端，用于输入第一脉冲信号V_I1；第一极（例如漏极）用于输入第四时钟信号V_D；第二极耦合在驱动控制端Q。相对于上述实施例，本实施例第N-1级和第N级栅极驱动电路单元缩减了级联第一开关晶体管T11的个数，还减少了第十五晶体管T15，并且，在本实施例中，第N-1级和第N级栅极驱动电路单元的第一输入模块2不需再输入控制信号V_CTR。本领域普通技术人员应该理解，第N-1级和第N级栅极驱动电路单元的第一信号输入端和第二信号输入端以及其它信号（端）的连接方式与其它实施例相同。Please refer to FIG. 9. FIG. 9 shows the circuit structure diagram of the N-1th and Nth-level gate drive circuit units. The specific simplified structure lies in thefirst input module 1, and thefirst input module 1 includes a first switching transistor. T11, the control electrode (eg gate) of the first switching transistor T11 is coupled to the first signal input terminal for inputting the first pulse signal V_I1 ; the first electrode (eg drain) is used for inputting the fourth clock signal V_D ; The second pole is coupled to the drive control terminal Q. Compared with the above-mentioned embodiment, the number of cascaded first switching transistors T11 and the fifteenth transistor T15 are reduced in the N-1th and Nth-level gate drive circuit units of this embodiment, and, in this embodiment In this example, thefirst input module 2 of the gate drive circuit unit of the N-1th stage and the Nth stage does not need to input the control signal V_CTR . Those of ordinary skill in the art should understand that the connection modes of the first signal input terminal and the second signal input terminal and other signals (terminals) of the N-1th stage and the Nth stage gate driving circuit unit are the same as those in other embodiments.

本实施例公开的两种简化方式是基于以下依据：The two simplified methods disclosed in this embodiment are based on the following basis:

在正向扫描模式下，起到激励栅极驱动电路开始工作作用的是首级栅极驱动电路单元的第一输入模块1，而后各级只要响应前一级输出脉冲驱动信号V_O即可开启本级栅极驱动电路单元的工作；结束栅极驱动电路工作的是尾级栅极驱动电路单元的第二输入模块2，随着尾级栅极驱动电路单元第二脉冲信号V_I2的输入标志着栅极驱动电路的正向扫描模式结束。In the forward scanning mode, it is thefirst input module 1 of the first stage gate drive circuit unit that acts as an incentive for the gate drive circuit to start working, and then each stage can be turned on as long as it responds to the output pulse drive signal V_O of the previous stage. The work of the gate drive circuit unit of this stage; what ends the work of the gate drive circuit is thesecond input module 2 of the gate drive circuit unit of the tail stage, along with the input sign of the second pulse signal V_I2 of the gate drive circuit unit of the tail stage The forward scan mode of the gate drive circuit ends.

在反向扫描模式下，起到激励栅极驱动电路开始工作作用的是尾级栅极驱动电路单元的第二输入模块2，而后各级只要响应后一级输出脉冲驱动信号V_O即可开启本级栅极驱动电路单元的工作；结束栅极驱动电路工作的是首栅极驱动电路单元的第一输入模块1，随着首级栅极驱动电路单元第一脉冲信号V_I1的输入标志着栅极驱动电路的反向扫描模式结束。In the reverse scanning mode, it is thesecond input module 2 of the tail-stage gate drive circuit unit that acts as an incentive to start the gate drive circuit, and then each stage can be turned on as long as it responds to the output pulse drive signal V_O of the latter stage. The work of the gate drive circuit unit of this stage; thefirst input module 1 of the first gate drive circuit unit is what ends the work of the gate drive circuit unit, and the input of the first pulse signal V_I1 of the gate drive circuit unit of the first stage marks The reverse scan mode of the gate drive circuit ends.

因此，无论是正向扫描模式，还是反向扫描模式，在实际应用过程中，只需对首级栅极驱动电路单元的第一输入模块1和尾级栅极驱动电路单元第二输入模块2输入控制信号V_CTR进行控制即可。Therefore, no matter it is the forward scanning mode or the reverse scanning mode, in the actual application process, only thefirst input module 1 of the first gate driving circuit unit and thesecond input module 2 of the tail gate driving circuit unit need to input The control signal V_CTR can be used for control.

实施例五：Embodiment five:

请参考图10，为本实施例公开的一种显示器结构图。Please refer to FIG. 10 , which is a structural diagram of a display disclosed in this embodiment.

显示面板100，显示面板100包括由多个二维像素构成的二维像素阵列，以及与每个像素相连的第一方向(例如横向)的多条栅极扫描线和第二方向(例如纵向)的多条数据线。像素阵列中的同一行像素均连接到同一条栅极扫描线，而像素阵列中的同一列像素则连接到同一条数据线。显示面板100可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸显示器等。Thedisplay panel 100, thedisplay panel 100 includes a two-dimensional pixel array composed of a plurality of two-dimensional pixels, and a plurality of gate scanning lines in a first direction (for example, horizontal) and a second direction (for example, vertical) connected to each pixel multiple data lines. Pixels in the same row in the pixel array are connected to the same gate scanning line, and pixels in the same column in the pixel array are connected to the same data line. Thedisplay panel 100 may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, etc., and a corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, etc.

栅极驱动电路200，栅极驱动电路200中栅极驱动电路单元的信号输出端耦合到显示面板100中与其对应的栅极扫描线，用于对像素阵列的逐行扫描，栅极驱动电路200可以通过焊接与显示面板100相连或者集成于显示面板100内。该栅极驱动电路200采用上述实施例提供的栅极驱动电路。Thegate drive circuit 200, the signal output end of the gate drive circuit unit in thegate drive circuit 200 is coupled to the corresponding gate scan line in thedisplay panel 100 for progressive scanning of the pixel array, thegate drive circuit 200 It may be connected with thedisplay panel 100 by welding or integrated in thedisplay panel 100 . Thegate driving circuit 200 adopts the gate driving circuit provided by the above-mentioned embodiments.

时序产生电路300，用于产生栅极驱动电路200所需的各种控制信号。Thetiming generating circuit 300 is used for generating various control signals required by thegate driving circuit 200 .

数据驱动电路400，用于产生图像数据信号，并将其输出到显示面板100中与其对应的数据线上，通过数据线传输到对应的像素单元内以实现图像灰度。Thedata driving circuit 400 is used to generate an image data signal, output it to the corresponding data line in thedisplay panel 100, and transmit it to the corresponding pixel unit through the data line to realize image grayscale.

实施例六：Embodiment six:

上述实施例中，第一输入模块1和/或第二输入模块2为本申请的改进之处，其关键点在于，在现有输入模块的基础上多引入了逻辑控制端，从而形成逻辑传输电路。本实施例对该逻辑传输电路单独进行说明，请参考图11，逻辑传输电路结构包括：In the above-mentioned embodiment, thefirst input module 1 and/or thesecond input module 2 are improvements of the present application, and the key point is that more logic control terminals are introduced on the basis of the existing input modules, thereby forming a logic transmission circuit. In this embodiment, the logical transmission circuit is described separately. Please refer to FIG. 11. The structure of the logical transmission circuit includes:

第一逻辑信号输入端，用于输入第一逻辑控制信号V₁。The first logic signal input terminal is used for inputting the first logic control signal V₁ .

第二逻辑信号输入端，用于输入第二逻辑控制信号V₂。The second logic signal input terminal is used for inputting the second logic control signal V₂ .

传输信号输入端，用于输入传输信号V_in。The transmission signal input terminal is used for inputting the transmission signal V_in .

信号跟随端。signal follower.

级联的至少一个开关晶体管T01，级联的至少一个开关晶体管T01耦合在第一逻辑信号输入端和信号跟随端之间，首级开关晶体管T01的第一极（例如漏极）用于输入传输信号，尾级开关晶体管T01的第二极（例如源极）耦合在信号跟随端，各开关晶体管T01的控制极（例如栅极）耦合在第一逻辑信号输入端，用于输入第一逻辑控制信号V₁。在一种具体实施例中，级联的至少一个开关晶体管T01的个数可以为2。Cascaded at least one switching transistor T01, the cascaded at least one switching transistor T01 is coupled between the first logic signal input terminal and the signal follower terminal, the first pole (such as the drain) of the first stage switching transistor T01 is used for input transmission signal, the second pole (such as the source) of the tail-stage switching transistor T01 is coupled to the signal follower terminal, and the control pole (such as the gate) of each switching transistor T01 is coupled to the first logic signal input terminal for inputting the first logic control signal V₁ . In a specific embodiment, the number of at least one switching transistor T01 cascaded may be two.

第一控制晶体管T21，第一控制晶体管T21的控制极（例如栅极）耦合至第二逻辑信号输入端，用于输入第二逻辑控制信号V₂，第一极（例如漏极）耦合至首级开关晶体管T01的第二极（例如源极），第一控制晶体管的第二极（例如源极）用于耦合至低电平端，用于输入低电平电压V_L。The first control transistor T21, the control electrode (eg gate) of the first control transistor T21 is coupled to the second logic signal input terminal for inputting the second logic control signal V₂ , the first electrode (eg drain) is coupled to the first The second pole (such as the source) of the stage switching transistor T01 and the second pole (such as the source) of the first control transistor are used to be coupled to the low-level terminal for inputting the low-level voltage V_L .

第一控制晶体管T21响应第二逻辑控制信号V₂断开时：当第一逻辑控制信号V₁为有效电平时，级联的开关晶体管T01导通，传输信号V_in施加到信号跟随端，即信号跟随端的电位V_Q跟随传输信号的变化而变化。第一控制晶体管T21响应第二逻辑控制信号V₂导通时，将首级开关晶体管T01的第二极（例如源极）耦合至低电平端。When the first control transistor T21 is turned off in response to the second logic control signal_V2 : when the first logic control signal_V1 is at an active level, the cascaded switch transistor T01 is turned on, and the transmission signal V_in is applied to the signal follower end, that is The potential V_Q of the signal following terminal changes with the change of the transmission signal. When the first control transistor T21 is turned on in response to the second logic control signal_V2 , it couples the second pole (for example, the source) of the primary switch transistor T01 to the low level terminal.

在一种具体实施例中，当第一控制晶体管T21为N沟道类型晶体管时，当第二逻辑控制信号V₂为高电平时，第一控制晶体管T21导通；当第二逻辑控制信号V₂为低电平时，第一控制晶体管T21断开。在其它实施例中，第一控制晶体管T21也可以选择其它类型的晶体管，对应的，第二逻辑控制信号V₂的逻辑控制关系也会随着发生响应的改变。进一步，在另一种实施例中，还可以在第一控制晶体管T21的控制极（例如栅极）增加逻辑非门，从而实现逻辑非运算。In a specific embodiment, when the first control transistor T21 is an N-channel type transistor, when the second logic control signal_V2 is at a high level, the first control transistor T21 is turned on; when the second logic control signal V When₂ is at low level, the first control transistor T21 is turned off. In other embodiments, the first control transistor T21 may also select other types of transistors, and correspondingly, the logic control relationship of the second logic control signal_V2 will also change accordingly. Further, in another embodiment, a logic NOT gate may also be added to the control electrode (eg, gate) of the first control transistor T21 , so as to realize a logic NOT operation.

在一种具体实施例中，当级联的开关晶体管T01为N沟道类型晶体管时，第一逻辑控制信号V₁的有效电平为高电平，同样地，在其它实施例中，级联的开关晶体管T01也可以选择其它类型的晶体管，对应的，第一逻辑控制信号V₁的有效电平也会随着发生响应的改变。In a specific embodiment, when the cascaded switching transistor T01 is an N-channel type transistor, the active level of the first logic control signal_V1 is a high level. Similarly, in other embodiments, the cascaded The switch transistor T01 can also select other types of transistors, correspondingly, the active level of the first logic control signal_V1 will also change accordingly.

采用本实施例的逻辑传输电路，可以实现逻辑运算，如多输入逻辑与、多输入逻辑或、逻辑非门等，并且，对晶体管的沟道宽长比依赖性小，输出高电平或者低电平幅度损失小，电路结构简单。Using the logic transmission circuit of this embodiment, logic operations can be realized, such as multi-input logic and, multi-input logic or, logic NOT gate, etc., and the dependence on the channel width-to-length ratio of the transistor is small, and the output high level or low level The level amplitude loss is small, and the circuit structure is simple.

本实施例逻辑传输电路除了在栅极驱动电路中的应用，还可应用于其他电路中，如图12、13所示为本实施例逻辑传输电路的其他应用。In addition to the application in the gate drive circuit, the logic transmission circuit of this embodiment can also be applied to other circuits, as shown in FIGS. 12 and 13 are other applications of the logic transmission circuit of this embodiment.

请参考图12，逻辑传输电路还包括第二控制晶体管T22，具体为：第二控制晶体管T22的第一极（例如漏极）耦合至信号跟随端，第二极（例如源极）用于耦合至低电平端，控制极（例如栅极）用于输入第一逻辑控制信号的非信号Please refer to FIG. 12 , the logic transmission circuit further includes a second control transistor T22, specifically: the first pole (such as the drain) of the second control transistor T22 is coupled to the signal follower terminal, and the second pole (such as the source) is used for coupling To the low level terminal, the control electrode (such as the gate) is used to input the non-signal of the first logic control signal

在本实施例中，当第一逻辑控制信号V₁的有效电平为高电平；第一控制晶体管T21为N沟道类型的晶体管，第二逻辑控制信号V₂的有效电平为高电平，在第二逻辑控制信号V₂输入至第一控制晶体管T21的控制极（例如栅极）之前，还作非运算。在其它实施例中，第一控制晶体管T21也可以是P沟道类型的晶体管，此时，第二逻辑控制信号V₂输入至第一控制晶体管T21的控制极（例如栅极）之前勿需作非运算。In this embodiment, when the active level of the first logic control signal_V1 is high level; the first control transistor T21 is an N-channel type transistor, the active level of the second logic control signal_V2 is high level level, before the second logic control signal_V2 is input to the control electrode (eg, gate) of the first control transistor T21, a NOT operation is also performed. In other embodiments, the first control transistor T21 may also be a P-channel type transistor. At this time, no operation is required before the second logic control signal_V2 is input to the control electrode (eg gate) of the first control transistor T21. NOT operation.

当第一逻辑控制信号V₁和第二逻辑控制信号V₂同时为有效电平时，级联的开关晶体管T01导通，第一控制晶体管T21和第二控制晶体管T22断开，将传输信号V_in施加到信号跟随端，即信号跟随端的电位V_Q跟随传输信号V_in的变化而变化，譬如，当V_in为高电平时，V_Q为高电平，反之，V_Q为低电平。When the first logic control signal_V1 and the second logic control signal_V2 are at the active level at the same time, the cascaded switch transistor T01 is turned on, the first control transistor T21 and the second control transistor T22 are turned off, and the transmission signal V_in Applied to the signal follower terminal, that is, the potential V_Q of the signal follower terminal changes with the change of the transmission signal V_in , for example, when V_in is at high level, V_Q is at high level, otherwise, V_Q is at low level.

当第一逻辑控制信号V₁为无效电平时，第二控制晶体管T22导通将信号跟随端耦合至低电平端，此时，信号跟随端的电位V_Q保持低电平V_L。When the first logic control signal V₁ is at an inactive level, the second control transistor T22 is turned on to couple the signal following terminal to the low level terminal, and at this time, the potential V_Q of the signal following terminal maintains a low level V_L .

当第二逻辑控制信号V₂为无效电平时，第一控制晶体管T21导通将首级开关晶体管T01的第二极（例如源极）耦合至低电平端。When the second logic control signal V₂ is at an inactive level, the first control transistor T21 is turned on to couple the second pole (for example, the source) of the primary switching transistor T01 to the low level terminal.

采用本实施例的电路结构，可以实现第一逻辑控制信号V₁和第二逻辑控制信号V₂的逻辑与运算，即只有当第一逻辑控制信号V₁和第二逻辑控制信号V₂同时为有效电平时，才将传输信号V_in施加到信号跟随端。With the circuit structure of this embodiment, the logical AND operation of the first logic control signal_V1 and the second logic control signal_V2 can be realized, that is, only when the first logic control signal_V1 and the second logic control signal_V2 are The transmission signal V_in is applied to the signal follower only when it is at an effective level.

请参考图13，公开了一种采用图11的电路实现的逻辑异或运算的电路，包括第一子模块81和第二子模块82，两个子模块均采用图13所示的逻辑传输电路。Please refer to FIG. 13 , which discloses a logic XOR operation circuit implemented by the circuit in FIG. 11 , including a first sub-module 81 and a second sub-module 82 , both of which use the logic transmission circuit shown in FIG. 13 .

其中，两个子模块的传输信号输入端并接，用于输入传输信号V_in；两个子模块的信号跟随端并接，用于跟随传输信号；第一子模块81和第二子模块82的第一逻辑信号输入端输入的逻辑控制信号相反，如第一子模块81的第一逻辑信号输入端输入

第二子模块82的第一逻辑信号输入端输入V₁；第一子模块81和第二子模块82的第二逻辑信号输入端输入的逻辑控制信号相反，如第一子模块81的第二逻辑信号输入端输入

第二子模块82的第二逻辑信号输入端输入V₂。Wherein, the transmission signal input terminals of the two sub-modules are connected in parallel for inputting the transmission signal V_in ; the signal following terminals of the two sub-modules are connected in parallel for following the transmission signal; the first sub-module 81 and the second sub-module 82 The logic control signal input by a logic signal input terminal is opposite, such as the input of the first logic signal input terminal of the first sub-module 81

The first logic signal input terminal of the second submodule 82 inputs_V1 ; the logic control signal input by the second logic signal input terminal of the first submodule 81 and the second submodule 82 is opposite, as the second logic signal input of the first submodule 81 Logic signal input input

The second logic signal input terminal of the second sub-module 82 inputs V₂ .

通过该电路，实现了逻辑异或运算的逻辑传输电路：Through this circuit, the logical transmission circuit of logical XOR operation is realized:

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>Q</span>Q</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>in</span>in</span>}}<span><span>(</span>(</span>{\mathrm{<span><span>V</span><figure-callout\; label="V"\; filenames="HDA0000468267620000051.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span><span>1</span>1</span>}}<span><span>\&CirclePlus;</span>\&CirclePlus;</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>2</span>2</span>}}<span><span>)</span>)</span>$

其中，

为异或运算，即in,

is an XOR operation, that is,

${\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>Q</span>Q</span>}}<span><span>=</span>=</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>in</span>in</span>}}<span><span>(</span>(</span>{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>1</span>1</span>}}\stackrel{<span><span>\&OverBar;</span>\&OverBar;</span>}{{\mathrm{<span><span>V</span><figure-callout\; label="V"\; filenames="HDA0000468267620000011.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span><span>2</span>2</span>}}}<span><span>+</span>+</span>\stackrel{<span><span>\&OverBar;</span>\&OverBar;</span>}{{\mathrm{<span><span>V</span><figure-callout\; label="V"\; filenames="HDA0000468267620000051.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span><span>1</span>1</span>}}}{\mathrm{<span><span>V</span>V</span>}}_{\mathrm{<span><span>2</span>2</span>}}<span><span>)</span>)</span>$

上式表明，当V₁和V₂的电平相同时，例如同为高电平或同为低电平时，V_Q为低电平；The above formula shows that when the levels of V₁ and V₂ are the same, for example, when both are high or both are low, V_Q is low;

当V₁和V₂的电平不同时，V_Q跟随V_in的变化而变化。When the levels of V₁ and V₂ are different, V_Q changes with the change of V_in .

本实施例采用简单的分流式压控电路结构实现异或逻辑，克服了基于反相器逻辑的许多缺点：例如对晶体管的沟道宽长比依赖性大、输出高电平或者低电平幅度损失大等。This embodiment adopts a simple shunt-type voltage control circuit structure to realize XOR logic, which overcomes many shortcomings based on inverter logic: for example, it has a large dependence on the channel width-to-length ratio of transistors, and outputs high or low level amplitudes. Big loss etc.

以上内容是结合具体的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换。The above content is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. Those of ordinary skill in the technical field to which the present invention belongs can also make some simple deduction or replacement without departing from the concept of the present invention.

Claims (10)

Translated fromChinese

1.一种栅极驱动电路单元，其特征在于，包括：1. A gate drive circuit unit, characterized in that, comprising:第一信号输入端，用于输入第一脉冲信号（V_I1）；The first signal input terminal is used for inputting the first pulse signal (V_I1 );第二信号输入端，用于输入第二脉冲信号（V_I2）；The second signal input terminal is used for inputting the second pulse signal (V_I2 );第一时钟信号输入端，用于输入第一时钟信号（V_A）；The first clock signal input terminal is used for inputting the first clock signal (V_A );信号输出端，用于输出脉冲驱动信号（V_O）；The signal output terminal is used to output the pulse driving signal (V_O );驱动模块（3），所述驱动模块（3）耦合在所述第一时钟信号输入端和所述信号输出端之间，在其驱动控制端（Q）获得驱动电压后，将第一时钟信号（V_A）传送到信号输出端，当所述第一时钟信号（V_A）为高电平时，驱动模块（3）对信号输出端上拉充电；当第一时钟信号（V_A）为低电平时，驱动模块（3）对信号输出端（V_O）下拉放电；A driving module (3), the driving module (3) is coupled between the first clock signal input terminal and the signal output terminal, and after its drive control terminal (Q) obtains a driving voltage, the first clock signal (V_A ) is transmitted to the signal output terminal, when the first clock signal (_VA ) is high level, the driving module (3) pulls up the signal output terminal to charge; when the first clock signal (_VA ) is low level, the drive module (3) pulls down and discharges the signal output terminal (V_O );低电平维持模块（5），所述低电平维持模块（5）耦合在信号输出端和低电平端之间；所述低电平维持模块（5）响应第一时钟信号（V_A）的高电平信号或第三时钟信号（V_C）的高电平信号将信号输出端耦合至低电平端，维持信号输出端低电平电位；A low-level maintenance module (5), the low-level maintenance module (5) is coupled between the signal output terminal and the low-level terminal; the low-level maintenance module (5) responds to the first clock signal (V_A ) The high-level signal of the third clock signal (V C ) or the high-level signal of the third clock signal (V_C ) couples the signal output terminal to the low-level terminal to maintain the low-level potential of the signal output terminal;第二输入模块（2），所述第二输入模块（2）包括级联的至少一个第二开关晶体管（T14），所述级联的至少一个第二开关晶体管（T14）耦合在所述第二信号输入端和所述驱动控制端（Q）之间，首级第二开关晶体管（T14）的第一极用于输入第二时钟信号（V_B），尾级第二开关晶体管（T14）的第二极耦合在驱动控制端（Q），各第二开关晶体管（T14）的控制极耦合在第二信号输入端，用于输入第二脉冲信号（V_I2）；在反向扫描模式下，所述第二输入模块（2）响应第二脉冲信号（V_I2）和第二时钟信号（V_B）的高电平交叠期信号对所述驱动控制端（Q）充电；在正向扫描模式下，第二脉冲信号（V_I2）和第二时钟信号（V_B）分别为高电平和低电平时，所述第二输入模块（2）对所述驱动控制端（Q）放电；The second input module (2), the second input module (2) includes at least one second switch transistor (T14) in cascade, and the at least one second switch transistor (T14) in cascade is coupled to the first switch transistor (T14) Between the second signal input terminal and the drive control terminal (Q), the first pole of the second switch transistor (T14) of the first stage is used to input the second clock signal (V_B ), and the second switch transistor (T14) of the tail stage The second pole of each second switching transistor (T14) is coupled to the drive control terminal (Q), and the control poles of each second switching transistor (T14) are coupled to the second signal input terminal for inputting the second pulse signal (V_I2 ); in the reverse scan mode , the second input module (2) charges the drive control terminal (Q) in response to the high-level overlap period signal of the second pulse signal (V_I2 ) and the second clock signal (V_B ); In scan mode, when the second pulse signal (V_I2 ) and the second clock signal (V_B ) are at high level and low level respectively, the second input module (2) discharges the driving control terminal (Q);第一输入模块（1），所述第一输入模块（1）包括级联的至少一个第一开关晶体管（T11），所述级联的至少一个第一开关晶体管（T11）耦合在所述第一信号输入端和所述驱动控制端（Q）之间，首级第一开关晶体管（T11）的第一极用于输入第四时钟信号（V_D），尾级第一开关晶体管（T11）的第二极耦合在驱动控制端（Q），各第一开关晶体管（T11）的控制极耦合在第一信号输入端，用于输入第一脉冲信号（V_I1）；在正向扫描模式下，所述第一输入模块（1）响应第一脉冲信号（V_I1）和第四时钟信号（V_D）的高电平交叠期信号对所述驱动控制端（Q）充电；在反向扫描模式下，第一脉冲信号（V_I1）和第四时钟信号（V_D）分别为高电平和低电平时，所述第一输入模块（1）对所述驱动控制端（Q）放电；The first input module (1), the first input module (1) includes at least one first switch transistor (T11) in cascade, and the at least one first switch transistor (T11) in cascade is coupled to the first switch transistor (T11) Between a signal input terminal and the drive control terminal (Q), the first pole of the first switching transistor (T11) of the first stage is used to input the fourth clock signal (V_D ), and the first switching transistor (T11) of the tail stage The second pole of each first switch transistor (T11) is coupled to the drive control terminal (Q), and the control poles of each first switching transistor (T11) are coupled to the first signal input terminal for inputting the first pulse signal (V_I1 ); in the forward scanning mode , the first input module (1) charges the drive control terminal (Q) in response to the high-level overlapping period signal of the first pulse signal (V_I1 ) and the fourth clock signal (V_D ); In scan mode, when the first pulse signal (V_I1 ) and the fourth clock signal (V_D ) are at high level and low level respectively, the first input module (1) discharges the driving control terminal (Q);所述第一输入模块（1）还包括第十五晶体管（T15），所述第十五晶体管（T15）的控制极用于输入控制信号（V_CTR），第一极耦合至首级第一开关晶体管（T11）的第二极，第二极耦合至所述低电平端；所述第十五晶体管（T15）在控制信号（V_CTR）高电平信号控制下将首级第一开关晶体管（T11）的第二极耦合至低电平端，在控制信号（V_CTR）低电平信号控制下第十五晶体管（T15）断开；The first input module (1) further includes a fifteenth transistor (T15), the control pole of the fifteenth transistor (T15) is used to input the control signal (V_CTR ), and the first pole is coupled to the first The second pole of the switching transistor (T11), the second pole is coupled to the low-level terminal; the fifteenth transistor (_T15 ) turns the first switching transistor The second pole of (T11) is coupled to the low-level terminal, and the fifteenth transistor (T15) is disconnected under the control of the low-level signal of the control signal (V_CTR );第一时钟信号（V_A）与第三时钟信号（V_C）互补。The first clock signal (_VA ) is complementary to the third clock signal (_VC ).2.一种栅极驱动电路单元，其特征在于，包括：2. A gate drive circuit unit, characterized in that it comprises:第一信号输入端，用于输入第一脉冲信号（V_I1）；The first signal input terminal is used for inputting the first pulse signal (V_I1 );第二信号输入端，用于输入第二脉冲信号（V_I2）；The second signal input terminal is used for inputting the second pulse signal (V_I2 );第一时钟信号输入端，用于输入第一时钟信号（V_A）；The first clock signal input terminal is used for inputting the first clock signal (V_A );信号输出端，用于输出脉冲驱动信号（V_O）；The signal output terminal is used to output the pulse driving signal (V_O );驱动模块（3），所述驱动模块（3）耦合在所述第一时钟信号输入端和所述信号输出端之间，在其驱动控制端（Q）获得驱动电压后，将第一时钟信号（V_A）传送到信号输出端，当所述第一时钟信号（V_A）为高电平时，驱动模块（3）对信号输出端上拉充电；当第一时钟信号（V_A）为低电平时，驱动模块（3）对信号输出端（V_O）下拉放电；A driving module (3), the driving module (3) is coupled between the first clock signal input terminal and the signal output terminal, and after its drive control terminal (Q) obtains a driving voltage, the first clock signal (V_A ) is transmitted to the signal output terminal, when the first clock signal (_VA ) is high level, the driving module (3) pulls up the signal output terminal to charge; when the first clock signal (_VA ) is low level, the drive module (3) pulls down and discharges the signal output terminal (V_O );低电平维持模块（5），所述低电平维持模块（5）耦合在信号输出端和低电平端之间；所述低电平维持模块（5）响应第一时钟信号（V_A）的高电平信号或第三时钟信号（V_C）的高电平信号将信号输出端耦合至低电平端，维持信号输出端低电平电位；A low-level maintenance module (5), the low-level maintenance module (5) is coupled between the signal output terminal and the low-level terminal; the low-level maintenance module (5) responds to the first clock signal (V_A ) The high-level signal of the third clock signal (V C ) or the high-level signal of the third clock signal (V_C ) couples the signal output terminal to the low-level terminal to maintain the low-level potential of the signal output terminal;第一输入模块（1），所述第一输入模块（1）包括级联的至少一个第一开关晶体管（T11），所述级联的至少一个第一开关晶体管（T11）耦合在所述第一信号输入端和所述驱动控制端（Q）之间，首级第一开关晶体管（T11）的第一极用于输入第四时钟信号（V_D），尾级第一开关晶体管（T11）的第二极耦合在驱动控制端（Q），各第一开关晶体管（T11）的控制极耦合在第一信号输入端，用于输入第一脉冲信号（V_I1）；在正向扫描模式下，所述第一输入模块（1）响应第一脉冲信号（V_I1）和第四时钟信号（V_D）的高电平交叠期信号对所述驱动控制端（Q）充电；在反向扫描模式下，第一脉冲信号（V_I1）和第四时钟信号（V_D）分别为高电平和低电平时，所述第一输入模块（1）对所述驱动控制端（Q）放电；The first input module (1), the first input module (1) includes at least one first switch transistor (T11) in cascade, and the at least one first switch transistor (T11) in cascade is coupled to the first switch transistor (T11) Between a signal input terminal and the drive control terminal (Q), the first pole of the first switching transistor (T11) of the first stage is used to input the fourth clock signal (V_D ), and the first switching transistor (T11) of the tail stage The second pole of each first switch transistor (T11) is coupled to the drive control terminal (Q), and the control poles of each first switching transistor (T11) are coupled to the first signal input terminal for inputting the first pulse signal (V_I1 ); in the forward scanning mode , the first input module (1) charges the drive control terminal (Q) in response to the high-level overlapping period signal of the first pulse signal (V_I1 ) and the fourth clock signal (V_D ); In scan mode, when the first pulse signal (V_I1 ) and the fourth clock signal (V_D ) are at high level and low level respectively, the first input module (1) discharges the driving control terminal (Q);第二输入模块（2），所述第二输入模块（2）包括级联的至少一个第二开关晶体管（T14），所述级联的至少一个第二开关晶体管（T14）耦合在所述第二信号输入端和所述驱动控制端（Q）之间，首级第二开关晶体管（T14）的第一极用于输入第二时钟信号（V_B），尾级第二开关晶体管（T14）的第二极耦合在驱动控制端（Q）各第二开关晶体管（T14）的控制极耦合在第二信号输入端，用于输入第二脉冲信号（V_I2）；在反向扫描模式下，所述第二输入模块（2）响应第二脉冲信号（V_I2）和第二时钟信号（V_B）的高电平交叠期信号对所述驱动控制端（Q）充电；在正向扫描模式下，第二脉冲信号（V_I2）和第二时钟信号（V_B）分别为高电平和低电平时，所述第二输入模块（2）对所述驱动控制端（Q）放电；The second input module (2), the second input module (2) includes at least one second switch transistor (T14) in cascade, and the at least one second switch transistor (T14) in cascade is coupled to the first switch transistor (T14) Between the second signal input terminal and the drive control terminal (Q), the first pole of the second switch transistor (T14) of the first stage is used to input the second clock signal (V_B ), and the second switch transistor (T14) of the tail stage The second pole of each second switching transistor (T14) is coupled to the second signal input terminal for inputting the second pulse signal (V_I2 ); in the reverse scan mode, The second input module (2) charges the drive control terminal (Q) in response to the high-level overlapping period signal of the second pulse signal (V_I2 ) and the second clock signal (V_B ); mode, when the second pulse signal (V_I2 ) and the second clock signal (V_B ) are at high level and low level respectively, the second input module (2) discharges the drive control terminal (Q);所述第二输入模块（2）还包括第十六晶体管（T16），所述第十六晶体管（T16）的控制极用于输入控制信号（V_CTR），第一极耦合至首级开关四晶体管（T14）的第二极，第二极耦合至所述低电平端；所述第十六晶体管（T16）在控制信号（V_CTR）高电平信号控制下将首级第二开关晶体管（T14）的第二极耦合至低电平端，在控制信号（V_CTR）低电平信号控制下第十六晶体管（T16）断开；The second input module (2) further includes a sixteenth transistor (T16), the control pole of the sixteenth transistor (T16) is used to input the control signal (V_CTR ), and the first pole is coupled to the primary switch IV The second pole of the transistor (T14) is coupled to the low-level terminal; the sixteenth transistor (_T16 ) turns the first-stage second switch transistor ( The second pole of T14) is coupled to the low-level terminal, and the sixteenth transistor (T16) is disconnected under the control of the low-level signal of the control signal (V_CTR );第一时钟信号（V_A）与第三时钟信号（V_C）互补。The first clock signal (_VA ) is complementary to the third clock signal (_VC ).3.如权利要求1所述的栅极驱动电路单元，其特征在于，所述第二输入模块（2）还包括第十六晶体管（T16），所述第十六晶体管（T16）的控制极用于输入控制信号（V_CTR），第一极耦合至首级第二开关晶体管（T14）的第二极，第二极耦合至所述低电平端；所述第十六晶体管（T16）在控制信号（V_CTR）高电平信号控制下将首级第二开关晶体管（T14）的第二极耦合至低电平端，在控制信号（V_CTR）低电平信号控制下第十六晶体管（T16）断开。3. The gate drive circuit unit according to claim 1, characterized in that, the second input module (2) further comprises a sixteenth transistor (T16), the control electrode of the sixteenth transistor (T16) For inputting a control signal (V_CTR ), the first pole is coupled to the second pole of the first-stage second switching transistor (T14), and the second pole is coupled to the low-level terminal; the sixteenth transistor (T16) is Under the control of the high-level signal of the control signal (V_CTR ), the second pole of the second switch transistor (T14) of the first stage is coupled to the low-level terminal, and under the control of the low-level signal of the control signal (V_CTR ), the sixteenth transistor ( T16) disconnected.4.如权利要求1至3任意一项所述的栅极驱动电路单元，其特征在于，所述第一输入模块（1）级联的第一开关晶体管（T11）的个数为2。4. The gate drive circuit unit according to any one of claims 1 to 3, characterized in that, the number of first switch transistors (T11) cascaded in the first input module (1) is two.5.如权利要求1至3任意一项所述的栅极驱动电路单元，其特征在于，所述第二输入模块（2）级联的第二开关晶体管（T14）的个数为2。5. The gate drive circuit unit according to any one of claims 1 to 3, characterized in that, the number of second switching transistors (T14) cascaded in the second input module (2) is two.6.如权利要求1至3任意一项所述的栅极驱动电路单元，其特征在于，所述第一脉冲信号（V_I1）和所述第二脉冲信号（V_I2）间隔一个时钟信号周期；第二时钟信号（V_B）与第四时钟信号（V_D）互补；6. The gate drive circuit unit according to any one of claims 1 to 3, characterized in that, the first pulse signal (V_I1 ) and the second pulse signal (V_I2 ) are separated by one clock signal cycle ; The second clock signal (V_B ) is complementary to the fourth clock signal (V_D );在正向扫描模式下，第四时钟信号（V_D）滞后于第一脉冲信号（V_I1）一个相位，第一时钟信号（V_A）滞后于第四时钟信号（V_D）一个相位；In the forward scan mode, the fourth clock signal (V_D ) lags behind the first pulse signal (V_I1 ) by one phase, and the first clock signal (_VA ) lags behind the fourth clock signal (V_D ) by one phase;在反向扫描模式下，第二时钟信号（V_B）滞后于第二脉冲信号（V_I2）一个相位，第四时钟信号（V_D）滞后于第一时钟信号（V_A）一个相位；In the reverse scanning mode, the second clock signal (V_B ) lags behind the second pulse signal (V_I2 ) by one phase, and the fourth clock signal (V_D ) lags behind the first clock signal (_VA ) by one phase;所述一个相位为T/4，所述T为时钟信号的周期。The one phase is T/4, and the T is a period of the clock signal.7.一种栅极驱动电路，包括：N个级联的栅极驱动电路单元，所述N为大于1的整数；其特征在于，首级采用如权利要求1或3所述的栅极驱动电路单元；尾级采用如权利要求2所述的栅极驱动电路单元。7. A gate drive circuit, comprising: N cascaded gate drive circuit units, where N is an integer greater than 1; it is characterized in that the first stage adopts the gate drive circuit according to claim 1 or 3 The circuit unit; the tail stage adopts the gate drive circuit unit as claimed in claim 2.8.一种显示器，其特征在于，包括：8. A display, characterized in that it comprises:显示面板（100），所述显示面板上制作有第一方向的栅极线和第二方向的数据线；A display panel (100), where gate lines in a first direction and data lines in a second direction are formed on the display panel;如权利要求7所述的栅极驱动电路（200），栅极驱动电路（200）中栅极驱动单元的信号输出端耦合到与其对应的栅极线；The gate drive circuit (200) according to claim 7, wherein the signal output terminal of the gate drive unit in the gate drive circuit (200) is coupled to the corresponding gate line;时序产生电路（300），用于产生栅极驱动电路（200）所需的各种控制信号；A timing generation circuit (300), used for generating various control signals required by the gate drive circuit (200);数据驱动电路(400)，用于产生图像数据信号，并将其输出到显示面板(100)中与其对应的数据线上。The data driving circuit (400) is used to generate image data signals and output them to corresponding data lines in the display panel (100).9.一种逻辑传输电路，其特征在于，包括：9. A logic transmission circuit, characterized in that, comprising:第一逻辑信号输入端，用于输入第一逻辑控制信号；The first logic signal input terminal is used for inputting a first logic control signal;第二逻辑信号输入端，用于输入第二逻辑控制信号；The second logic signal input terminal is used for inputting a second logic control signal;传输信号输入端，用于输入传输信号；The transmission signal input terminal is used for inputting the transmission signal;信号跟随端；signal follower;级联的至少一个开关晶体管，所述级联的至少一个开关晶体管耦合在所述第一逻辑信号输入端和所述信号跟随端之间，首级开关晶体管的第一极用于输入传输信号，尾级开关晶体管的第二极耦合在信号跟随端，各开关晶体管的控制极耦合在第一逻辑信号输入端，用于输入第一逻辑控制信号；At least one switch transistor in cascade, the at least one switch transistor in cascade is coupled between the first logic signal input terminal and the signal follower terminal, the first pole of the first stage switch transistor is used to input the transmission signal, The second poles of the tail-stage switching transistors are coupled to the signal following end, and the control poles of each switching transistor are coupled to the first logic signal input end for inputting the first logic control signal;第一控制晶体管，所述第一控制晶体管的控制极耦合至第二逻辑信号输入端，用于输入第二逻辑控制信号，第一极耦合至首级开关晶体管的第二极，第一控制晶体管的第二极用于耦合至低电平端，当所述第一控制晶体管响应所述第二逻辑控制信号断开且级联的开关晶体管响应第一逻辑控制信号导通时，将传输信号施加到信号跟随端，当所述第一控制晶体管响应所述第二逻辑控制信号导通时，将首级开关晶体管的第二极耦合至低电平端。The first control transistor, the control pole of the first control transistor is coupled to the second logic signal input terminal for inputting the second logic control signal, the first pole is coupled to the second pole of the first stage switch transistor, the first control transistor The second pole of is used to be coupled to the low level terminal, when the first control transistor is turned off in response to the second logic control signal and the cascaded switch transistor is turned on in response to the first logic control signal, the transmission signal is applied to A signal follower terminal, when the first control transistor is turned on in response to the second logic control signal, couples the second pole of the first stage switch transistor to the low level terminal.10.如权利要求9所述的逻辑传输电路，其特征在于，还包括第二控制晶体管；10. The logic transmission circuit according to claim 9, further comprising a second control transistor;所述第二控制晶体管的第一极耦合至信号跟随端，第二极用于耦合至低电平端，控制极用于输入第一逻辑控制信号的非信号；The first pole of the second control transistor is coupled to the signal follower terminal, the second pole is used to couple to the low-level terminal, and the control pole is used to input the negative signal of the first logic control signal;当第一逻辑控制信号和第二逻辑控制信号同时为有效电平时，级联的开关晶体管导通，第一控制晶体管和第二控制晶体管断开，将传输信号施加到信号跟随端；When the first logic control signal and the second logic control signal are at an active level at the same time, the cascaded switch transistor is turned on, the first control transistor and the second control transistor are turned off, and the transmission signal is applied to the signal follower;当第一逻辑控制信号为无效电平时，第二控制晶体管导通将信号跟随端耦合至低电平端；When the first logic control signal is at an inactive level, the second control transistor is turned on to couple the signal following terminal to a low level terminal;当第二逻辑控制信号为无效电平时，第一控制晶体管导通将首级开关晶体管的第二极耦合至低电平端。When the second logic control signal is at an inactive level, the first control transistor is turned on to couple the second pole of the primary switching transistor to the low level terminal.

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