Embodiment
The operation principle of 1CRM Flyback pfc converter
Fig. 1 is Flyback pfc converter main circuit.
Without loss of generality, definition input ac voltage vinexpression formula be
vin(t)=Vmsinωt (1)
Wherein Vmfor input voltage peak value, ω=2 π flinefor input voltage angular frequency, flinefor input voltage frequency
Voltage after input rectifying is so
vg=Vm|sinωt| (2)
Fig. 2 is the inductive current waveform of a switch periods inner conversion device.In the time of switching tube Q conducting, diode D cut-off, former limit inductance Lpthe voltage at two ends is vg, current i Lpby zero beginning with vg/ Lplinear rising of slope, i solppeak value iLp_pkfor
Wherein tonfor the ON time of Q
When Q turn-offs, diode D conducting, by secondary inductance Lscurrent ilsafterflow, now secondary inductance Lsthe voltage at two ends is Vo, secondary inductance current ilswith Vo/ Lsslope from secondary current peak value ils_pkdecline, ilsdrop to zero time tofffor
Wherein n is the transformer primary secondary turn ratio, Lsfor transformer secondary inductance, ils_pkfor secondary inductance current peak.
Because Flyback converter is operated in CRM pattern, therefore, in the time that the electric current of diode D drops to zero, switching tube Q is open-minded, starts new switch periods.
Can obtain duty ratio d by formula (4) is
d(t)=ton/(ton+toff)=nVo/(nVo+Vm|sinωt|) (5)
By formula (3) and (5), in a switch periods, the mean value i of former limit inductive currentlp_avfor
So, input current iinfor
In a switch periods, the mean value i of secondary currentls_avbe output current iofor:
So, in half power frequency period, output current mean value Iofor
Wherein Tlinefor the input voltage cycle.
By formula (1) and formula (7), can obtain the average value P of input power in half power frequency periodin
Suppose that transducer effciency is 100%, input power equals power output so, i.e. Pin=Po.Can obtain switching tube ON time t by formula (10)on
By formula (7), formula (10) and formula (11) can be in the hope of the expression formula of power factor PF value
By formula (12), in conjunction with 3.1 joint design objectives, power factor PF is with Vm/ nVovariation rule curve as shown in Figure 3.2 reduce the control strategy of output current peak-to-average force ratio
3.1 traditional approach
By formula (8), formula (9) and formula (11), determine under ON time control mode output current instantaneous value iowith mean value Ioratio
In the time of ω t=pi/2, formula (13) is got maximum, and peak-to-average force ratio is
Make Fig. 4 according to formula (14), can find out and adopt while determining ON time control, peak-to-average force ratio is larger.
3.2 become ON time control method
For reducing output current peak-to-average force ratio, can in input current, inject 3 times and 5 subharmonic, establish input current expression formula and be
Wherein
i
1for fundamental voltage amplitude, I
3*that 3 subharmonic amplitudes are based on I
1per unit value, I
5*that 5 subharmonic amplitudes are based on I
1per unit value.
By power-balance, output current instantaneous value io1+3+5(t) be
In half power frequency period, to formula (16) integration, can obtain output current mean value I in half power frequency periodo1+3+5
Can be found out by formula (17), in output current mean value and input current, inject 3 times, 5 subharmonic amounts irrelevant.Guarantee to equate with the output current of determining under ON time control, can obtain
According to formula (6), formula (10) and formula (15), ON time ton1+3+5for
By formula (16) and formula (18), output current with the ratio of its mean value is
After inputcurrent injection 3 times, 5 subharmonic, meet under the prerequisite of PF>=0.9 I3*, I5*must just can make peak-to-average force ratio minimum for particular value, get I3*=0.382, I5*=0.081, now peak-to-average force ratio is 1.40, PF=0.93.
3.3 matchings become ON time control method
ON time shown in formula (19) change function analog circuit realize more difficult, seek below relatively simple function come matching it.Can find out from formula (19), fitting function core is that (ω t) for matching g wherein.
Based on Taylor series
Only retain first derivative item, (ω can approximate expression be t) g
According to formula (15) and formula (16), can obtain
Can be obtained by formula (1) and formula (23), adopt matching to become after ON time control, power factor PF is
Get PF=0.93, can obtain k=-0.78.
According to formula (24), in half power frequency period, output current mean value is
Guarantee to become after ON time control in matching, average output driving current remains unchanged,
By k=-0.78 substitution formula (27), obtain a=3.086.(ideal curve t) of ω and matched curve are as shown in Figure 5 for g.
Can be in the hope of by formula (6), formula (10) and formula (23), after matching, become ON time into
By k=-0.78, a=3.086 substitution formula (24), can obtain the ratio i of output current and its mean valueo*for
To above formula differentiate in half power frequency period, making derivative is zero to ask extreme value, can be in the hope of adopting matching to become after ON time control, and output current peak-to-average force ratio is 1.44.
4 performance comparison
4.1 former limit inductance and switching frequencies
For ease of analyzing, design parameter is as follows: vin=85~265VAC, Po=60W, Vo=24V, n=4.
By formula (4) and formula (11), determine switching frequency f under ON timesfor
Can be obtained by formula (4) and (28), become switching frequency f under ON times' be
Adopt and determine ON time control, input voltage Vmone timing, f in half power frequency periodsconstantly change, when ω t=pi/2, fsminimum.At different input voltage Vmunder, fsminimum value is also different.Adopt and become ON time control, input voltage Vmone timing, f in half power frequency periodsconstantly change, when ω t gets [0, pi/2] interior a certain value, fsminimum.At different input voltage Vmunder, fsminimum value difference, its corresponding ω t is also different.Consider human auditory system frequency range, get fsmin=20kHz, can make the threshold inductance value under different input voltages, as shown in Figure 6.
By the threshold inductance value L under wide input rangepmax=656 μ H and L 'pmax=598 μ H are substitution formula (31) and formula (32) respectively, and the switching frequency that can obtain switching tube in two kinds of situations changes function
Fig. 7 is for being respectively (a) 85V, (b) 175V and (c) excursion of switching frequency under half power frequency period ON time decided at the higher level but not officially announced and the control of change ON time when 265V when input voltage.On the whole, within the scope of 85V~175V, under the control of change ON time, switching tube switching frequency is less; Within the scope of 175V~265V, determine under ON time control switching tube switching frequency less.
4.2 current peaks and effective value
According to formula (3) and formula (11), can be in half power frequency period, determine primary current peak I under ON time controllp_pkwith effective value IlP_rmsbe respectively
In like manner, according to formula (3), formula (23) and formula (28), can be in half power frequency period, primary current peak I under the control of change ON time 'lp_pkwith effective value I'lP_rmsbe respectively
Fig. 8 is that wide region is inputted lower two kinds of control mode primary current peak values and effective value waveform.As can be seen from the figure, than the control of fixing time, adopt and become conducting control, converter primary current peak value is smaller, and effective value is bigger.
The CRM Flyback LED driver of the low output current peak-to-average force ratio of 5 the present invention
In conjunction with Fig. 9, input voltage vgthrough resistance the first resistance R1with the second resistance R2dividing potential drop obtains va=kvgvm| sin ω t|, k herevgit is dividing potential drop coefficient.The 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the first diode D1, the first capacitor C1composition dividing potential drop peak sample circuit, vc=1.28kvgvm, wherein R3/ R4=1.28R1/ R2.Output voltage Vothrough the 9th resistance R9with the tenth resistance R10dividing potential drop is again through the 7th resistance R7, the 8th resistance R8, the 4th operational amplification circuit A4the amplifier of composition obtains vd=kvgnVo, wherein R9/ R10=R1/ R2, R8/ R7=n-1.Vawith vcaccess subtraction circuit, wherein R11=R14, R12=R13, R14/ R13=0.78, be output as vf=kvgvm(1-0.78|sin ω t|).Vawith vdaccess add circuit, wherein R15=R16=R17=R19=2R18, be output as ve=kvg(nVo+ Vm| sin ω t|).Vd, vewith vfaccess the first multiplier, it exports va=[kvgvm(1-0.78|sin ω t|) (nVo+ Vm| sin ω t|)]/nVo.Output current ioobtain error signal v by output current feedback circuiteA, veAwith vaaccess the second multiplier, it exports vc=veAva=[veAkvgvm(1-0.78|sin ω t|) (nVo+ Vm| sin ω t|)]/nVo, by vchand over and cut the ON time that can obtain suc as formula Changing Pattern shown in (30) with sawtooth waveforms.Wherein va, vc, vd, ve, vf, va, vc, vbbe respectively the first dividing potential drop follow circuit 3, the second dividing potential drop peak sample circuit 4, the 3rd dividing potential drop amplifying circuit 5, add circuit 6, subtraction circuit 7, the 1st multiplier the 8, the 2nd multiplier 9, output voltage output current feedback circuit 10.Physical circuit is as follows:
The CRM Flyback LED driver of low output current peak-to-average force ratio of the present invention, comprises main power circuit 1 and control circuit, and described main power circuit 1 comprises input voltage source vin, electromagnetic interface filter, diode rectifier circuit RB, transformer T1, switching tube Qb, diode Db, filter capacitor Co, filter inductance Lowith load LED, wherein input voltage source vinbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and transformer T1the first winding Npdifferent name end connect, transformer T1the first winding Npsame Name of Ends access switching tube Qbdrain electrode, switching tube Qbsource electrode be connected zero point with reference potential, transformer T1the second winding Nzdifferent name end be connected zero point with reference potential, transformer T1tertiary winding Nssame Name of Ends and diode Dbanodic bonding, diode Dbnegative electrode access respectively filter capacitor Coone end and filter inductance Loone end, filter capacitor Coother end access reference potential zero point, filter inductance Lothe other end be connected with the anode tap of load LED, the both end voltage of load LED is output voltage Vo; It is V that described control circuit adopts Changing Patternm(nVo+ Vm| sin ω t|) (1-0.78|sin ω t)/nVothe output signal driving switch pipe Q of ON timebcomprise sawtooth waveforms comparison and switch tube driving circuit 2, the first dividing potential drop follow circuit 3, the second dividing potential drop peak sample circuit 4, the 3rd dividing potential drop amplifying circuit 5, add circuit 6, subtraction circuit 7, the first multiplier 8, the second multiplier 9, output current feedback circuit 10, the wherein output of sawtooth waveforms comparison and switch tube driving circuit 2 and switching tube Qbgate pole connect; The input of the first dividing potential drop follow circuit 3 and input voltage sampled point Vgthe output cathode that is diode rectifier circuit RB connects, and the output terminals A of the first dividing potential drop follow circuit 3 is connected with input of add circuit 6 and an input of subtraction circuit 7 respectively; The input of the second dividing potential drop peak sample circuit 4 and input voltage sampled point Vgthe output cathode that is diode rectifier circuit RB connects, and the second output C of dividing potential drop peak sample circuit 4 and another input of subtraction circuit 7 are connected; The output D of the 3rd dividing potential drop amplifying circuit 5 respectively with another input of add circuit 6 and the 3rd input v of the first multiplier 8zconnect; The second input v of the output E of add circuit 6 and the first multiplier 8yconnect the first input end v of the output F of subtraction circuit 7 and the first multiplier 8xconnect the first input end v of the output of the first multiplier 8 and the second multiplier 9aconnect the output access sawtooth waveforms comparison of the second multiplier 9 and the input of switch tube driving circuit 2, the second input v of the output of output current feedback circuit 10 and the second multiplier 9bconnect.
Described sawtooth waveforms comparison and switchtube driving circuit 2 comprise zero passage detection, rest-set flip-flop, driving, saw-toothed wave generator, the first operational amplifier A1; The input of zero passage detection and transformer T1the second winding Nzsame Name of Ends connect, the output of zero passage detection and the S of rest-set flip-flop end is connected, the R of rest-set flip-flop holds and the first operational amplifier A1output connect, the Q of rest-set flip-flop end is connected with the input driving and the input of saw-toothed wave generator respectively, the output of saw-toothed wave generator and the first operational amplifier A1positive input connect, the output of driving is output and the switching tube Q of sawtooth waveforms comparison and switchtube driving circuit 2bgate pole connect, the output of the second multiplier 9 accesses the first operational amplifier A1reverse input end be the input of sawtooth waveforms comparison and switchtube driving circuit 2.
The first described dividing potentialdrop follow circuit 3 comprises the second operational amplifier A2, the first resistance R1, the second resistance R2; Wherein the first resistance R1one end and input voltage sampled point Vgthe output cathode that is diode rectifier circuit RB connects, the first resistance R1the other end and the second resistance R2one end connects, and the first resistance R1with the second resistance R2common port access the first operational amplifier A2positive input, the second resistance R2the other end be connected zero point with reference potential, the second operational amplifier A2reverse input end be directly connected with output terminals A, form in-phase voltage follower.
The second described dividing potential droppeak sample circuit 4 comprises the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the first diode D1, the first capacitor C1, the 6th resistance R6, the 3rd operational amplifier A3; Wherein the 3rd resistance R3one end and input voltage sampled point Vgthe output cathode that is diode rectifier circuit RB connects, the 3rd resistance R3the other end and the 4th resistance R4one end connects, and the 3rd resistance R3with the 4th resistance R4common port access the 5th resistance R5one end, the 4th resistance R4the other end be connected zero point with reference potential, the 5th resistance R5the other end and the first diode D1after anodal series connection through the first diode D1negative pole access the 3rd operational amplifier A3normal phase input end, the first capacitor C1with the 6th resistance R6one end and the 3rd operational amplifier A after in parallel3normal phase input end be connected, another termination reference potential zero point, the 3rd operational amplifier A3inverting input be directly connected with output C.
The 3rd described dividing potentialdrop amplifying circuit 5 comprises the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, four-operational amplifier A4; Wherein the 7th resistance R7termination reference potential zero point, the 7th resistance R7the other end and the 8th resistance R8one end connect, and the 7th resistance R7with the 8th resistance R8common port access four-operational amplifier A4inverting input, the 8th resistance R8the other end and four-operational amplifier A4output D connect, the 9th resistance R9one end and the output voltage V ofmain power circuit 1oanodal connection, the 9th resistance R9the other end and the tenth resistance R10one end connect, and the 9th resistance R9with the tenth resistance R10common port access four-operational amplifier A4normal phase input end.
Described addcircuit 6 comprises the 15 resistance R15, the 16 resistance R16, the 17 resistance R17, the 18 resistance R18, the 19 resistance R19, the 5th operational amplifier A5; Wherein the 15 resistance R15one end is connected with the output terminals A of the first dividing potentialdrop follow circuit 3, other end access the 5th operational amplifier A5positive input, the 16 resistance R16one end is connected with the 3rd dividing potentialdrop amplifying circuit 5 output D, other end access the 5th operational amplifier A5positive input, the 17 resistance R17one end and the 5th operational amplifier A5positive input connect, other end access reference point position zero point, the 18 resistance R18one end access the 5th operational amplifier A5reverse input end, other end access reference point position zero point, the 19 resistance R19access the 5th operational amplifier A5reverse input end and output E between, the second input v ofadd circuit 6 output E and the first multiplier 8yconnect.
Described subtraction circuit 7 comprises the 11 resistance R11, the 12 resistance R12, the 13 resistance R13, the 14 resistance R14, the 6th operational amplifier A6; Wherein the 11 resistance R11one end is connected with the output terminals A of the first dividing potentialdrop follow circuit 3, and the other end is connected to the 6th operational amplifier A6reverse input end, the 12 resistance R12be connected to the 6th operational amplifier A6reverse input end and output F between, the 13 resistance R13one end is connected to the output C of the second dividing potential droppeak sample circuit 4, the 13 resistance R13other end access the 6th operational amplifier A6positive input, the 14 resistance R14one end access the 6th operational amplifier A6positive input, the 14 resistance R14the other end be connected zero point with reference potential, the 6th operational amplifier A6output be the first input end v that the output F of subtraction circuit 7 accesses the first multiplier 8x.
Described output current feedback circuit 10 comprises the second transformer T2, the second diode D2, the 20 resistance R20, the 21 resistance R21, the second capacitor C2, the 3rd capacitor C3, the 22 resistance R22, the 7th operational amplifier A7; Wherein the second transformer T2former limit Same Name of Ends and the transformer T of main power circuit 11tertiary winding Nsdifferent name end connect, the second transformer T2former limit different name end be connected zero point with reference potential, the second transformer T2secondary Same Name of Ends and the second diode D2anodal connection, the second transformer T2secondary different name end and the 20 resistance R20rear and the second diode D connect2negative pole connects, the 20 resistance R20with the second diode D2common port access the 21 resistance R21one end, the 21 resistance R21the other end and the second capacitor C2one end connect, and the 21 resistance R21with the second capacitor C2common port access the 7th operational amplifier A7inverting input, the second capacitor C2the other end be connected zero point with reference potential, the 22 resistance R22with the 3rd capacitor C3access the 7th operational amplifier A after series connection7reverse input end and output between, the positive input of the 7th operational amplifier A 7 and input voltage reference point Vogconnect the 7th operational amplifier A7output be the second input v that the output of output current feedback circuit 10 accesses the second multiplier 9b.
In sum, the CRM Flyback LED driver of low output current peak-to-average force ratio of the present invention, in the situation that keeping power factor PF value to meet application requirements, adopt and become ON time control and realize and in input current, only contain a certain amount of identical with first-harmonic initial phase three times, quintuple harmonics, the switching tube ON time of driver is changed according to certain rule in a power frequency period, within the scope of whole 85V~265V ac input voltage, output current peak-to-average force ratio is reduced near 1.44, reduce output current peak-to-average force ratio, simultaneously little to other performance impacts.