CN103763215A - Chip array priority mapping method and system - Google Patents

Abstract

The invention relates to the field of network communication and discloses a chip array priority mapping method. Through the method, priority forwarding of control management messages in a virtual switching link is effectively achieved. The method includes the first step of identifying received messages and distinguishing service messages and control messages, the second step of remapping the highest-priority service messages to other priorities, the third step of mapping the priority of the control messages to the highest priority, the fourth step of repackaging message descriptors and identifying the priority of the current messages again, and the fifth step of allowing the virtual switching link to forward the messages according to the new priority. The invention further discloses a chip array priority mapping system. The chip array priority mapping system comprises a message identification module, a message mapping module, a message packaging module and a message switching module. The chip array priority mapping method and system are not restricted to inherent limitation of hardware, and firmware input, manpower cost and time cost are effectively reduced. The chip array priority mapping method and system can be widely suitable for chips with a limit of the array number to establish a virtual switching system.

Description

Chip queue priority mapping method and system

Technical field

The present invention relates to network communication field, relate in particular to chip queue priority mapping method and the system in virtual exchange system design, used.

Background technology

In virtual switch technological system building process, because control and management message (or referred to as the controlling message) kind of virtual switch link transmission is a lot, and relate to the packet sending and receiving of striding equipment application protocol.For guaranteeing the stability of virtual exchange system, must guarantee to control message can reliably be forwarded, conventionally namely make the type message forward by highest-priority queue, otherwise when impacting, service message makes to control after message dropping, can cause concussion or the division of virtual exchange system, affect normal data and forward.When the hardware chip using has number of queues restriction, this problem will certainly exist.As conventional exchange chip, chip queue only has altogether 8, corresponding 8 different priority, and each agreement and data message use have been distributed in 8 queues.

In order to ensure control and management message, can preferentially be forwarded, prior art generally all can only guarantee by using method, and the total number of restriction message can not exceed or approach the bandwidth of virtual switch link.This mode to the stability of system be do not have guaranteed, and because virtual switch technology is to use the resilient channels of switching engine to communicate, in Software for Design, not realizing at present the different Q OS(service quality to resilient channels) value carries out data statistics, when the total number of message exceedes or approach the bandwidth of virtual switch link, will inevitably there is the problem that control and management message is dropped, cause the virtual exchange system in actual application unstable, in the serious situation of the limit, cause virtual exchange system division, affecting Network normally moves.

Summary of the invention

The object of the invention is, a kind of chip queue priority mapping method is provided, effectively solve the control and management message prior forwarding problems in virtual switch link.

The present invention solve the technical problem, and the technical scheme of employing is that chip queue priority mapping method, comprises step:

A, the message of receiving is identified differentiated service message and control message;

B, the service message of limit priority is remapped to other priority;

C, will to control message priority-level mapping be limit priority;

The lay equal stress on priority of the current message of new logo of d, Reseal message descriptor;

E, virtual switch link E-Packet according to new priority.

Concrete, the QOS grade that described priority is message.

More specifically, described QOS grade equates with chip number of queues.

Preferably, steps d is specially, and Reseal message descriptor is also encapsulated into HIGIG protocol headers by the message priority remapping.

Recommend, step b is specially:

B1, non-lowest priority service message is remapped to low one-level priority;

B2, constant to lowest priority service message maintenance priority.

Another object of the present invention is, a kind of chip queue priority mapped system is provided, and comprises message identification module, message mapping block, message package module and message switching module;

Message identification module, identifies the message of receiving, differentiated service message and control message;

Message mapping block, is remapped to other priority by the service message of limit priority; To control message priority-level mapping is limit priority;

Message package module, the lay equal stress on priority of the current message of new logo of Reseal message descriptor;

Message switching module, E-Packets according to new priority.

Concrete, the QOS grade that described priority is message.

More specifically, described QOS grade equates with chip number of queues.

Preferably, described message mapping block, further Reseal message descriptor is also encapsulated into HIGIG protocol headers by the message priority remapping.

Recommend, described message mapping block is further remapped to low one-level priority to non-lowest priority service message; To lowest priority service message, keep priority constant.

The invention has the beneficial effects as follows, be not limited to the inherent limitations of hardware, effectively reduce firmware and drop into and manpower time cost.The present invention is as the basic module of system, and End-Customer end can't perceive, and the chip that can be widely used in number of queues restriction carries out the structure of virtual exchange system.

Accompanying drawing explanation

Fig. 1 is the flow chart of embodiment;

Fig. 2 is system configuration schematic diagram of the present invention.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.

The present invention has utilized message to enter after chip, revises the method that priority remaps, and guarantees that the control message prior of queue forwards, and finally realizes queue compression.

Embodiment

This example is take the exchange chip commonly used as example, the QOS queue one of this chip has 8 queues, virtual switch port also only has 8 QOS queues, be respectively QOS0～7, corresponding 8 QOS grades and 8 priority, with 8 queues of user be overlapping, the control message that does not have independent queue to leave virtual switch for is used, acquiescence QOS queue and internal priority also will participate in the conversion operations of 802.1p, TOS, DSCP.As shown in Figure 1, concrete steps comprise chip queue priority mapping method flow process:

When port, receiving priority is the corresponding limit priority of 7() message after, chip can be identified by the type of message.If control message, hold it in QOS7 queue forwarding, if service message also can enter QOS7 queue according to the original priority of this message, and then the internal mapping table having defined by comparison, by message descriptor of this message Reseal, the priority of describing this service message is low one-level 6, send into 6 queues of virtual switch port-qos, virtual switch port can divest the message descriptor of this message, afterwards the priority 6 after mapping is write to HIGIG protocol headers and encapsulate this message, this message will be according to this priority at virtual switch link repeating.In repeating process, service message compress mode adopts original message priority except QOS0(correspondence lowest priority) the mode of one-level is fallen, be that QOS7 queue messages drops to QOS6, QOS6 queue messages drops to QOS5, by that analogy, until QOS1 queue, QOS0 queue messages priority remains unchanged.Thus by 8 priority mapping to 7 queues of service message, for the reserved limit priority QOS7 queue of control and management message of virtual switch link, the control message that port is received, can be mapped to highest-priority queue or remain on highest-priority queue, finally realizing queue compression.

The bandwidth of supposing this routine virtual switch link is 1G, by pouring into summation, exceedes virtual switch link bandwidth 5% different Q OS value and tests.The QOS value of these two flows is respectively QOS7 and QOS6, and they send respectively and account for bandwidth is 10% and 95% known unicast message flow.Finally check the packet receiving result after virtual switch link forwards.Result is that the message of QOS7 queue still can be received 10% flow, there will not be and substitute.The message of QOS6 queue can be received 90% flow, loses 5% flow, strict guarantee is described the message of high priority preferentially forwarded.When two streams of replacing are respectively QOS1 and QOS0, result is respectively to lose 2.5% flow, and this is because the message of QOS1 and QOS0 is all compressed to QOS0 queue.The queue of checking most critical is QOS7 queue, and by filling, wrap test is the transmission that can not affect the control message of QOS7 queue in QOS6 queue excess load, and now virtual exchange system, in stable state, can not be subject to the impact of excess load.Can find out, this spr chip queue priority mapping method, the platoon ratio being compressed is average, and duty ratio is more balanced, can not produce special impact to the queue of certain priority.If by the service message of limit priority, be fixedly mapped to other priority queries, although program is simpler, may produce larger impact to these other priority queries, be unfavorable for the equilibrium of load.

Chip queue priority mapped system structure of the present invention, referring to Fig. 2, comprises message identification module, message mapping block, message package module and message switching module.

Message identification module, identifies the message of receiving, differentiated service message and control message.

Message mapping block, is remapped to other priority by the service message of limit priority; To control message priority-level mapping is limit priority.Here the QOS grade that priority is message also equates with chip number of queues.

Message mapping block, further Reseal message descriptor is also encapsulated into Higig head by the message priority remapping.Non-lowest priority service message is remapped to low one-level priority; To lowest priority service message, keep priority constant.

Message package module, the lay equal stress on priority of the current message of new logo of Reseal message descriptor.

Message switching module, E-Packets according to new priority.

Claims (10)

1. chip queue priority mapping method, comprises step:

A, the message of receiving is identified differentiated service message and control message;

B, the service message of limit priority is remapped to other priority;

C, will to control message priority-level mapping be limit priority;

The lay equal stress on priority of the current message of new logo of d, Reseal message descriptor;

E, virtual switch link E-Packet according to new priority.

2. chip queue priority mapping method according to claim 1, is characterized in that, the QOS grade that described priority is message.

3. chip queue priority mapping method according to claim 2, is characterized in that, described QOS grade equates with chip number of queues.

4. chip queue priority mapping method according to claim 1, is characterized in that, steps d is specially, and Reseal message descriptor is also encapsulated into HIGIG protocol headers by the message priority remapping.

5. chip queue priority mapping method according to claim 1, is characterized in that, step b is specially:

B1, non-lowest priority service message is remapped to low one-level priority;

B2, constant to lowest priority service message maintenance priority.

6. chip queue priority mapped system, comprises message identification module, message mapping block, message package module and message switching module;

Message identification module, identifies the message of receiving, differentiated service message and control message;

Message mapping block, is remapped to other priority by the service message of limit priority; To control message priority-level mapping is limit priority;

Message package module, the lay equal stress on priority of the current message of new logo of Reseal message descriptor;

Message switching module, E-Packets according to new priority.

7. chip queue priority mapped system according to claim 6, is characterized in that, the QOS grade that described priority is message.

8. chip queue priority mapped system according to claim 7, is characterized in that, described QOS grade equates with chip number of queues.

9. chip queue priority mapped system according to claim 6, is characterized in that, described message mapping block, and further Reseal message descriptor is also encapsulated into HIGIG protocol headers by the message priority remapping.

10. chip queue priority mapped system according to claim 9, is characterized in that, described message mapping block is further remapped to low one-level priority to non-lowest priority service message; To lowest priority service message, keep priority constant.

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