CN103744805B - Cpci bus switching value and analog output module hardware structure and the configurable driving method of sequential under VxWorks - Google Patents

Abstract

Translated fromChinese

VxWorks下CPCI总线开关量与模拟量输出模块硬件架构与时序可配置驱动方法，本发明涉及CPCI总线开关量输出与模拟量输出模块的硬件架构与输出时序可配置驱动方法。本发明是要解决现有的设备驱动程序无法实现开关量输出与模拟量输出在时序上配合的问题。VxWorks操作系统下CPCI总线开关量输出模块：包括CPCI总线，PCI9054接口转换芯片，配置芯片，FPGA可编程逻辑器件，配置供电与输出部分；CPCI总线模拟量输出模块：包括CPCI总线，PCI9054接口转换芯片，配置芯片，FPGA可编程逻辑器件，配置供电，DAC芯片，隔离输出与信号输出接口。本发明应用于计算机程序领域。

The hardware architecture and timing configurable driving method of CPCI bus switch and analog output module under VxWorks, the invention relates to the hardware architecture and output timing configurable driving method of CPCI bus switch output and analog output module. The invention aims to solve the problem that the existing device driver program cannot realize the timing coordination between the switching output and the analog output. CPCI bus switch output module under VxWorks operating system: including CPCI bus, PCI9054 interface conversion chip, configuration chip, FPGA programmable logic device, configuration power supply and output part; CPCI bus analog output module: including CPCI bus, PCI9054 interface conversion chip , configuration chip, FPGA programmable logic device, configuration power supply, DAC chip, isolated output and signal output interface. The invention applies to the field of computer programs.

Description

Translated fromChinese

VxWorks下CPCI总线开关量与模拟量输出模块硬件架构与时序可配置驱动方法Hardware architecture and timing configurable driving method of CPCI bus switch and analog output module under VxWorks

技术领域technical field

本发明涉及CPCI总线开关量输出与模拟量输出模块的硬件架构与输出时序可配置驱动方法，属于计算机程序领域。The invention relates to a hardware structure and a configurable driving method of output timing of a CPCI bus switching quantity output and analog quantity output module, and belongs to the field of computer programs.

背景技术Background technique

VxWorks操作系统下基于CPCI总线的开关量输出设备及模拟量输出设备作为常用的测试模块，已经广泛的应用在自动测试系统中。设备的驱动程序作为应用程序与底层硬件通信的桥梁，应用程序通过设备的驱动程序实现对底层硬件的控制。在某些特定的测试系统应用中，用户根据需要在进行开关量输出的同时，需要模拟量输出在时序上的配合，而现有设备的驱动程序只能实现对开关量模块及模拟量输出模块单独的控制，并不能实现开关量输出与模拟量输出的配合。The switching output device and analog output device based on CPCI bus under the VxWorks operating system are commonly used test modules and have been widely used in automatic test systems. The device driver acts as a bridge between the application program and the underlying hardware, and the application program controls the underlying hardware through the device driver program. In some specific test system applications, the user needs to cooperate with the timing of the analog output while performing the switch output according to the needs, and the driver program of the existing equipment can only realize the switching module and the analog output module. Separate control cannot realize the coordination of switching output and analog output.

发明内容Contents of the invention

本发明是要解决现有的设备驱动程序只能实现对开关量模块及模拟量输出模块单独的控制，无法实现开关量输出与模拟量输出在时序上配合的问题，而提供了VxWorks操作系统下CPCI总线开关量输出与模拟量输出时序可配置驱动方法。The present invention is to solve the problem that the existing device driver can only realize the separate control of the switch module and the analog output module, but cannot realize the timing coordination between the switch output and the analog output, and provides a VxWorks operating system The timing of the CPCI bus switch output and analog output can be configured to drive the method.

VxWorks操作系统下CPCI总线开关量输出模块：包括CPCI总线，PCI9054接口转换芯片，配置芯片，FPGA可编程逻辑器件，配置供电与输出部分；其中，所述输出部分包括达林顿管驱动阵列，回读电路，继电器输出阵列与信号输出接口；CPCI bus switching value output module under VxWorks operating system: including CPCI bus, PCI9054 interface conversion chip, configuration chip, FPGA programmable logic device, configuration power supply and output part; wherein, the output part includes Darlington tube drive array, feedback Read circuit, relay output array and signal output interface;

所述PCI9054接口转换芯片分别连接有CPCI总线、配置芯片与FPGA可编程逻辑器件，所述FPGA可编程逻辑器件另两端分别连有配置供电与输出部分；The PCI9054 interface conversion chip is respectively connected with a CPCI bus, a configuration chip and an FPGA programmable logic device, and the other two ends of the FPGA programmable logic device are respectively connected with a configuration power supply and an output part;

所述FPGA可编程逻辑器件输出端与达林顿管驱动阵列输入端相连，所述达林顿管驱动阵列输出端与继电器输出阵列输入端相连，所述继电器输出阵列输出端一端连有信号输出接口，所述继电器输出阵列输出端另一端与回读电路输入端相连，所述回读电路输出端与FPGA可编程逻辑器件输入端相连；The output end of the FPGA programmable logic device is connected to the input end of the Darlington tube drive array, the output end of the Darlington tube drive array is connected to the input end of the relay output array, and one end of the output end of the relay output array is connected to a signal output Interface, the other end of the output end of the relay output array is connected to the input end of the readback circuit, and the output end of the readback circuit is connected to the input end of the FPGA programmable logic device;

CPCI总线模拟量输出模块：包括CPCI总线，PCI9054接口转换芯片，配置芯片，FPGA可编程逻辑器件，配置供电，DAC芯片，隔离输出与信号输出接口；CPCI bus analog output module: including CPCI bus, PCI9054 interface conversion chip, configuration chip, FPGA programmable logic device, configuration power supply, DAC chip, isolation output and signal output interface;

所述PCI9054接口转换芯片分别连接有CPCI总线、配置芯片与FPGA可编程逻辑器件，所述FPGA可编程逻辑器件另一端连有配置供电，所述FPGA可编程逻辑器件输出端与DAC芯片输入端相连，所述DAC芯片输出端与隔离输出输入端相连，所述隔离输出输出端与信号输出接口相连。The PCI9054 interface conversion chip is respectively connected with a CPCI bus, a configuration chip and an FPGA programmable logic device, the other end of the FPGA programmable logic device is connected with a configuration power supply, and the output end of the FPGA programmable logic device is connected with the input end of the DAC chip , the output end of the DAC chip is connected to the isolation output input end, and the isolation output output end is connected to the signal output interface.

VxWorks操作系统下CPCI总线开关量输出与模拟量输出时序可配置驱动方法按以下步骤实现：Under the VxWorks operating system, the timing configurable driving method of the CPCI bus switch output and analog output is realized according to the following steps:

一、用户根据需要将CPCI总线开关量输出配置信息、所需CPCI总线模拟量输出配置信息与延时输出配置信息写到可配置驱动程序中；1. The user writes the configuration information of the CPCI bus switch output, the required CPCI bus analog output configuration information and the delay output configuration information to the configurable driver according to the needs;

二、可配置驱动程序在已开发好的底层硬件功能函数接口基础上根据步骤一所述用户配置信息重新封装一次驱动接口函数，在应用程序调用驱动接口函数时，根据用户在驱动程序中设定好的电路功能，返回用户所需的电路输出状态数据。2. The configurable driver repackages the driver interface function based on the user configuration information described in step 1 on the basis of the developed underlying hardware function interface. Good circuit function, returns the circuit output status data required by the user.

发明效果：Invention effect:

本发明提出了VxWorks操作系统下CPCI总线开关量输出与模拟量输出时序可配置驱动方法，当用户根据需要在进行开关量输出的同时，需要对应的模拟量输出在时序上的配合时，可配置驱动程序可以实现上述的要求，且灵活性好。The present invention proposes a configurable drive method for the time sequence of the output of the CPCI bus and the output of the analog quantity under the VxWorks operating system. When the user is performing the output of the switch quantity as required, when the timing of the corresponding analog quantity output needs to be coordinated, the configurable The driver program can realize the above requirements with good flexibility.

1）、本发明的CPCI设备可配置驱动程序可以实现开关量输出，模拟量配合输出的要求；1) The configurable driver program of the CPCI device of the present invention can realize the switch output, and the analog output can meet the requirements of output;

2）、本发明的CPCI设备可配置驱动程序可以满足开关量输出与模拟量输出在时序上的要求；2) The configurable driver program of the CPCI device of the present invention can meet the timing requirements of switching output and analog output;

3）、本发明的CPCI设备可配置驱动程序具有独立性与通用性，可应用于其它方法。3) The configurable driver program of the CPCI device of the present invention is independent and versatile, and can be applied to other methods.

附图说明Description of drawings

图1是具体实施方式一中基于CPCI总线的开关量输出模块的硬件架构图；Fig. 1 is the hardware structure figure of the switching value output module based on CPCI bus in the specific embodiment one;

图2是具体实施方式一中基于CPCI总线的模拟量输出模块硬件模块架构图；Fig. 2 is the hardware module architecture diagram of the analog quantity output module based on CPCI bus in the specific embodiment one;

图3是具体实施方式八中可配置驱动程序的流程图。Fig. 3 is a flow chart of the configurable driver in the eighth embodiment.

具体实施方式detailed description

具体实施方式一：本实施方式的VxWorks操作系统下CPCI总线开关量输出模块：包括CPCI总线，PCI9054接口转换芯片，配置芯片，FPGA可编程逻辑器件，配置供电与输出部分；其中，所述输出部分包括达林顿管驱动阵列，回读电路，继电器输出阵列与信号输出接口；Specific embodiment one: CPCI bus switch output module under the VxWorks operating system of the present embodiment: comprise CPCI bus, PCI9054 interface conversion chip, configuration chip, FPGA programmable logic device, configuration power supply and output part; Wherein, described output part Including Darlington tube drive array, readback circuit, relay output array and signal output interface;

所述PCI9054接口转换芯片分别连接有CPCI总线、配置芯片与FPGA可编程逻辑器件，所述FPGA可编程逻辑器件另两端分别连有配置供电与输出部分；The PCI9054 interface conversion chip is respectively connected with a CPCI bus, a configuration chip and an FPGA programmable logic device, and the other two ends of the FPGA programmable logic device are respectively connected with a configuration power supply and an output part;

所述FPGA可编程逻辑器件输出端与达林顿管驱动阵列输入端相连，所述达林顿管驱动阵列输出端与继电器输出阵列输入端相连，所述继电器输出阵列输出端一端连有信号输出接口，所述继电器输出阵列输出端另一端与回读电路输入端相连，所述回读电路输出端与FPGA可编程逻辑器件输入端相连；The output end of the FPGA programmable logic device is connected to the input end of the Darlington tube drive array, the output end of the Darlington tube drive array is connected to the input end of the relay output array, and one end of the output end of the relay output array is connected to a signal output Interface, the other end of the output end of the relay output array is connected to the input end of the readback circuit, and the output end of the readback circuit is connected to the input end of the FPGA programmable logic device;

CPCI总线模拟量输出模块：包括CPCI总线，PCI9054接口转换芯片，配置芯片，FPGA可编程逻辑器件，配置供电，DAC芯片，隔离输出与信号输出接口；CPCI bus analog output module: including CPCI bus, PCI9054 interface conversion chip, configuration chip, FPGA programmable logic device, configuration power supply, DAC chip, isolation output and signal output interface;

所述PCI9054接口转换芯片分别连接有CPCI总线、配置芯片与FPGA可编程逻辑器件，所述FPGA可编程逻辑器件另一端连有配置供电，所述FPGA可编程逻辑器件输出端与DAC芯片输入端相连，所述DAC芯片输出端与隔离输出输入端相连，所述隔离输出输出端与信号输出接口相连。The PCI9054 interface conversion chip is respectively connected with a CPCI bus, a configuration chip and an FPGA programmable logic device, the other end of the FPGA programmable logic device is connected with a configuration power supply, and the output end of the FPGA programmable logic device is connected with the input end of the DAC chip , the output end of the DAC chip is connected to the isolation output input end, and the isolation output output end is connected to the signal output interface.

本实施方式效果：The effect of this implementation mode:

本实施方式提出了VxWorks操作系统下CPCI总线开关量输出与模拟量输出时序可配置驱动方法，当用户根据需要在进行开关量输出的同时，需要对应的模拟量输出在时序上的配合时，可配置驱动程序可以实现上述的要求，且灵活性好。This embodiment proposes a configurable drive method for the timing of the CPCI bus switch output and analog output under the VxWorks operating system. When the user needs to cooperate with the corresponding analog output in timing while performing the switch output, the The above requirements can be realized by configuring the driver program, and the flexibility is good.

1）、本实施方式的CPCI设备可配置驱动程序可以实现开关量输出，模拟量配合输出的要求；1) The configurable driver program of the CPCI device in this embodiment can realize the switching output, and the analog output can meet the output requirements;

2）、本实施方式的CPCI设备可配置驱动程序可以满足开关量输出与模拟量输出在时序上的要求；2) The configurable driver program of the CPCI device in this embodiment can meet the timing requirements of switch output and analog output;

3）、本实施方式的CPCI设备可配置驱动程序具有独立性与通用性，可应用于其它方法。3). The configurable driver program of the CPCI device in this embodiment is independent and versatile, and can be applied to other methods.

具体实施方式二：本实施方式与具体实施方式一不同的是：所述基于CPCI总线开关量输出模块运行在CPCI机箱中，通过CPCI总线和控制计算机进行数据传输；Specific embodiment two: the difference between this embodiment and specific embodiment one is: described based on CPCI bus switch quantity output module runs in CPCI chassis, carries out data transmission by CPCI bus and control computer;

所述CPCI总线通过CPCI总线接口控制电路与硬件功能电路之间相连。The CPCI bus is connected with the hardware function circuit through the CPCI bus interface control circuit.

其它步骤及参数与具体实施方式一相同。Other steps and parameters are the same as in the first embodiment.

具体实施方式三：本实施方式与具体实施方式一或二不同的是：所述输出部分还包括继电器；所述继电器在结构上分为2组，每组继电器为16个，每个继电器均为双刀双掷型，其中一刀实现回读功能，另外一刀的公共端COM、常开触点端NO和常闭触点NC引出到接口，实现32路单端电信号的连接功能。Specific embodiment three: the difference between this embodiment and specific embodiment one or two is that: the output part also includes relays; the relays are structurally divided into two groups, each group of relays is 16, each relay is Double-pole double-throw type, one of which realizes the readback function, and the common terminal COM, normally open contact terminal NO and normally closed contact NC of the other pole are led to the interface to realize the connection function of 32 single-ended electrical signals.

每个继电器与其它继电器触点是相互隔离的，各个继电器是独立的；每组32个继电器由2个16位寄存器控制；由于继电器的控制电流较大，所以需要达林顿阵列来驱动继电器阵列，为每组32个继电器配备32路达林顿驱动；回读电路实现对每组32个继电器状态的回读。Each relay is isolated from other relay contacts, and each relay is independent; each group of 32 relays is controlled by two 16-bit registers; due to the large control current of the relays, a Darlington array is required to drive the relay array , Equipped with 32 Darlington drivers for each group of 32 relays; the readback circuit realizes the readback of the status of each group of 32 relays.

其它步骤及参数与具体实施方式一或二相同。Other steps and parameters are the same as those in Embodiment 1 or Embodiment 2.

具体实施方式四：本实施方式与具体实施方式一至三之一不同的是：所述CPCI总线接口控制电路采用PLX公司的PCI9054接口芯片实现，将CPCI总线转换到本地总线。Specific embodiment four: this embodiment is different from one of specific embodiments one to three in that: the CPCI bus interface control circuit adopts the PCI9054 interface chip of PLX Company to realize, and the CPCI bus is converted to a local bus.

其它步骤及参数与具体实施方式一至三之一相同。Other steps and parameters are the same as those in Embodiments 1 to 3.

具体实施方式五：本实施方式与具体实施方式一至四之一不同的是：所述PCI9054本地总线一侧使用FPGA实现总线接口译码，FPGA可编程逻辑器件实现对开关量输出硬件功能模块的控制。Specific embodiment five: this embodiment is different from one of specific embodiments one to four in that: one side of the PCI9054 local bus uses FPGA to realize bus interface decoding, and the FPGA programmable logic device realizes the control of the switch output hardware function module .

其它步骤及参数与具体实施方式一至四之一相同。Other steps and parameters are the same as in one of the specific embodiments 1 to 4.

具体实施方式六：本实施方式与具体实施方式一至五之一不同的是：所述继电器选用松下公司型号为AGN2004H的继电器。其它步骤及参数与具体实施方式一至五之一相同。Embodiment 6: This embodiment differs from Embodiment 1 to Embodiment 5 in that: the relay uses Panasonic's model AGN2004H. Other steps and parameters are the same as one of the specific embodiments 1 to 5.

具体实施方式七：本实施方式与具体实施方式一至六之一不同的是：所述DAC芯片采用TI公司的DAC8218集成芯片，输出的模拟量经过ISO124隔离芯片隔离输出。其它步骤及参数与具体实施方式一至六之一相同。Embodiment 7: This embodiment is different from Embodiment 1 to Embodiment 6 in that: the DAC chip adopts DAC8218 integrated chip of TI Company, and the output analog quantity is isolated and output by ISO124 isolation chip. Other steps and parameters are the same as one of the specific embodiments 1 to 6.

具体实施方八：VxWorks操作系统下CPCI总线开关量输出与模拟量输出时序可配置驱动方法按以下步骤实现：Specific implementation method eight: the CPCI bus switch output and analog output timing configurable drive method is implemented in the following steps under the VxWorks operating system:

一、用户根据需要将CPCI总线开关量输出配置信息、所需CPCI总线模拟量输出配置信息与延时输出配置信息写到可配置驱动程序中；1. The user writes the configuration information of the CPCI bus switch output, the required CPCI bus analog output configuration information and the delay output configuration information to the configurable driver according to the needs;

二、可配置驱动程序在已开发好的底层硬件功能函数接口基础上根据步骤一所述用户配置信息重新封装一次驱动接口函数，在应用程序调用驱动接口函数时，根据用户在驱动程序中设定好的电路功能，返回用户所需的电路输出状态数据。2. The configurable driver repackages the driver interface function based on the user configuration information described in step 1 on the basis of the developed underlying hardware function interface. Good circuit function, returns the circuit output status data required by the user.

具体实施方式九：本实施方式与具体实施方式八不同的是：所述步骤二中应用程序调用驱动函数具体为：Embodiment 9: The difference between this embodiment and Embodiment 8 is that the application program calls the driving function in the step 2, specifically:

一、首先应用程序调用CPCI总线开关量输出模块写操作驱动接口函数，控制CPCI总线开关量输出通道输出，同时做标记记录硬件控制输出值；1. First, the application calls the CPCI bus switch output module write operation drive interface function, controls the output of the CPCI bus switch output channel, and marks and records the hardware control output value at the same time;

二、然后解析可配置驱动程序，将可配置驱动程序中的CPCI总线开关量输出配置信息、所需CPCI总线模拟量输出配置信息及延时配置信息保存起来；2. Then analyze the configurable driver, and save the CPCI bus switch output configuration information, required CPCI bus analog output configuration information and delay configuration information in the configurable driver;

三、然后将开关量输出标记值和输出配置信息中解析后的开关量输出配置信息比对，如果对比不一致，返回ERROR，结束；如果比对一致，查看在进行所需的模拟量配合输出之前，是否有延时配置信息，如果有延时，则先延时配置的时间；3. Then compare the switch output tag value with the parsed switch output configuration information in the output configuration information. If the comparison is inconsistent, return ERROR and end; if the comparison is consistent, check before performing the required analog output. , whether there is a delay configuration information, if there is a delay, first delay the configured time;

四、然后调用模拟量输出模块的数字量模拟量转换接口，进行相应的模拟量输出。其它步骤及参数与具体实施方式八相同。4. Then call the digital-to-analog conversion interface of the analog output module to perform corresponding analog output. Other steps and parameters are the same as those in Embodiment 8.

Claims (9)

1. The hardware structure of cpci bus output switch parameter and analog output module under 1.VxWorks operating system, it is characterized in that cpci bus switching value output module under vxworks operating system: comprise cpci bus, PCI9054 interface conversion chip, configuring chip, FPGA programmable logic device (PLD), configuration feed circuit and output; Wherein, described output comprises Darlington transistor driving array, read back circuit, relay output array and signal output interface;

   Described PCI9054 interface conversion chip is connected to cpci bus, configuring chip and FPGA programmable logic device (PLD), and the described another two ends of FPGA programmable logic device (PLD) are connected with configuration power supply and output respectively;

   Described FPGA programmable logic device (PLD) output terminal drives array input end to be connected with Darlington transistor, described Darlington transistor drives array output end to be connected with relay output array input end, described relay output array output terminal has signal output interface, another output terminal of described relay output array is connected with read back circuit input end, and described read back circuit output terminal is connected with the read back information input end of FPGA programmable logic device (PLD);

   Cpci bus analog output module: comprise cpci bus, PCI9054 interface conversion chip, configuring chip, FPGA programmable logic device (PLD), configuration power supply, DAC chip, isolation and amplifier and signal output interface;

   Described PCI9054 interface conversion chip is connected to cpci bus, configuring chip and FPGA programmable logic device (PLD), configuration feed circuit are used for powering to described FPGA programmable logic device (PLD), described FPGA programmable logic device (PLD) output terminal is connected with DAC chip input end, described DAC chip output terminal is connected with isolation and amplifier input end, and described isolation and amplifier output terminal is connected with signal output interface.
2. 2. the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system according to claim 1, it is characterized in that described cpci bus switching value output module operates in CPCI cabinet, carry out data transmission by cpci bus and computer for controlling;

   Described cpci bus is by being connected between cpci bus interface control circuit with hardware capability circuit.
3. 3. the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system according to claim 2, is characterized in that described output also comprises relay; Described relay is structurally divided into 2 groups, every group relay is 16, and each relay is dpdt double-pole double-throw (DPDT) type, and wherein a cutter realizes retaking of a year or grade function, common port COM, the normally opened contact end NO of an other cutter and normally closed contact NC are drawn out to interface, realize the linkage function of 32 road single-ended electrical signals.
4. 4. the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system according to claim 3, it is characterized in that described cpci bus interface control circuit adopts the PCI9054 interface chip of PLX company to realize, cpci bus is transformed into local bus.
5. 5. the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system according to claim 4, it is characterized in that described PCI9054 local bus side uses FPGA to realize bus interface decoding, FPGA programmable logic device (PLD) realizes the control that switch amount exports hardware function.
6. 6. the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system according to claim 5, is characterized in that described relay selects PANASONIC model to be the relay of AGN2004H.
7. 7. the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system according to claim 6, it is characterized in that described DAC chip adopts the DAC8218 integrated chip of TI company, the analog quantity of output is through ISO124 isolating chip isolation and amplifier.
8. 8. application rights requires cpci bus output switch parameter and the configurable driving method of analog output sequential under the vxworks operating system of the hardware structure of cpci bus output switch parameter and analog output module under vxworks operating system described in 1, it is characterized in that cpci bus output switch parameter and the configurable driving method of analog output sequential realize according to the following steps under vxworks operating system:

   One, cpci bus output switch parameter configuration information, required cpci bus analog output configuration information and time delay are exported configuration information and write in configurable driver by user as required;

   Two, configurable driver once drives interface function according to user configuration information Reseal described in step one on the bottom hardware functional function interface basis developed, when application call drives interface function, according to the circuit function that user sets in driver, return the circuit output state data needed for user.
9. 9. cpci bus output switch parameter and the configurable driving method of analog output sequential under vxworks operating system according to claim 8, is characterized in that in described step 2, application call drives interface function to be specially:

   One, first application call cpci bus switching value output module write operation drives interface function, controls cpci bus output switch parameter passage and exports, the record hardware controls that simultaneously makes marks output valve;

   Two, then resolve configurable driver, the cpci bus output switch parameter configuration information in configurable driver, required cpci bus analog output configuration information and time delay configuration information are saved;

   Three, then by the output switch parameter configuration information comparison after parsing in output switch parameter mark value and output configuration information, if contrast inconsistent, return ERROR, terminate; If comparison is consistent, checked before carrying out required analog quantity cooperation output, whether have time delay configuration information, if there is time delay, then the time of first time delay configuration;

   Four, then call the digital quantity analog quantity translation interface of analog output module, carry out corresponding analog output.