CN103730430A - Multilayer composite membrane passivation structure of table top high-power semiconductor device and manufacturing technology of multilayer composite membrane passivation structure of table top high-power semiconductor device - Google Patents

Abstract

The invention discloses a multilayer composite membrane passivation structure of a table top high-power semiconductor device. The multilayer composite membrane passivation structure comprises P-type boron junction areas and an N-type phosphorus junction area, the upper end and the lower end of the N-type phosphorus junction area are provided with the P-type phosphorus areas respectively, and an alpha-polycrystalline silicon layer, a semi-insulating polycrystalline silicon thin membrane, a low-temperature heat oxidation layer, a high-temperature Si3N4 thin membrane, a negative charge glass passivation layer and a low-temperature heat oxidation layer are sequentially arranged on the surface of a PN junction of a table top of the table top high-power semiconductor device from inside to outside. A manufacturing technology of the multilayer composite membrane passivation structure of the table top high-power semiconductor device includes the following steps: a, depositing the alpha-polycrystalline silicon, b, depositing semi-insulating polycrystalline silicon, c, depositing the low-temperature heat oxidation layer, d, depositing Si3N4, e, conducting passivation on glass, and f, depositing the low-temperature heat oxidation layer in the outmost layer. The multilayer composite membrane passivation structure and the manufacturing technology have the advantages that the alpha-polycrystalline silicon layer is deposited, so that crystal lattice adaptation can be achieved, damage to crystal lattices of a silicon wafer in a groove can be repaired, leaked currents in the surfaces of junctions are reduced, and the stability and the reliability of the device at the high temperature are improved.

Description

A kind of table top large power semiconductor device multilayer complex films passivating structure and preparation technology thereof

Technical field

The present invention relates to a kind of table top large power semiconductor device multilayer complex films passivating structure, also relate to a kind of preparation technology of table top large power semiconductor device multilayer complex films passivating structure.

Background technology

In order to prevent surface contamination, conventionally all need to be at semiconductor device surface covering protection deielectric-coating to form passivation layer.Table top high-power semiconductor device passivation technology generally adopts single-glass passivation, glassivation can effectively prevent that table top pn knot from staiing, and as a kind of terminal structure, improve the surface breakdown characteristic of table top high tension apparatus, make high-voltage semi-conductor device obtain voltage blocking ability.But single-glass passivation technology exist glass and silicon chip thermal coefficient of expansion inconsistent, under thermal stress, easily cause chip cracked, and glass is dielectric, can not shield external electric field can not modulate table top pn knot surface field, boron-containing glass also can adulterate and make that device is low to be punctured semiconductor, thereby passivation effect is limited, the reliability that single-glass passivation high tension apparatus is worked under high temperature, condition of high voltage is also lower.

The effect of α-polysilicon layer is: table top power semiconductor conventionally all adopts the wet etching method of hydrofluoric acid+red fuming nitric acid (RFNA)+glacial acetic acid in table top modeling process, more coarse in the complete pit of groove corrosion, the more important thing is that corrosion can cause generation lattice defect and higher surface density of states in groove, the compound meeting of device surface strengthens greatly, and leakage current is larger.

Therefore,, for addressing the above problem, spy provides a kind of new technical scheme.

Summary of the invention

The invention provides a kind of table top large power semiconductor device multilayer complex films passivating structure, a kind of preparation technology of table top large power semiconductor device multilayer complex films passivating structure is also provided.

The technical solution used in the present invention is:

A kind of table top large power semiconductor device multilayer complex films passivating structure, comprise P type boron interface and N type phosphorus interface, upper and lower two ends, described N type phosphorus interface are equipped with P type boron interface, on table top large power semiconductor device table top PN junction surface, comprise successively from inside to outside α-polysilicon layer, semi-insulating polysilicon film, low thermal oxidation layer, high temperature Si₃n₄film, negative electrical charge glass passivation layer and low thermal oxidation layer.

A kind of preparation technology of table top large power semiconductor device multilayer complex films passivating structure comprises following processing step successively:

A, deposit α-polysilicon, adopt LPCVD deposit, and temperature is 570 ~ 580 ℃, pressure 0.3 ~ 0.4t, SiH₄flow 40cc/min, deposition time 4 ~ 5min;

B, deposit semi-insulating polysilicon, adopt LPCVD deposit, and temperature is 650 ~ 670 ℃, pressure 0.3t, SiH₄flow 250cc/min, N₂o flow 40cc/min, deposition time 40 ~ 50min;

C, deposit low thermal oxidation layer, adopt LPCVD deposit, and temperature is 420 ~ 450 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 20 ~ 30min;

D, deposit Si₃n₄, adopting LPCVD deposit, temperature is 750 ~ 800 ℃, pressure 0.3 ~ 0.5t, SiH₂cl₂flow 150cc/min, NH₃flow 400cc/min, deposition time 20 ~ 30min;

E, glassivation, adopt the method for blade coating to be coated with leadaluminosilicate glass, first scrapes front and scrape the back side again, and glass burns condition and is: 450 ~ 500 ℃ of temperature, time 10min, O₂flow is 1000 ~ 1500mL/min, N₂flow is 4000mL/min, and sintering condition is: 750 ~ 780 ℃ of temperature, time 20min, O₂flow is 1000 ~ 1500mL/min, N₂flow is 4000mL/min, carries out twice blade coating, burns, sintered glass powder;

F, the deposit of outermost low thermal oxidation layer, adopt LPCVD deposit, and temperature is 420 ~ 450 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 30 ~ 50min.

The invention has the beneficial effects as follows: this table top large power semiconductor device multilayer complex films passivating structure both can be used for the passivation of single table surface power semiconductor and also can be used for two table top power semiconductor passivation, was widely used;

Deposit α-polysilicon layer can be realized lattice adaptation, repair silicon chip lattice damage in groove, reduce to tie tracking current, it above α-polysilicon, is SiPOS passivation film, this rete has semi-insulating characteristic, can shield well mobile ion and the impact of external electric field on device, improve the puncture voltage of device and reduce high-temperature current leakage; Sipos layer and high temperature Si₃n₄the effect of the low thermal oxidation layer (LTO) between film is: alleviate silicon face and Si₃n₄crystal lattice stress between film and thermal stress, avoid the generation of fault, dislocation, reduces silicon chip lattice defect, improves chip hot operation stability and reliability, high temperature Si simultaneously₃n₄effect can stop the contamination of mobile ion to device, reduce high pressure electric leakage, improve the dependability of high tension apparatus; Glass passivation layer effect is to strengthen passivation, improves the puncture voltage of device; The effect of outermost one deck low thermal oxidation layer (LTO) is coarse silicon chip surface after level and smooth glassing, improves silicon chip surface evenness to facilitate follow-up lead-in wire photoetching, metallization process; Be with the difference of common LPCVD, common LPCVD technique is only for preparing a kind of (as LTO or SIPOS or Si3N4) or two kinds (SIPOS+Si3N4) at chip surface, the present invention utilizes LPCVD technique at same chip surface successively deposit plural layers, multi-layer compound film is a rounded system, indispensable, improve the knot surface passivation performance of table top large power semiconductor device, reduce the leakage current of device, improve hot operation stability and the reliability of device, the working junction temperature that improves device, significantly improves product of production line yield.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Fig. 1 is two table top high-voltage semi-conductor device multilayer complex films passivating structure schematic diagrames.

Fig. 2 is single table surface high-voltage semi-conductor device multilayer complex films passivating structure schematic diagram.

Wherein: 1, α-polysilicon layer, 2, semi-insulating polysilicon film, 3, low thermal oxidation layer, 4, high temperature Si₃n₄film, 5, negative electrical charge glass passivation layer, 6, P type boron interface, 7, N type phosphorus interface.

Embodiment

In order to deepen the understanding of the present invention, below in conjunction with embodiment and accompanying drawing, to of the present invention, be described in further detail, this embodiment only, for explaining the present invention, does not form the restriction to protection scope of the present invention.

As shown in Figure 1 or 2, a kind of table top large power semiconductor device multilayer complex films passivating structure of the present invention, comprise P type boron interface 6 and Ntype phosphorus interface 7, N type phosphorus interface is equipped with P type boron interface 6 in two ends Shang Xia 7, on table top large power semiconductor device table top PN junction surface, comprises successively from inside to outside α-polysilicon layer 1,semi-insulating polysilicon film 2, lowthermal oxidation layer 3, high temperature Si₃n₄film 4, negative electrical chargeglass passivation layer 5 and lowthermal oxidation layer 3.

The invention has the beneficial effects as follows: this table top large power semiconductor device multilayer complex films passivating structure both can be used for the passivation of single table surface power semiconductor and also can be used for two table top power semiconductor passivation, was widely used.

Embodiment 1

A kind of preparation technology of table top large power semiconductor device multilayer complex films passivating structure comprises following processing step successively:

A, deposit α-polysilicon, adopt LPCVD deposit, and temperature is 570 ℃, pressure 0.3t, SiH₄flow 40cc/min, deposition time 4min;

B, deposit semi-insulating polysilicon, adopt LPCVD deposit, and temperature is 650 ℃, pressure 0.3t, SiH₄flow 250cc/min, N₂o flow 40cc/min, deposition time 40min;

C, deposit low thermal oxidation layer, adopt LPCVD deposit, and temperature is 420 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 20min;

D, deposit Si₃n₄, adopting LPCVD deposit, temperature is 750 ℃, pressure 0.3t, SiH₂cl₂flow 150cc/min, NH₃flow 400cc/min, deposition time 20min;

E, glassivation, adopt the method for blade coating to be coated with leadaluminosilicate glass, first scrapes front and scrape the back side again, and glass burns condition and is: 450 ℃ of temperature, time 10min, O₂flow is 1000mL/min, N₂flow is 4000mL/min, and sintering condition is: 750 ℃ of temperature, time 20min, O₂flow is 1000mL/min, N₂flow is 4000mL/min, carries out twice blade coating, burns, sintered glass powder;

F, the deposit of outermost low thermal oxidation layer, adopt LPCVD deposit, and temperature is 420 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 30min.

Embodiment 2

A kind of preparation technology of table top large power semiconductor device multilayer complex films passivating structure comprises following processing step successively:

A, deposit α-polysilicon, adopt LPCVD deposit, and temperature is 575 ℃, pressure 0.35t, SiH₄flow 40cc/min, deposition time 4.5min;

B, deposit semi-insulating polysilicon, adopt LPCVD deposit, and temperature is 660 ℃, pressure 0.3t, SiH₄flow 250cc/min, N₂o flow 40cc/min, deposition time 45min;

C, deposit low thermal oxidation layer, adopt LPCVD deposit, and temperature is 435 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 25min;

D, deposit Si₃n₄, adopting LPCVD deposit, temperature is 770 ℃, pressure 0.4t, SiH₂cl₂flow 150cc/min, NH₃flow 400cc/min, deposition time 25min;

E, glassivation, adopt the method for blade coating to be coated with leadaluminosilicate glass, first scrapes front and scrape the back side again, and glass burns condition and is: 480 ℃ of temperature, time 10min, O₂flow is 1200mL/min, N₂flow is 4000mL/min, and sintering condition is: 765 ℃ of temperature, time 20min, O₂flow is 1200mL/min, N₂flow is 4000mL/min, carries out twice blade coating, burns, sintered glass powder;

F, the deposit of outermost low thermal oxidation layer, adopt LPCVD deposit, and temperature is 435 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 40min.

Embodiment 3

A kind of preparation technology of table top large power semiconductor device multilayer complex films passivating structure comprises following processing step successively:

A, deposit α-polysilicon, adopt LPCVD deposit, and temperature is 580 ℃, pressure 0.4t, SiH₄flow 40cc/min, deposition time 5min;

B, deposit semi-insulating polysilicon, adopt LPCVD deposit, and temperature is 670 ℃, pressure 0.3t, SiH₄flow 250cc/min, N₂o flow 40cc/min, deposition time 50min;

C, deposit low thermal oxidation layer, adopt LPCVD deposit, and temperature is 450 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 30min;

D, deposit Si₃n₄, adopting LPCVD deposit, temperature is 800 ℃, pressure 0.5t, SiH₂cl₂flow 150cc/min, NH₃flow 400cc/min, deposition time 30min;

E, glassivation, adopt the method for blade coating to be coated with leadaluminosilicate glass, first scrapes front and scrape the back side again, and glass burns condition and is: 500 ℃ of temperature, time 10min, O₂flow is 1500mL/min, N₂flow is 4000mL/min, and sintering condition is: 780 ℃ of temperature, time 20min, O₂flow is 1500mL/min, N₂flow is 4000mL/min, carries out twice blade coating, burns, sintered glass powder;

F, the deposit of outermost low thermal oxidation layer, adopt LPCVD deposit, and temperature is 450 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 50min.

The invention has the beneficial effects as follows: deposit α-polysilicon layer can be realized lattice adaptation, repair silicon chip lattice damage in groove, reduce to tie tracking current, it above α-polysilicon, is SiPOS passivation film, this rete has semi-insulating characteristic, can shield well mobile ion and the impact of external electric field on device, improve the puncture voltage of device and reduce high-temperature current leakage; Sipos layer and high temperature Si₃n₄the effect of the low thermal oxidation layer (LTO) between film is: alleviate silicon face and Si₃n₄crystal lattice stress between film and thermal stress, avoid the generation of fault, dislocation, reduces silicon chip lattice defect, improves chip hot operation stability and reliability, high temperature Si simultaneously₃n₄effect can stop the contamination of mobile ion to device, reduce high pressure electric leakage, improve the dependability of high tension apparatus; Glass passivation layer effect is to strengthen passivation, improves the puncture voltage of device; The effect of outermost one deck low thermal oxidation layer (LTO) is coarse silicon chip surface after level and smooth glassing, improves silicon chip surface evenness to facilitate follow-up lead-in wire photoetching, metallization process; Be with the difference of common LPCVD, common LPCVD technique is only for preparing a kind of (as LTO or SIPOS or Si3N4) or two kinds (SIPOS+Si3N4) at chip surface, the present invention utilizes LPCVD technique at same chip surface successively deposit plural layers, multi-layer compound film is a rounded system, indispensable, improve the knot surface passivation performance of table top large power semiconductor device, reduce the leakage current of device, improve hot operation stability and the reliability of device, the working junction temperature that improves device, significantly improves product of production line yield.

The above, be only preferred embodiment of the present invention, is not the restriction of the present invention being made to any other form, and according to any modification or equivalent variations that technical spirit of the present invention is done, still belong to the present invention's scope required for protection.

Claims (2)

1. a table top large power semiconductor device multilayer complex films passivating structure, comprise P type boron interface and N type phosphorus interface, upper and lower two ends, described N type phosphorus interface are equipped with P type boron interface, it is characterized in that: on table top large power semiconductor device table top PN junction surface, comprise successively from inside to outside α-polysilicon layer, semi-insulating polysilicon film, low thermal oxidation layer, high temperature Si₃n₄film, negative electrical charge glass passivation layer and low thermal oxidation layer.

2. a preparation technology for table top large power semiconductor device multilayer complex films passivating structure as claimed in claim 1, is characterized in that: comprise successively following processing step:

A, deposit α-polysilicon, adopt LPCVD deposit, and temperature is 570 ~ 580 ℃, pressure 0.3 ~ 0.4t, SiH₄flow 40cc/min, deposition time 4 ~ 5min;

B, deposit semi-insulating polysilicon, adopt LPCVD deposit, and temperature is 650 ~ 670 ℃, pressure 0.3t, SiH₄flow 250cc/min, N₂o flow 40cc/min, deposition time 40 ~ 50min;

C, deposit low thermal oxidation layer, adopt LPCVD deposit, and temperature is 420 ~ 450 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 20 ~ 30min;

D, deposit Si₃n₄, adopting LPCVD deposit, temperature is 750 ~ 800 ℃, pressure 0.3 ~ 0.5t, SiH₂cl₂flow 150cc/min, NH₃flow 400cc/min, deposition time 20 ~ 30min;

E, glassivation, adopt the method for blade coating to be coated with leadaluminosilicate glass, first scrapes front and scrape the back side again, and glass burns condition and is: 450 ~ 500 ℃ of temperature, time 10min, O₂flow is 1000 ~ 1500mL/min, N₂flow is 4000mL/min, and sintering condition is: 750 ~ 780 ℃ of temperature, time 20min, O₂flow is 1000 ~ 1500mL/min, N₂flow is 4000mL/min, carries out twice blade coating, burns, sintered glass powder;

F, the deposit of outermost low thermal oxidation layer, adopt LPCVD deposit, and temperature is 420 ~ 450 ℃, pressure 0.3t, SiH₄flow 150cc/min, O₂flow 40cc/min, deposition time 30 ~ 50min.

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