CN103681261A - Preparation method of buffer layer or current carrier storage layer of power device - Google Patents
Preparation method of buffer layer or current carrier storage layer of power deviceDownload PDFInfo
- Publication number
- CN103681261A CN103681261ACN201210345386.0ACN201210345386ACN103681261ACN 103681261 ACN103681261 ACN 103681261ACN 201210345386 ACN201210345386 ACN 201210345386ACN 103681261 ACN103681261 ACN 103681261A
- Authority
- CN
- China
- Prior art keywords
- doping
- substrate
- neutrons
- buffer layer
- storage layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/261—Bombardment with radiation to produce a nuclear reaction transmuting chemical elements
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Toxicology (AREA)
- General Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明属于半导体设备技术领域，特别涉及一种功率器件缓冲层或截流子存储层的制备方法。The invention belongs to the technical field of semiconductor equipment, and in particular relates to a preparation method of a power device buffer layer or a carrier storage layer.
背景技术Background technique
半导体嬗变掺杂（nuclear transmutation doping of semiconductor）：用一定能量的中子、带电粒子或γ射线等照射材料，通过选择的核反应在基体中生成原来不存在的新元素，达到半导体材料的掺杂目的。目前，只有中子嬗变掺杂(NDT)得到了实际应用。此方法的原理是K.拉克－霍罗维茨于1951年提出的。1974年成功地用核反应堆热中子对区熔硅进行核嬗变掺杂，首次生产了商品的中子嬗变掺杂硅。目前中子掺杂硅单晶已成为工业产品，产量逐年增加。Semiconductor transmutation doping (nuclear transmutation doping of semiconductor): irradiate materials with neutrons, charged particles or gamma rays of a certain energy, and generate new elements that do not exist in the matrix through selected nuclear reactions to achieve the purpose of doping semiconductor materials . Currently, only neutron transmutation doping (NDT) has been used in practice. The principle of this method was proposed by K. Lark-Horowitz in 1951. In 1974, nuclear reactor thermal neutrons were successfully used for nuclear transmutation doping of zone molten silicon, and commercial neutron transmutation doped silicon was produced for the first time. At present, neutron-doped silicon single crystal has become an industrial product, and the output is increasing year by year.
中子嬗变掺杂，Neutron Transmutation Doping(NTD)：这是采用中子辐照的办法来对材料进行掺杂的一种技术。由于同位素原子在晶体中的分布是非常均匀的，而且中子在硅中的穿透深度又很大[≈100cm]，所以这种n型Si和p型Ge的掺杂非常均匀。这对于大功率半导体器件和辐射探测器件的制作是很有用的。Neutron transmutation doping, Neutron Transmutation Doping (NTD): This is a technique that uses neutron irradiation to dope materials. Since the distribution of isotopic atoms in the crystal is very uniform, and the penetration depth of neutrons in silicon is very large [≈100cm], the doping of n-type Si and p-type Ge is very uniform. This is very useful for the manufacture of high-power semiconductor devices and radiation detection devices.
光子嬗变掺杂：这是采用高能光子辐照的办法来对材料进行掺杂的一种技术，由于高能的电子在硅中的衰减系数很小，故掺入的杂质浓度也有非常好的均匀度。Photon transmutation doping: This is a technology that uses high-energy photon irradiation to dope materials. Since the attenuation coefficient of high-energy electrons in silicon is very small, the doped impurity concentration also has very good uniformity. .
目前，N+缓冲侧层的形成可以用不同的方法。最早的PT结构是在N+的衬底上先外延一层高掺杂的N+缓冲层，然后再外延低掺杂的N-漂移层。截流子存储层技术是对NPT结构的改进，它是将N型杂质从背面注入到集电集和漂移区之间。注入的尝试较浅，也可以先注入再退火，增加掺杂深度。也可以通过注氢退火形成较深的FS结构。SPT技术是利用扩散形成较深的N+缓冲层。而截流子存储层的形成可以在P槽注入之前进行一次N型掺杂的注入退火。也可以通过外延形成截流子存储层。Currently, the formation of the N+ buffer side layer can be done in different ways. In the earliest PT structure, a highly doped N+ buffer layer was epitaxially grown on an N + substrate, and then a low doped N- drift layer was epitaxially grown. The intercepting sub-storage layer technology is an improvement to the NPT structure, which injects N-type impurities from the back to between the collector and the drift region. The implantation attempt is relatively shallow, and it can also be implanted first and then annealed to increase the doping depth. A deeper FS structure can also be formed by hydrogen injection annealing. SPT technology uses diffusion to form a deep N+ buffer layer. For the formation of the carrier storage layer, an N-type doped implantation annealing can be performed before the P-channel implantation. The pinch sub-storage layer can also be formed by epitaxy.
但是，PT结构通过外延形成N+缓冲层的工艺比较复杂，成本较高，截流子存储层结构通过注入形成的N+缓冲层的注入深度较低。在集电区也会有施主与集电区的受主发生补偿，降低了集电区掺杂的有效浓度，导致集电区电阻增加。SPT技术形成的N+掺杂的峰值是在背面表面，这样导致集电区也会有大量施主与集电区的受主发生补偿，降低了集电区掺杂的有效浓度，导致集电区电阻增加。通过注入扩散形成的截流子存储层在随后制作P槽时也会发生补偿，增加了闩锁电阻，降低了闩锁电流。通过外延形成截流子存储层的工艺比较复杂，制造成本较高。通过注入或扩散形成的N缓冲层或截流子存储层的掺杂的纵向分布不能是任意分布。However, the process of forming the N+ buffer layer by epitaxy in the PT structure is relatively complicated and the cost is high, and the implantation depth of the N+ buffer layer formed by implantation of the interceptor sub-storage layer structure is relatively low. In the collector area, there will also be donors and acceptors in the collector area to compensate, which reduces the effective concentration of doping in the collector area, resulting in an increase in the resistance of the collector area. The peak of N+ doping formed by SPT technology is on the back surface, which will cause a large number of donors in the collector area to compensate with the acceptors in the collector area, reducing the effective concentration of doping in the collector area, resulting in The resistance increases. The interceptor storage layer formed by implantation and diffusion will also be compensated when the P-groove is fabricated later, which increases the latch-up resistance and reduces the latch-up current. The process of forming the interceptor storage layer by epitaxy is relatively complicated, and the manufacturing cost is relatively high. The longitudinal distribution of the doping of the N buffer layer or the carrier storage layer formed by implantation or diffusion cannot be random.
发明内容Contents of the invention
本发明所要解决的技术问题是提供一种功率器件缓冲层或截流子存储层的制备方法，解决了现有技术中掺杂分布不均匀、掺杂深度不够和掺杂中引入杂质的技术问题。The technical problem to be solved by the present invention is to provide a preparation method of a power device buffer layer or a choke storage layer, which solves the technical problems of uneven doping distribution, insufficient doping depth and the introduction of impurities in the prior art.
为解决上述技术问题，本发明提供了一种功率器件缓冲层或截流子存储层的制备方法，通过中子嬗变掺杂将中子通过掩膜注入到衬底的单侧或者双侧或者通过光致嬗变掺杂将光子通过掩膜注入到衬底的单侧或者双侧，通过控制辐照剂量，使所述衬底形成具有特定浓度的缓冲层或截流子存储层。In order to solve the above-mentioned technical problems, the present invention provides a method for preparing a buffer layer or a storage layer for interceptors of a power device, in which neutrons are injected into one or both sides of the substrate through a mask through neutron transmutation doping or through light Transmutation-induced doping injects photons into one or both sides of the substrate through a mask, and by controlling the radiation dose, the substrate forms a buffer layer or a storage layer of interceptors with a specific concentration.
进一步地，所述控制方法还包括通过中子嬗变掺杂将中子通过中子束扫描的方法注入到衬底的单侧或者双侧。Further, the control method further includes injecting neutrons into one side or both sides of the substrate by neutron transmutation doping by neutron beam scanning.
进一步地，所述功率器件为PIN二极管、VDMOS、IGBT或IEGT中的任一一种。Further, the power device is any one of PIN diode, VDMOS, IGBT or IEGT.
进一步地，所述功率器件的半导体材料为硅、锗、碳化硅、金刚石、砷化镓或锑化铟的任一一种。Further, the semiconductor material of the power device is any one of silicon, germanium, silicon carbide, diamond, gallium arsenide or indium antimonide.
本发明提供的功率器件缓冲层或截流子存储层的制备方法，在中子经过的路径上，由于嬗变引入了N型的杂质，通过控制中子的剂量，可以形成具有浓度的N+掺杂层。同时，由于中子束足够细，可以形成任何形状的掺杂分布图。In the preparation method of the power device buffer layer or the interceptor storage layer provided by the present invention, N-type impurities are introduced due to transmutation on the path of neutrons, and N+ doping with high concentration can be formed by controlling the dose of neutrons. layer. At the same time, since the neutron beam is sufficiently thin, any shape of doping profile can be formed.
附图说明Description of drawings
图1为本发明实施例提供的将中子通过掩膜注入到衬底的单侧示意图；Fig. 1 is a one-side schematic view of injecting neutrons into a substrate through a mask provided by an embodiment of the present invention;
图2为本发明实施例提供的将中子通过掩膜注入到衬底的双侧示意图；Fig. 2 is a double-sided schematic diagram of injecting neutrons into a substrate through a mask provided by an embodiment of the present invention;
图3为本发明实施例提供的将中子通过中子束扫描的方法注入到衬底的单侧示意图；Fig. 3 is a one-side schematic diagram of injecting neutrons into a substrate by neutron beam scanning method provided by an embodiment of the present invention;
图4为本发明实施例提供的将中子通过中子束扫描的方法注入到衬底的双侧示意图；Fig. 4 is a double-sided schematic diagram of injecting neutrons into a substrate through a neutron beam scanning method provided by an embodiment of the present invention;
图5为本发明实施例提供的通过中子束辐照形成N+缓冲层的示意图；Fig. 5 is a schematic diagram of forming an N+ buffer layer by neutron beam irradiation provided by an embodiment of the present invention;
图6为本发明实施例提供的通过中子束辐照形成N+截流子存储层的示意图。Fig. 6 is a schematic diagram of forming an N+ interceptor storage layer by neutron beam irradiation according to an embodiment of the present invention.
具体实施方式Detailed ways
本发明实施例提供的一种功率器件缓冲层或截流子存储层的制备方法，参见图1，通过中子嬗变掺杂将中子通过掩膜注入到衬底的单侧，参加图2，也可以通过中子嬗变掺杂将中子通过掩膜注入到衬底的双侧，同时，也可以通过光致嬗变掺杂将光子通过掩膜注入到衬底的单侧，或者通过光致嬗变掺杂将光子通过掩膜注入到衬底的双侧，在本发明实施例中，功率器件为硅片100，由于中子的穿透能力非常强，通过中子吸收材料制作的掩膜102，辐射到嬗变掺杂区域103，几乎是直线穿过衬底。在中子经过的路径上由于嬗变引入了N型的杂质，将硅片100一端与测试设备相连，测试设备检测硅片100中P柱的电荷量和N柱中的电荷量，根据硅片100中P柱的电荷量和N柱中的电荷量，控制中子的剂量，使衬底形成具有浓度的N+缓冲层或N+截流子存储层。The embodiment of the present invention provides a method for preparing a buffer layer or a storage layer of a power device, see FIG. 1, inject neutrons into one side of the substrate through a mask through neutron transmutation doping, refer to FIG. 2, also Neutrons can be injected into both sides of the substrate through a mask through neutron transmutation doping, and photons can also be injected into one side of the substrate through a mask through phototransmutation doping, or through phototransmutation doping The photons are injected into both sides of the substrate through the mask. In the embodiment of the present invention, the power device is a
N+掺杂层还可以通过方向性很好的中子束101扫描的方法形成，此方法可以省去掩膜，参见图3,该控制方法还包括通过中子嬗变掺杂将中子通过中子束扫描的方法注入到衬底的单侧，参见图4，通过中子嬗变掺杂将中子通过中子束扫描的方法注入到衬底的双侧。The N+ doped layer can also be formed by scanning a
本发明的方案可以通过改变中子辐照的区域，并精确控制辐照的剂量，从而形成特定的纵向掺杂浓度分布，只要中子束足够细，理论上这种方法可以形成任何形状的掺杂分布图。这一点是难以通过注入或扩散过程实现的。The scheme of the present invention can form a specific vertical doping concentration distribution by changing the neutron irradiation area and precisely controlling the irradiation dose. As long as the neutron beam is thin enough, this method can theoretically form any shape of doping concentration. Miscellaneous distribution diagram. This is difficult to achieve through implantation or diffusion processes.
参见图5，本发明实施例提供的通过中子束辐照形成N+缓冲层，N+缓冲层中的掺杂浓度可以通过调节中子束与半导体的相对位置和辐照的剂量而形成任何所需的浓度分布。从图5中可以看出，105为中子束的平行移动的范围，中子束101在该范围内移动，1031-1035为不同掺杂浓度的嬗变掺杂层，其中，106为嬗变掺杂层的浓度区域。Referring to Fig. 5, an N+ buffer layer is formed by neutron beam irradiation according to an embodiment of the present invention, and the doping concentration in the N+ buffer layer can be adjusted by adjusting the relative position of the neutron beam and the semiconductor and the irradiation dose to form any desired concentration profile. As can be seen from Figure 5, 105 is the range of parallel movement of the neutron beam, and the
由于这种掺杂方式没有在P+集电区引入N型的杂质，故在集电区不会发生补偿效应。Since this doping method does not introduce N-type impurities in the P+ collector area, no compensation effect will occur in the collector area.
参见图6，本发明实施例提供的通过中子束辐照形成N+截流子存储层，在图6中，IGBT漂移区200为第一导电类型，201为IGBT的栅极区域。低掺杂的第二导电类型区域202为IGBT基区。高掺杂的第一导电类型区域203为IGBT的发射区。IGBT的栅极区域201被绝缘层204包围。207为发射极金属，IGBT的发射区之间由发射极金属207连接。205为高掺杂浓度的第一导电类型区域，为IGBT的缓冲层。高掺杂浓度的第二导电类型区域206为IGBT的集电极。N+截流子存储层中的掺杂浓度可以通过调节中子束与半导体的相对位置和辐照的剂量而形成任何所需的浓度分布。由于这种掺杂方式没有在P-基区引入N型的杂质，故在集电区不会发生补偿效应。Referring to FIG. 6 , an N+ interceptor storage layer is formed by neutron beam irradiation according to an embodiment of the present invention. In FIG. 6 , the
子嬗变掺杂可以在其它工艺完成后再进行，也可以插入到某一个常规工艺之中进行，可以在对晶圆进行掺杂，也可以对芯片进行掺杂。Sub-transmutation doping can be carried out after other processes are completed, or it can be inserted into a certain conventional process. It can be doped on the wafer or on the chip.
对于其它的半导体材料也可以通过某种适当的嬗变掺杂，比如高能光子辐照等进行侧向掺杂形成N+型的缓冲层或截流子存储层。对于P沟道的IGBT等器件，通过适当的嬗变掺杂也可以形成P+型的缓冲层或截流子存储层。Other semiconductor materials can also be laterally doped by some appropriate transmutation doping, such as high-energy photon irradiation, to form an N+ type buffer layer or a carrier storage layer. For devices such as P-channel IGBTs, a P+ type buffer layer or a carrier storage layer can also be formed through appropriate transmutation doping.
可用于各类功率器件的缓冲层，截流子存储层的形成。功率器件的半导体材料为硅、锗、碳化硅、金刚石、砷化镓或锑化铟的任一一种。可以形成N型的掺杂层，也可以形成P型的掺杂层。It can be used in the formation of buffer layers and interceptor storage layers of various power devices. The semiconductor material of the power device is any one of silicon, germanium, silicon carbide, diamond, gallium arsenide or indium antimonide. An N-type doped layer may be formed, or a P-type doped layer may be formed.
本方案主要是用于制造PIN二极管，VDMOS（垂直双扩散金属-氧化物半导体场效应晶体管）、IGBT（绝缘栅双极型晶体管）、IEGT（电子注入增强栅晶体管）器件的N+缓冲层或截流子存储层。本发明的优点如下：This solution is mainly used to manufacture PIN diodes, VDMOS (vertical double-diffused metal-oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), and IEGT (electron injection enhanced gate transistors) devices. sub-storage tier. The advantages of the present invention are as follows:
1.嬗变掺杂所用的粒子束有很强的穿透能力非常强，而且粒子在硅片中的路径几乎是直线，在衬底几乎形成了一致的掺杂分布。掺杂的区域分明，浓度可以精确控制。1. The particle beam used for transmutation doping has a very strong penetrating ability, and the path of the particles in the silicon wafer is almost a straight line, forming an almost uniform doping distribution on the substrate. The doping area is distinct, and the concentration can be precisely controlled.
2.可以形成距半导体表面任何深度的掺杂层。这个是离子注入或扩散难以实现的。2. A doped layer can be formed at any depth from the semiconductor surface. This is difficult to achieve with ion implantation or diffusion.
3.通过控制嬗变掺杂的位置和剂量，可以实现任何掺杂分布，从而优化器件的性能。3. By controlling the location and dose of transmutation doping, any doping profile can be achieved, thereby optimizing the performance of the device.
4.侧向掺杂由于没有在其它地方引入杂质，故不会与其它地方相反类型的杂质发生补偿。4. Since the lateral doping does not introduce impurities in other places, it will not compensate for the opposite type of impurities in other places.
最后所应说明的是，以上具体实施方式仅用以说明本发明的技术方案而非限制，尽管参照实例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.
Claims (4)
Translated fromChinesePriority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210345386.0ACN103681261A (en) | 2012-09-17 | 2012-09-17 | Preparation method of buffer layer or current carrier storage layer of power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210345386.0ACN103681261A (en) | 2012-09-17 | 2012-09-17 | Preparation method of buffer layer or current carrier storage layer of power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103681261Atrue CN103681261A (en) | 2014-03-26 |
Family
ID=50318469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210345386.0APendingCN103681261A (en) | 2012-09-17 | 2012-09-17 | Preparation method of buffer layer or current carrier storage layer of power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103681261A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87100971A (en)* | 1986-02-25 | 1987-09-09 | 英国原子能管理局 | Photonuclear doping of semiconductors |
| US6028329A (en)* | 1997-01-28 | 2000-02-22 | Industrial Technology Research Institute | Bipolar junction transistor device and a method of fabricating the same |
| US6162665A (en)* | 1993-10-15 | 2000-12-19 | Ixys Corporation | High voltage transistors and thyristors |
| TW200501433A (en)* | 2003-04-08 | 2005-01-01 | Cree Inc | Semi-insulating silicon carbide produced by neutron transmutation doping |
| CN1868066A (en)* | 2003-10-16 | 2006-11-22 | 克里公司 | Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby |
| CN102315104A (en)* | 2011-09-08 | 2012-01-11 | 浙江向日葵光能科技股份有限公司 | Manufacturing method for realizing selective-emitter crystalline silicon solar cell through neutron transmutation doping |
- 2012
- 2012-09-17CNCN201210345386.0Apatent/CN103681261A/enactivePending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87100971A (en)* | 1986-02-25 | 1987-09-09 | 英国原子能管理局 | Photonuclear doping of semiconductors |
| US6162665A (en)* | 1993-10-15 | 2000-12-19 | Ixys Corporation | High voltage transistors and thyristors |
| US6028329A (en)* | 1997-01-28 | 2000-02-22 | Industrial Technology Research Institute | Bipolar junction transistor device and a method of fabricating the same |
| TW200501433A (en)* | 2003-04-08 | 2005-01-01 | Cree Inc | Semi-insulating silicon carbide produced by neutron transmutation doping |
| CN1868066A (en)* | 2003-10-16 | 2006-11-22 | 克里公司 | Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby |
| CN102315104A (en)* | 2011-09-08 | 2012-01-11 | 浙江向日葵光能科技股份有限公司 | Manufacturing method for realizing selective-emitter crystalline silicon solar cell through neutron transmutation doping |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10998398B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US10497801B2 (en) | Method of manufacturing a semiconductor device having an undulated profile of net doping in a drift zone | |
| US10629678B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN105655244B (en) | The method and semiconductor devices of manufacture semiconductor devices are injected using light ion | |
| US8361893B2 (en) | Semiconductor device and substrate with chalcogen doped region | |
| JP2021073733A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US10497570B2 (en) | Method for manufacturing semiconductor device having buffer layer | |
| US20240332373A1 (en) | Semiconductor device and manufacturing method | |
| CN105280485A (en) | Method of Manufacturing a Semiconductor Device Comprising Field Stop Zone | |
| JPWO2015087507A1 (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN107680905A (en) | Including activating the manufacture method of dopant and there is the semiconductor device of precipitous knot | |
| CN114944337A (en) | A kind of manufacturing method of superjunction IGBT | |
| CN111739930B (en) | A kind of MOS gate-controlled thyristor hardened against ionizing radiation | |
| JP6976493B1 (en) | Semiconductor devices and their manufacturing methods | |
| CN103839994A (en) | IGBT structure and manufacturing method thereof | |
| CN104716039B (en) | Improve the back process preparation method of IGBT performances | |
| CN103681261A (en) | Preparation method of buffer layer or current carrier storage layer of power device | |
| CN109712885A (en) | A kind of semiconductor devices buffering layer manufacturing method | |
| CN105206516A (en) | Method for forming field cut-off layer in semiconductor device | |
| CN103489775A (en) | Novel field cut-off type insulated gate bipolar transistor manufacturing method | |
| CN103855000A (en) | Manufacturing method of reverse-resistance type insulated gate bipolar transistor | |
| JP2008172145A (en) | Diode manufacturing method | |
| CN103681262B (en) | Manufacturing method of high-charge-balance super junction device | |
| CN104716040B (en) | The preparation method for effectively reducing the IGBT device of power consumption | |
| CN119545829A (en) | Method for manufacturing IGBT device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | Application publication date:20140326 | |
| RJ01 | Rejection of invention patent application after publication |