技术领域technical field
本发明是涉及一种半导体制造技术领域，更确切的说，本发明涉及一种采用伪栅极制造半导体器件的方法。The present invention relates to the technical field of semiconductor manufacturing, more precisely, the present invention relates to a method for manufacturing semiconductor devices using dummy gates.
背景技术Background technique
在使用伪栅极制造半导体器件的过程中，通常包括在衬底上形成伪栅极、源极漏极，然后去除伪栅极上的相应部分并填充因移除伪栅极该部分而产生的沟槽以形成栅极等一系列的步骤。在这一系列的步骤中，伪栅极相应部分的去除是一个极为关键的步骤。通常情况下使用干刻蚀在去除由多晶硅所形成的伪栅极，但是干刻蚀的刻蚀选择性不理想，往往会对器件造成不必要的损伤，从而对所制造的器件的性能造成影响。In the process of using dummy gates to manufacture semiconductor devices, it usually includes forming dummy gates, source drains on the substrate, and then removing the corresponding part on the dummy gate and filling the gap generated by removing the part of the dummy gate. Trench to form a series of steps such as gate. In this series of steps, the removal of the corresponding part of the dummy gate is an extremely critical step. Usually, dry etching is used to remove the dummy gate formed by polysilicon, but the etching selectivity of dry etching is not ideal, which often causes unnecessary damage to the device, thereby affecting the performance of the manufactured device .
但是目前采用伪栅极制造半导体器件的工艺中没有方法来克服上述问题。However, there is no way to overcome the above-mentioned problems in the process of manufacturing semiconductor devices using dummy gates at present.
发明内容Contents of the invention
鉴于以上问题，本发明提供一种采用伪栅极制造半导体器件的方法，包括步骤：In view of the above problems, the present invention provides a method for manufacturing a semiconductor device using a dummy gate, comprising steps:
a)提供半导体衬底，所述半导体衬底包括第一区域和第二区域；a) providing a semiconductor substrate comprising a first region and a second region;
b)在所述第一区域的衬底上形成第一伪栅极，在所述第二区域的衬底上形成第二伪栅极，所述第一伪栅极和第二伪栅极包括依次堆栈的栅极介电层、覆盖层和多晶硅层；b) forming a first dummy gate on the substrate in the first region, forming a second dummy gate on the substrate in the second region, the first dummy gate and the second dummy gate comprising sequentially stacked gate dielectric layer, capping layer and polysilicon layer;
c)在所述衬底中形成源漏极；c) forming source and drain electrodes in the substrate;
d)在所述第二伪栅极的顶部形成阻挡层；d) forming a barrier layer on top of the second dummy gate;
e)采用湿法蚀刻去除所述第一伪栅极的多晶硅层以形成沟槽；e) removing the polysilicon layer of the first dummy gate by wet etching to form a trench;
f)填充所述沟槽形成金属栅极。f) filling the trench to form a metal gate.
进一步，所述步骤d）包括：Further, said step d) includes:
在所述第一伪栅极的多晶硅层上形成掩膜层；forming a mask layer on the polysilicon layer of the first dummy gate;
在所述第二伪栅极的多晶硅层上形成所述阻挡层；forming the barrier layer on the polysilicon layer of the second dummy gate;
去除所述第一伪栅极的多晶硅层上的掩膜层；removing the mask layer on the polysilicon layer of the first dummy gate;
进一步，其中所述掩膜层是光刻胶层。Further, the mask layer is a photoresist layer.
进一步，其中还包括在所述光刻胶层和所述多晶硅层之间形成BARC。Further, it also includes forming BARC between the photoresist layer and the polysilicon layer.
进一步，其中所述阻挡层是氧化层或氮化层。Further, the barrier layer is an oxide layer or a nitride layer.
进一步，其中所述阻挡层具有大于30埃的厚度。Further, wherein the barrier layer has a thickness greater than 30 angstroms.
进一步，其中所述形成阻挡层的方法是等离子体的方法或离子注入的方法。Further, the method for forming the barrier layer is a plasma method or an ion implantation method.
进一步，其中所述去除掩膜层步骤中使用包括H2和N2的气体。Further, the gas including H2 and N2 is used in the step of removing the mask layer.
进一步，其中所述湿法刻蚀第一伪栅极的多晶硅层步骤中使用的溶液包括TMAH。Further, the solution used in the step of wet etching the polysilicon layer of the first dummy gate includes TMAH.
进一步，其中所述湿法刻蚀第一伪栅极的多晶硅层步骤中使用的溶液包括KTMAH。Further, the solution used in the step of wet etching the polysilicon layer of the first dummy gate includes KTMAH.
进一步，还包括在所述去除掩膜层步骤之后进行去除自然氧化层的步骤。Further, it also includes the step of removing the natural oxide layer after the step of removing the mask layer.
进一步，其中使用DHF来执行所述自然氧化层的去除。Further, wherein DHF is used to perform the removal of the native oxide layer.
进一步，其中所述去除自然氧化层的步骤在与所述湿法刻蚀多晶硅层的步骤相同的反应腔中执行。Further, the step of removing the natural oxide layer is performed in the same reaction chamber as the step of wet etching the polysilicon layer.
进一步，还包括在步骤f）之后进行去除第二伪栅极的多晶硅层形成沟槽；填充所述沟槽形成金属栅极。Further, after step f), removing the polysilicon layer of the second dummy gate to form a trench; filling the trench to form a metal gate.
进一步，其中所述去除第二伪栅极的多晶硅层的方法是湿法刻蚀去除的方法。Further, the method for removing the polysilicon layer of the second dummy gate is a wet etching method.
进一步，还包括在所述衬底和所述伪栅极之间形成界面层。Further, it also includes forming an interface layer between the substrate and the dummy gate.
进一步，其中使用高K材料形成所述栅极介电层。Further, the gate dielectric layer is formed using a high-K material.
进一步，其中使用TiN或TaN来形成所述覆盖层。Further, TiN or TaN is used to form the capping layer.
进一步，还包括在步骤b）之后，在所述伪栅极的侧壁和衬底上形成偏移侧墙和间隙壁的步骤。Further, after step b), the step of forming offset sidewalls and spacers on the sidewalls of the dummy gate and the substrate is also included.
进一步，还包括在步骤c）之后形成ILD于所述衬底和所述第一和第二伪栅极上以及平坦化所述ILD以暴露所述第一伪栅极和第二伪栅极的步骤。Further, after step c), forming an ILD on the substrate and the first and second dummy gates and planarizing the ILD to expose the first dummy gate and the second dummy gate step.
本发明中采用伪栅极的方法在半导体器件的制造过程中可以在半导体的制造过程中对多晶硅的伪栅极的相应部分进行高度选择性的去除，从而可以避免对器件造成损伤，从而提高所制造的半导体器件的性能。In the present invention, the dummy gate method can be used in the manufacturing process of semiconductor devices to highly selectively remove the corresponding part of the dummy gate of polysilicon, thereby avoiding damage to the device, thereby improving the performance of the semiconductor device. performance of fabricated semiconductor devices.
附图说明Description of drawings
图1-8是本发明各个工艺步骤的器件剖面图。1-8 are device cross-sectional views of various process steps of the present invention.
具体实施方式detailed description
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的采用伪栅极制造半导体器件的方法。显然，本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。In order to thoroughly understand the present invention, detailed steps will be provided in the following description to explain the method for manufacturing semiconductor devices using dummy gates proposed by the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.
应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合接下来，将结合附图更加完整地描述本发明。It should be understood that when the terms "comprising" and/or "comprising" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or A number of other features, wholes, steps, operations, elements, components and/or combinations thereof Next, the present invention will be described more fully with reference to the accompanying drawings.
参照图1。首先，提供半导体衬底200。包括第一区域和第二区域，所述第一区域可以为PMOS区域，所述第二区域可以为NMOS区域。所述衬底可以为以下所提到的材料中的至少一种：硅、绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S-SiGeOI）以及绝缘体上锗化硅（SiGeOI）等。在所述衬底中可以形成有掺杂区域和/或隔离结构，所述隔离结构为浅沟槽隔离（STI）结构或者局部氧化硅（LOCOS）隔离结构。在本发明的实施例中，所述衬底可以是Si衬底，其还可以包括在Si上的界面层，图中未示出。在一个实施例中通过快速热氧化工艺（RTO）或原子层沉积工艺（ALD）来形成具有5-10A的SiO2界面层。然后在该衬底上形成栅极介电层201，可以选用高K材料来形成所述栅极介电层，例如用在Hf02中引入Si、Al、N、La、Ta等元素并优化各元素的比率来得到的高K材料等。所述形成栅极介电层的方法可以是物理气相沉积工艺或原子层沉积工艺(ALD)。在本发明的实施例中，在所述SiO2界面层上形成HfAION栅极介电层，其厚度为15到60埃。之后，在栅极介电层201上形成栅极堆栈结构的覆盖层202，可以是ALD所形成的TiN或TaN的覆盖层。之后在覆盖层202上沉积多晶硅层300。在本发明的一个实施例中，使用低压化学气相淀积(LPCVD)工艺来形成多晶硅层，其的工艺条件包括：反应气体为硅烷(SiH4)，所述硅烷的流量范围为100～200立方厘米/分钟(sccm)，如150sccm；反应腔内温度范围为700～750摄氏度；反应腔内压力为250～350毫毫米汞柱(mTorr)，如300mTorr；所述反应气体中还包括缓冲气体，所述缓冲气体可为氦气(He)或氮气，所述氦气和氮气的流量范围为5～20升/分钟(slm)，如8slm、10slm或15slm。Refer to Figure 1. First, a semiconductor substrate 200 is provided. It includes a first area and a second area, the first area may be a PMOS area, and the second area may be an NMOS area. The substrate may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), and germanium-on-insulator Silicon oxide (SiGeOI), etc. A doped region and/or an isolation structure may be formed in the substrate, and the isolation structure is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure. In an embodiment of the present invention, the substrate may be a Si substrate, which may also include an interface layer on Si, which is not shown in the figure. In one embodiment, a SiO2 interfacial layer with 5-10 Å is formed by rapid thermal oxidation (RTO) or atomic layer deposition (ALD). Then a gate dielectric layer 201 is formed on the substrate, and a high-K material can be selected to form the gate dielectric layer, such as introducing Si, Al, N, La, Ta and other elements into HfO2 and optimizing each element The ratio to get high-K materials, etc. The method for forming the gate dielectric layer may be physical vapor deposition or atomic layer deposition (ALD). In an embodiment of the present invention, a HfAION gate dielectric layer is formed on the SiO2 interface layer with a thickness of 15 to 60 angstroms. After that, a cover layer 202 of the gate stack structure is formed on the gate dielectric layer 201 , which may be a cover layer of TiN or TaN formed by ALD. A polysilicon layer 300 is then deposited on the capping layer 202 . In one embodiment of the present invention, a low-pressure chemical vapor deposition (LPCVD) process is used to form the polysilicon layer, and its process conditions include: the reaction gas is silane (SiH4), and the flow rate of the silane is in the range of 100 to 200 cubic centimeters per minute (sccm), such as 150sccm; the temperature range in the reaction chamber is 700 to 750 degrees Celsius; the pressure in the reaction chamber is 250 to 350 millimeters of mercury (mTorr), such as 300mTorr; the reaction gas also includes a buffer gas, so The buffer gas may be helium (He) or nitrogen, and the flow range of the helium and nitrogen is 5-20 liters/minute (slm), such as 8 slm, 10 slm or 15 slm.
然后，可以使用光刻工艺对以上步骤所形成的界面层、栅极介电层201、覆盖层202和多晶硅层300进行图案化处理以形成堆栈的伪栅极结构。Then, the interface layer, the gate dielectric layer 201 , the capping layer 202 and the polysilicon layer 300 formed in the above steps may be patterned using a photolithography process to form a stacked dummy gate structure.
如图2所示。还可以进行形成偏移侧墙（offset spacer）211的步骤。偏移侧墙的材料可以是氮化硅，氧化硅或者氮氧化硅等绝缘材料。偏移侧墙可以提高形成的晶体管的沟道长度，减小短沟道效应和由于短沟道效应引起的热载流子效应。形成偏移侧墙的工艺可以是化学气相沉积。在一个实施例中所形成的偏移侧墙的厚度可以小到80埃。as shown in picture 2. A step of forming offset spacers 211 may also be performed. The material of the offset sidewall may be insulating material such as silicon nitride, silicon oxide or silicon oxynitride. The offset sidewall can increase the channel length of the formed transistor, reduce the short channel effect and the hot carrier effect caused by the short channel effect. The process for forming the offset sidewalls may be chemical vapor deposition. In one embodiment, the thickness of the formed offset spacer can be as small as 80 Angstroms.
以及形成轻掺杂源极/漏极(LDD)于栅极结构任一侧的衬底中的步骤。所述形成LDD的方法可以是离子注入工艺或扩散工艺。LDD注入的离子类型根据将要形成的半导体器件的电性决定，即形成的器件为NMOS器件，则LDD注入工艺中掺入的杂质离子为磷、砷、锑、铋中的一种或组合；若形成的器件为PMOS器件，则注入的杂质离子为硼。根据所需的杂质离子的浓度，离子注入工艺可以一步或多步完成。and the step of forming lightly doped source/drain (LDD) in the substrate on either side of the gate structure. The method for forming the LDD may be an ion implantation process or a diffusion process. The type of ions implanted by the LDD is determined by the electrical properties of the semiconductor device to be formed, that is, the formed device is an NMOS device, and the impurity ions doped in the LDD implantation process are one or a combination of phosphorus, arsenic, antimony, and bismuth; if The formed device is a PMOS device, and the implanted impurity ions are boron. Depending on the desired concentration of impurity ions, the ion implantation process can be performed in one or more steps.
以及在衬底200和上述步骤所形成的偏移侧墙上形成间隙壁（Spacer）212的步骤。可以使用氮化硅、碳化硅、氮氧化硅或其组合的材料。可以在衬底上沉积第一氧化硅层、第一氮化硅层以及第二氧化硅层，然后采用蚀刻方法形成间隙壁，所述间隙壁可以具有10-30NM的厚度。And a step of forming a spacer (Spacer) 212 on the substrate 200 and the offset sidewall formed in the above steps. Materials of silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof may be used. A first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer may be deposited on the substrate, and then an etching method is used to form a spacer, and the spacer may have a thickness of 10-30NM.
以及用离子注入工艺或扩散工艺重掺杂源极和漏极（S/D）形成于栅极间隙壁任一侧的衬底中的步骤，高温退火步骤，形成金属硅化物（SAB）阻挡层等步骤(图中未示出)。And the step of heavily doping the source and drain (S/D) by ion implantation process or diffusion process in the substrate formed on either side of the gate spacer, high temperature annealing step, forming a metal silicide (SAB) barrier layer and other steps (not shown in the figure).
参照图3。然后还可以在器件的表面沉积蚀刻停止层，图中未示出。蚀刻停止层可用SiCN、SiN、SiC、SiOF、SiON等形成。然后进行沉积层间介电层（ILD）220于栅极结构之上及其之间。可以采用化学气相沉积法、高密度等离子体化学气相沉积法、旋转涂布法、溅镀等方法形成，所述层间介电层可以采用氧化硅、氮氧化硅、氮化硅等材料来形成。Refer to Figure 3. An etch stop layer may then also be deposited on the surface of the device, not shown in the figure. The etch stop layer can be formed with SiCN, SiN, SiC, SiOF, SiON, or the like. An interlayer dielectric (ILD) 220 is then deposited over and between the gate structures. It can be formed by methods such as chemical vapor deposition, high-density plasma chemical vapor deposition, spin coating, sputtering, etc., and the interlayer dielectric layer can be formed by materials such as silicon oxide, silicon oxynitride, and silicon nitride. .
参照图4。然后对层间介电层220和/或刻蚀停止层进行平坦化处理。所述平坦化处理的非限制性实例包括机械平坦化方法和化学机械抛光平坦化方法。以暴露伪栅极结构的上表面。在一个实施例中用CMP的方法以暴露多晶硅层300。Refer to Figure 4. A planarization process is then performed on the interlayer dielectric layer 220 and/or the etch stop layer. Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method. to expose the upper surface of the dummy gate structure. In one embodiment, CMP is used to expose the polysilicon layer 300 .
参照图5。然后在平坦化步骤处理过的第一伪栅极区域的层间介电层及所暴露的第一伪栅极结构上形成掩模层301。在一个实施例中，在PFET区域所暴露的多晶硅层和ILD上形成掩膜层。可以包括数种掩模材料的任何一种，包括但不限于：硬掩模材料和光刻胶掩模材料。优选地，掩模层包括光刻胶掩模材料。光刻胶掩模材料可以包括选自包括正性光刻胶材料、负性光刻胶材料和混合光刻胶材料等。该掩模层可以包括具有厚度从大约2000到大约5000埃的正性光刻胶材料或负性光刻胶材料。在一个实施例中还可以包括光刻胶的底部抗反射涂层（BARC），可以用TiN或SiN来形成该BARC。Refer to Figure 5. Then a mask layer 301 is formed on the interlayer dielectric layer of the first dummy gate region processed in the planarization step and the exposed first dummy gate structure. In one embodiment, a masking layer is formed over the exposed polysilicon layer and ILD in the PFET region. Any of several mask materials may be included, including but not limited to: hard mask materials and photoresist mask materials. Preferably, the mask layer comprises a photoresist mask material. The photoresist mask material may include a material selected from positive photoresist materials, negative photoresist materials, hybrid photoresist materials, and the like. The mask layer may include a positive photoresist material or a negative photoresist material having a thickness from about 2000 to about 5000 Angstroms. A bottom anti-reflective coating (BARC) of photoresist may also be included in one embodiment, and the BARC may be formed from TiN or SiN.
参照图6。在平坦化步骤后暴露的第二伪栅极的多晶硅层上形成阻挡层302。在一个实施例中，该阻挡层形成于NFET区域伪栅极的多晶硅层上。该阻挡层可以是形成于多晶硅层上的氧化层或氮化层，可以使用等离子体氧化或氮化的方法以及离子注入的方法。在一个实施例中的等离子体氧化的方法在PECVD的系统中进行，其射频原频率为13.56Hz，气源为氩气和氧气的混合气体，其比例为9:1，气体流量为50sccm，反应室气压为5.26*104Pa，衬底温度为250摄氏度，射频源功率为2W/cm2，所形成的氧化层的厚度可以大于30埃。Refer to Figure 6. A barrier layer 302 is formed on the polysilicon layer of the second dummy gate exposed after the planarization step. In one embodiment, the barrier layer is formed on the polysilicon layer of the dummy gate of the NFET region. The blocking layer may be an oxide layer or a nitride layer formed on the polysilicon layer, and a method of plasma oxidation or nitriding and ion implantation may be used. The method for plasma oxidation in one embodiment is carried out in the system of PECVD, and its radio frequency original frequency is 13.56Hz, and gas source is the mixed gas of argon and oxygen, and its ratio is 9:1, and gas flow rate is 50sccm, and reaction The pressure of the chamber is 5.26*104Pa, the temperature of the substrate is 250 degrees Celsius, and the power of the radio frequency source is 2W/cm2, and the thickness of the formed oxide layer can be greater than 30 angstroms.
参照图7。然后进行去除掩模层301的步骤。其条件包括在反应腔中通入O2。在一个实施例中，还包括通入的混合气体，其包括适量的N2和H2，以增加离子浓度从而加快去除的速率。Refer to Figure 7. A step of removing the mask layer 301 is then performed. The conditions include feeding O2 into the reaction chamber. In one embodiment, a mixed gas is also included, which includes an appropriate amount of N2 and H2, so as to increase the concentration of ions so as to accelerate the removal rate.
以上步骤完成之后，所形成于伪栅极结构的多晶硅层上的氧化层的厚度将会具有不同的厚度，其还包括自然氧化层。在一个实施例中所观察到的氧化层包括大约10埃的自然氧化层和在PFET区域的约30埃的二次生长的氧化层。After the above steps are completed, the thickness of the oxide layer formed on the polysilicon layer of the dummy gate structure will have different thicknesses, which also includes the natural oxide layer. The oxide observed in one embodiment included approximately 10 Angstroms of native oxide and approximately 30 Angstroms of secondary grown oxide in the PFET region.
接着进行去除自然氧化层的步骤和用湿刻蚀的方法去除第一伪栅极结构的多晶硅层的步骤。在本发明的实施例中，利用稀释的氢氟酸（DHF）工艺把自然氧化层腐蚀掉，HF：H2O的体积比可以为1：（10-200），处理温度为20-25摄氏度，该工艺可以使自然氧化层的腐蚀终止于氧含量很低的多晶硅层表面。Then perform the step of removing the natural oxide layer and the step of removing the polysilicon layer of the first dummy gate structure by wet etching. In the embodiment of the present invention, the natural oxide layer is corroded by dilute hydrofluoric acid (DHF), the volume ratio of HF:H2O can be 1: (10-200), and the treatment temperature is 20-25 degrees Celsius. The process can stop the corrosion of the natural oxide layer on the surface of the polysilicon layer with very low oxygen content.
可以利用四甲基氢氧化铵（TMAH）来去除第一伪栅极的多晶硅层。一个实施例中使用浓度为22%wt的四甲基氢氨水溶液来去除NFET区域伪栅极的多晶硅层。在另外的实施例中，还使用各向异性腐蚀液（KTMAH）来去除多晶硅层，在TMAH水溶液中加入氢氧化钾（KOH），其中TMAH的质量分数为10%-25%、TMAH与KOH的摩尔比为2-4，反应的温度为60-90摄氏度。从而第一伪栅极的多晶硅层可以被去除以形成沟槽，如图8所示。The polysilicon layer of the first dummy gate may be removed using tetramethylammonium hydroxide (TMAH). In one embodiment, the polysilicon layer of the dummy gate in the NFET region is removed by using an aqueous solution of tetramethylhydrogen ammonia with a concentration of 22%wt. In another embodiment, anisotropic etching solution (KTMAH) is also used to remove the polysilicon layer, and potassium hydroxide (KOH) is added to the TMAH aqueous solution, wherein the mass fraction of TMAH is 10%-25%, the ratio of TMAH and KOH The molar ratio is 2-4, and the reaction temperature is 60-90 degrees Celsius. Therefore, the polysilicon layer of the first dummy gate can be removed to form a trench, as shown in FIG. 8 .
其中以上去除自然氧化物和去除第一伪栅极结构的多晶硅层的步骤可以在同一个反应腔中进行以减少器件的移动从而减少损伤的几率。The above steps of removing the natural oxide and removing the polysilicon layer of the first dummy gate structure can be performed in the same reaction chamber to reduce the movement of the device and thus reduce the probability of damage.
由于上述在第二伪栅极所暴露的多晶硅层上形成的阻挡层具有一定的厚度，且本发明的湿刻蚀对其刻蚀的作用有限，所以其可以保护其下方的多晶硅层，使得具有高选择性的刻蚀方法能够应用在第一伪栅极多晶硅层的去除步骤中。Since the above-mentioned barrier layer formed on the polysilicon layer exposed by the second dummy gate has a certain thickness, and the wet etching of the present invention has a limited effect on its etching, it can protect the polysilicon layer below it, so that it has A highly selective etching method can be applied in the step of removing the polysilicon layer of the first dummy gate.
然后在去除第一伪栅极多晶硅层而形成的沟槽中填充栅极材料以形成栅极，可以是填充金属材料以形成金属栅。在一个实施例中的金属栅还可以包括：TiN、TaN、TiN和TaN和上述的组合功函数金属层；TaN、TiN、TaC、TaSiN、WN、TiAl、TiAlN或上述的组合的阻挡层；和导电层等。形成栅极的方法可以包括沉积、退火和平坦化等步骤。Then fill the trench formed by removing the polysilicon layer of the first dummy gate to form a gate, which may be filled with a metal material to form a metal gate. The metal gate in one embodiment may also include: TiN, TaN, TiN and TaN and the above-mentioned combined work function metal layer; TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or a barrier layer of the above-mentioned combination; and conductive layer, etc. A method of forming a gate may include deposition, annealing, and planarization.
然后进行去除第二伪栅极多晶硅层以形成沟槽的步骤以及填充所述沟槽形成栅极的步骤。Then the steps of removing the second dummy gate polysilicon layer to form a trench and filling the trench to form a gate are performed.
然后进行后续工艺以完成半导体元件的制造。Subsequent processes are then performed to complete the fabrication of the semiconductor element.
为了说明和描述的目的，给出了本发明各个方面的以上描述。其并不旨在穷尽列举或将本发明限制为所公开的精确形式，且明显地，可以进行多种修改和变化。本发明旨在将对本领域技术人员是显而易见的这些修改和变化包括在由所附权利要求限定的本发明的范围内。The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and changes are possible. The present invention is intended to include within the scope of the present invention such modifications and variations as would be apparent to those skilled in the art.
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