技术领域technical field
本发明涉及超大规模集成电路制造领域，主要涉及一种适用于超高集成度集成电路制造的源栅漏共同控制型单掺杂型隧穿场效应晶体管。The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and mainly relates to a source-gate-drain common control type single-doped tunneling field-effect transistor suitable for ultra-high-integration integrated circuit manufacturing.
背景技术Background technique
PIN型隧穿场效应晶体管(TFETs), 通过引入化合物半导体、锗化硅或锗等禁带宽度更窄的材料来生成器件的隧穿部分，以及通过引入高介电常数的绝缘物质作为栅电极介质层，对比传统金属氧化物半导体场效应晶体管（MOSFETs），PIN型隧穿场效应晶体管具备更好的开关特性及更低的功耗，因此可以取代MOSFETs器件而成为下一代超大规模集成电路逻辑单元或存储单元。PIN-type tunneling field-effect transistors (TFETs), the tunneling part of the device is generated by introducing materials with narrower band gaps such as compound semiconductors, silicon germanium or germanium, and by introducing high dielectric constant insulating substances as gate electrodes Dielectric layer, compared with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs), PIN-type tunneling field-effect transistors have better switching characteristics and lower power consumption, so they can replace MOSFETs devices and become the next generation of VLSI logic unit or storage unit.
然而由于在热处理的过程当中，重掺杂的P区或N区会发生再次扩散，因此，随着器件尺寸的不断缩小，要想在几十或十几个纳米的尺寸下实现PIN结构，对于掺杂工艺和热处理工艺的要求极高。However, due to the re-diffusion of the heavily doped P region or N region during the heat treatment process, as the size of the device continues to shrink, it is necessary to realize the PIN structure at a size of tens or tens of nanometers. The doping process and heat treatment process are extremely demanding.
发明内容Contents of the invention
发明目的purpose of invention
为解决上述问题，本发明提出了一种利用源电极、栅电极和漏电极共同控制来实现的无需生成物理PIN结构的单掺杂型隧穿场效应晶体管，有效避免了普通隧穿晶体管对于深纳米尺度下的重掺杂PIN结在热处理工艺过程当中会发生再次扩散的这一技术难题。In order to solve the above-mentioned problems, the present invention proposes a single-doped tunneling field-effect transistor that is realized by using the common control of the source electrode, the gate electrode and the drain electrode without generating a physical PIN structure, effectively avoiding the common tunneling transistor for deep The technical problem that the heavily doped PIN junction at the nanometer scale will diffuse again during the heat treatment process.
技术方案Technical solutions
本发明是通过以下技术方案来实现的：The present invention is achieved through the following technical solutions:
一种源栅漏共控单掺杂型隧穿晶体管，包括SOI晶圆硅衬底，SOI晶圆硅衬底上方为SOI晶圆绝缘层，其特征在于：SOI晶圆绝缘层上方为半导体薄膜，半导体薄膜上方一侧为源电极，另一侧为漏电极，中间为绝缘介质层，半导体薄膜与绝缘介质层之间靠近源电极位置处为窄禁带宽度半导体薄膜区；绝缘介质层上方为层间隔离绝缘介质，绝缘介质层与层间隔离绝缘介质之间为栅电极。A source-gate-drain common-controlled single-doped tunneling transistor, comprising an SOI wafer silicon substrate, an SOI wafer insulating layer above the SOI wafer silicon substrate, characterized in that: a semiconductor film is placed above the SOI wafer insulating layer , one side above the semiconductor film is the source electrode, the other side is the drain electrode, and the middle is an insulating dielectric layer. The semiconductor film and the insulating dielectric layer are close to the source electrode. The interlayer isolating insulating medium, and the gate electrode is between the insulating medium layer and the interlayer isolating insulating medium.
源电极除与半导体薄膜的源极部分连接之外，还附着于栅电极绝缘介质层的临近源极一侧的上方。In addition to being connected to the source portion of the semiconductor thin film, the source electrode is also attached above the side of the gate electrode insulating medium layer close to the source.
漏电极除与半导体薄膜的漏极部分连接之外，还附着于绝缘介质层的临近漏极一侧的上方。In addition to being connected to the drain part of the semiconductor thin film, the drain electrode is also attached above the side of the insulating dielectric layer adjacent to the drain.
绝缘介质层为二氧化硅或具有高介电常数的绝缘介质。The insulating medium layer is silicon dioxide or insulating medium with high dielectric constant.
窄禁带宽度半导体薄膜区为具有窄禁带宽度的半导体材料。The narrow band gap semiconductor thin film region is a semiconductor material with a narrow band gap.
窄禁带宽度半导体薄膜区为锗、锗化硅或碳化硅。The semiconductor thin film region with narrow band gap is germanium, silicon germanium or silicon carbide.
优点及效果Advantages and effects
本发明具有如下优点及有益效果：The present invention has following advantage and beneficial effect:
由于本发明所提出的单掺杂型隧穿场效应晶体管不需要生成普通隧穿晶体管的PIN结构,而是通过源电极、栅电极和漏电极的共同控制下生成虚拟PIN结构，因而避免了普通隧穿晶体管对于深纳米尺度下的重掺杂PIN结在热处理工艺过程当中会发生再次扩散的这一技术难题。Since the single-doped tunneling field effect transistor proposed in the present invention does not need to generate the PIN structure of the ordinary tunneling transistor, but generates a virtual PIN structure under the common control of the source electrode, the gate electrode and the drain electrode, thereby avoiding the common Tunneling transistors have the technical problem of re-diffusion during the heat treatment process for heavily doped PIN junctions at deep nanometer scales.
附图说明Description of drawings
图1为本发明这种源栅漏共同控制的单掺杂型隧穿场效应薄膜晶体管在SOI衬底上形成的二维结构示意图。图中沟道的隧穿部分以锗化硅为例。FIG. 1 is a schematic diagram of a two-dimensional structure of a single-doped tunneling field-effect thin film transistor with common source-gate-drain control in the present invention formed on an SOI substrate. The tunneling part of the channel in the figure is exemplified by silicon germanium.
图2至图9为制备本发明这种源栅漏共同控制的单掺杂型隧穿场效应薄膜晶体管及其阵列的具体工艺流程图。FIG. 2 to FIG. 9 are specific process flow charts for preparing the single-doped tunneling field-effect thin film transistor with common source-gate-drain control and its array according to the present invention.
附图标记说：The reference sign says:
1、源电极；2、半导体薄膜；3、窄禁带宽度半导体薄膜区；4、漏电极；5、绝缘介质层；6、栅电极；7、层间隔离绝缘介质；8、SOI晶圆绝缘层；9、SOI晶圆硅衬底。1. Source electrode; 2. Semiconductor thin film; 3. Narrow band gap semiconductor thin film region; 4. Drain electrode; 5. Insulating medium layer; 6. Gate electrode; 7. Interlayer isolation insulating medium; 8. SOI wafer insulation Layer; 9, SOI wafer silicon substrate.
具体实施方式detailed description
下面结合附图对本发明做进一步的说明：Below in conjunction with accompanying drawing, the present invention will be further described:
本发明是一种利用源电极、栅电极和漏电极共同控制来实现无需生成物理PIN结构的单掺杂型隧穿场效应晶体管。所述的隧穿场效应晶体管，只需生成P型或N型的单掺杂结构，通过采用源电极、栅电极和漏电极的共同控制半导体薄膜各个区域的载流子分布类型的方法来实现虚拟的PIN结，因此避免了普通隧穿晶体管对于深纳米尺度下的重掺杂PIN结在热处理工艺过程当中会发生再次扩散的这一技术难题。The invention is a single-doped tunneling field effect transistor which realizes no physical PIN structure by utilizing common control of the source electrode, the gate electrode and the drain electrode. The tunneling field effect transistor only needs to generate a P-type or N-type single-doped structure, which is realized by using the method of jointly controlling the carrier distribution type of each region of the semiconductor thin film by using the source electrode, the gate electrode and the drain electrode. The virtual PIN junction thus avoids the technical problem of re-diffusion in the heat treatment process of the heavily doped PIN junction in the deep nanoscale of ordinary tunneling transistors.
本发明这种源栅漏共控单掺杂型隧穿晶体管，包括SOI晶圆硅衬底9，SOI晶圆硅衬底9上方为SOI晶圆绝缘层8，其特征在于：SOI晶圆绝缘层8上方为半导体薄膜2，半导体薄膜2上方一侧为源电极1，另一侧为漏电极4，中间为绝缘介质层5，半导体薄膜2与绝缘介质层5之间靠近源电极位置处为窄禁带宽度半导体薄膜区3；绝缘介质层5上方为层间隔离绝缘介质7，绝缘介质层5与层间隔离绝缘介质7之间为栅电极6。The source-gate-drain common-controlled single-doped tunneling transistor of the present invention includes an SOI wafer silicon substrate 9, an SOI wafer insulating layer 8 is formed above the SOI wafer silicon substrate 9, and is characterized in that: the SOI wafer insulating layer 8 Above the layer 8 is a semiconductor thin film 2, one side above the semiconductor thin film 2 is a source electrode 1, the other side is a drain electrode 4, and the middle is an insulating dielectric layer 5, and the position between the semiconductor thin film 2 and the insulating dielectric layer 5 near the source electrode is Narrow bandgap semiconductor thin film region 3; above the insulating dielectric layer 5 is an interlayer isolation insulating dielectric 7, and between the insulating dielectric layer 5 and the interlayer isolation insulating dielectric 7 is a gate electrode 6.
源电极1除与半导体薄膜2的源极部分连接之外，还附着于绝缘介质层5的临近源极一侧的上方，使其对半导体硅薄膜2的源极部分的电场和载流子分布具有一定控制作用。在器件工作时对源电极1施加反向电压，这样临近源电极1一侧的半导体硅薄膜2形成空穴反型层，通过调节源电极1的反向电压大小可使空穴反型层的浓度远大于掺杂浓度，并以此实现虚拟的重掺杂P区，同时降低半导体硅薄膜2临近源电极一侧的源极电阻的大小。In addition to being connected to the source electrode part of the semiconductor film 2, the source electrode 1 is also attached to the top of the insulating medium layer 5 near the source electrode side, so that the electric field and carrier distribution of the source electrode part of the semiconductor silicon film 2 Has a certain control effect. When the device is working, a reverse voltage is applied to the source electrode 1, so that the semiconductor silicon film 2 adjacent to the source electrode 1 forms a hole inversion layer, and the hole inversion layer can be made by adjusting the reverse voltage of the source electrode 1. The concentration is much higher than the doping concentration, so as to realize a virtual heavily doped P region and reduce the source resistance of the semiconductor silicon film 2 adjacent to the source electrode.
漏电极4除与半导体薄膜2的漏极部分连接之外，还附着于绝缘介质层5的临近漏极一侧的上方，使其对半导体薄膜2的漏极部分的电场和载流子分布具有一定控制作用。在器件工作时对漏电极4施加正向电压，这样临近漏电极4一侧的半导体硅薄膜2形成电子积累层，通过调节漏电极4的正向电压大小可使电子积累层的浓度远大于掺杂浓度，并以此实现虚拟的重掺杂N区，同时降低半导体硅薄膜2临近漏电极一侧的漏极电阻的大小。Drain electrode 4 is except being connected with the drain electrode part of semiconductor thin film 2, is also attached to the top of the side near the drain electrode of insulating medium layer 5, makes it to the electric field of the drain electrode part of semiconductor thin film 2 and carrier distribution. Definitely control. When the device is working, a forward voltage is applied to the drain electrode 4, so that the semiconductor silicon film 2 near the drain electrode 4 forms an electron accumulation layer. By adjusting the forward voltage of the drain electrode 4, the concentration of the electron accumulation layer can be much higher than that of doped impurity concentration, and thereby realize a virtual heavily doped N region, and at the same time reduce the size of the drain resistance of the side of the semiconductor silicon film 2 adjacent to the drain electrode.
通过调节栅电极6上所施加的电压，使得位于栅电极6下方的窄禁带宽度半导体薄膜区3实现载流子的耗尽，以此实现虚拟的本征区。通过与源电极1和漏电极4的共同控制作用，实现虚拟的P-I-N结构。通过调节栅电极6的电压来调节窄禁带宽度半导体薄膜区3的能带弯曲程度以控制隧穿电流的大小。By adjusting the voltage applied to the gate electrode 6 , the narrow bandgap semiconductor film region 3 located below the gate electrode 6 is depleted of carriers, thereby realizing a virtual intrinsic region. A virtual P-I-N structure is realized through the joint control with the source electrode 1 and the drain electrode 4 . By adjusting the voltage of the gate electrode 6 to adjust the band bending degree of the narrow bandgap semiconductor thin film region 3 to control the size of the tunneling current.
上述绝缘介质层5为二氧化硅或具有高介电常数的绝缘介质，如：二氧化铪、四氮化三硅或三氧化二铝等。采用介电常数较高的绝缘介质层5可以增强源电极1、栅电极6和漏电极4对半导体薄膜2和窄禁带宽度半导体薄膜区3的电场分布、载流子分布以及能带弯曲程度的控制能力。The insulating medium layer 5 is silicon dioxide or an insulating medium with a high dielectric constant, such as hafnium dioxide, silicon nitride or aluminum oxide. The electric field distribution, carrier distribution and energy band bending degree of the source electrode 1, the gate electrode 6 and the drain electrode 4 to the semiconductor thin film 2 and the narrow bandgap semiconductor thin film region 3 can be enhanced by adopting an insulating medium layer 5 with a higher dielectric constant control ability.
上述窄禁带宽度半导体薄膜区3为锗、锗化硅或碳化硅等具有较窄禁带宽度的单晶或化合物半导体材料。The narrow bandgap semiconductor thin film region 3 is a single crystal or compound semiconductor material with a narrow bandgap, such as germanium, silicon germanium or silicon carbide.
本发明工作过程如下：The working process of the present invention is as follows:
以N极为例，在器件工作时，源电极1施加反向电压，使半导体薄膜2与源电极1临近的一侧电子耗尽，并在表面形成浓度大于半导体薄膜2掺杂浓度的空穴反型层；漏电极4施加正向电压，使半导体薄膜2与漏电极4临近的一侧电子积累，并在表面形成浓度大于半导体薄膜2掺杂浓度的电子积累层；通过调节栅电极6的电压，在单掺杂的N型半导体薄膜2上形成虚拟的P-I-N结构。Taking the N pole as an example, when the device is working, the source electrode 1 applies a reverse voltage to deplete the electrons on the side of the semiconductor film 2 adjacent to the source electrode 1, and form a hole reflection layer with a concentration greater than the doping concentration of the semiconductor film 2 on the surface. type layer; the drain electrode 4 applies a forward voltage, so that the semiconductor film 2 and the side near the drain electrode 4 accumulate electrons, and form an electron accumulation layer with a concentration greater than the doping concentration of the semiconductor film 2 on the surface; by adjusting the voltage of the gate electrode 6 , forming a virtual P-I-N structure on the single-doped N-type semiconductor thin film 2 .
在器件工作时，源电极1施加反向电压，漏电极4施加正向电压，使半导体薄膜2的两端分别形成空穴反型层和电子积累层，因此分别降低了源漏电阻的大小。When the device is working, the source electrode 1 applies a reverse voltage, and the drain electrode 4 applies a forward voltage, so that the two ends of the semiconductor film 2 form a hole inversion layer and an electron accumulation layer, respectively, thereby reducing the size of the source and drain resistance respectively.
当栅电极6所施加的电压较低时，窄禁带宽度半导体薄膜区3的能带弯曲程度较小，此时器件处于关断状态；随着栅电极6所施加的电压逐渐升高，窄禁带宽度半导体薄膜区3的能带弯曲程度也随之增加，隧穿电流亦随之增大；当栅电极6施加较高电压时，窄禁带宽度半导体薄膜区3的能带弯曲程度剧烈，此时器件处于开启状态。When the applied voltage of the gate electrode 6 was low, the energy band bending degree of the narrow bandgap semiconductor thin film region 3 was small, and the device was in an off state; The energy band bending degree of the semiconductor thin film region 3 with the forbidden band width also increases thereupon, and the tunneling current also increases thereupon; when a higher voltage is applied to the gate electrode 6, the energy band bending degree of the narrow bandgap semiconductor thin film region 3 is sharp , when the device is on.
为方便说明各区域之间的相互及相邻位置关系，示意图及工艺流程图中各区域特征尺寸并不代表实际尺寸。且本发明所示实例仅仅是实现本发明所提出的源栅漏共控单掺杂型隧穿晶体管中的一种。由于工艺制造偏差所引起的形变均应被认为是本发明的范围之内。In order to facilitate the description of the mutual and adjacent positional relationship between each area, the characteristic dimensions of each area in the schematic diagram and process flow chart do not represent the actual size. And the example shown in the present invention is only one of the source-gate-drain common-controlled single-doped tunneling transistors proposed in the present invention. Deformations caused by process manufacturing deviations should be considered within the scope of the present invention.
上述源栅漏共控单掺杂型隧穿晶体管的制造方法，步骤如下：The manufacturing method of the above-mentioned source-gate-drain common-controlled single-doped tunneling transistor is as follows:
如图2所示，提供一个SOI衬底，将上方的半导体薄膜2减薄至30nm以下，利用光刻、刻蚀等工艺刻蚀掉用做隧道跃迁的部分。As shown in FIG. 2 , an SOI substrate is provided, and the upper semiconductor thin film 2 is thinned to below 30nm, and the part used for the tunnel transition is etched away by photolithography, etching and other processes.
如图3所示，通过外延生长及刻蚀工艺，生成窄禁带宽度半导体薄膜区3，例如：锗化硅。As shown in FIG. 3 , a semiconductor film region 3 with a narrow bandgap width, such as silicon germanium, is formed through epitaxial growth and etching processes.
如图4所示，进一步刻出单元之间的隔离部分，并通过淀积二氧化硅或氮化硅来填充隔离部分以形成单元间的层间隔离绝缘介质7；抛平后刻蚀掉半导体薄膜2上方的绝缘层部分。As shown in Figure 4, further carve out the isolation part between the units, and fill the isolation part by depositing silicon dioxide or silicon nitride to form the interlayer isolation insulating dielectric 7 between the units; etch away the semiconductor after flattening Part of the insulating layer above the film 2.
如图5所示，淀积高介电常数绝缘介质以生成绝缘介质层5，如：二氧化铪、四氮化三硅或三氧化二铝等。在晶圆上方对半导体薄膜2进行离子注入以形成N型或P型掺杂，并刻蚀掉如图所示部分，用于源电极1、漏电极4的生成。As shown in FIG. 5 , an insulating dielectric layer 5 with a high dielectric constant is deposited to form an insulating dielectric layer 5 , such as hafnium dioxide, silicon nitride or aluminum oxide. Ion implantation is performed on the semiconductor thin film 2 above the wafer to form N-type or P-type doping, and the portion shown in the figure is etched away for the generation of the source electrode 1 and the drain electrode 4 .
如图6所示，通过金属淀积和刻蚀工艺，生成源电极1和漏电极4。As shown in FIG. 6, a source electrode 1 and a drain electrode 4 are formed through metal deposition and etching processes.
如图7所示，淀积二氧化硅或氮化硅，并通过刻蚀工艺将用作生成栅电极的部分去掉。以此形成栅电极6与源电极1和漏电极4之间的层间隔离绝缘介质7。As shown in FIG. 7, silicon dioxide or silicon nitride is deposited, and the portion used to form the gate electrode is removed by an etching process. In this way, an interlayer insulating insulating medium 7 between the gate electrode 6 and the source electrode 1 and the drain electrode 4 is formed.
如图8所示，通过淀积多晶硅和刻蚀工艺生成栅电极6。As shown in FIG. 8, the gate electrode 6 is formed by depositing polysilicon and etching processes.
如图9所示，淀积的层间隔离绝缘介质7在源电极1和漏电极4的上方，通过刻蚀工艺生成源电极1、漏电极4的通孔，并注入金属以进一步生成源电极1和漏电极4。As shown in Figure 9, the deposited interlayer isolation insulating dielectric 7 is above the source electrode 1 and the drain electrode 4, and the through holes of the source electrode 1 and the drain electrode 4 are formed through an etching process, and metal is implanted to further form the source electrode 1 and the drain electrode 4.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310508661.0ACN103531636B (en) | 2013-10-25 | 2013-10-25 | Source grid leak controls single doping type tunneling transistor altogether |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310508661.0ACN103531636B (en) | 2013-10-25 | 2013-10-25 | Source grid leak controls single doping type tunneling transistor altogether |
| Publication Number | Publication Date |
|---|---|
| CN103531636A CN103531636A (en) | 2014-01-22 |
| CN103531636Btrue CN103531636B (en) | 2017-12-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310508661.0AExpired - Fee RelatedCN103531636B (en) | 2013-10-25 | 2013-10-25 | Source grid leak controls single doping type tunneling transistor altogether |
| Country | Link |
|---|---|
| CN (1) | CN103531636B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409489B (en)* | 2014-12-08 | 2017-04-26 | 沈阳工业大学 | High-integrated groove insulated gate tunneling bipolar enhancement transistor and manufacture method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355102A (en)* | 2007-07-25 | 2009-01-28 | 台湾积体电路制造股份有限公司 | A semiconductor device and method of forming the semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8441000B2 (en)* | 2006-02-01 | 2013-05-14 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
| US20090034355A1 (en)* | 2007-07-30 | 2009-02-05 | Qimonda Ag | Integrated circuit including memory cells with tunnel fet as selection transistor |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355102A (en)* | 2007-07-25 | 2009-01-28 | 台湾积体电路制造股份有限公司 | A semiconductor device and method of forming the semiconductor device |
| Publication number | Publication date |
|---|---|
| CN103531636A (en) | 2014-01-22 |
| Publication | Publication Date | Title |
|---|---|---|
| US8860140B2 (en) | Tunneling field effect transistor and method for forming the same | |
| CN102983168B (en) | Tunneling field effect transistor with double-diffused strip gate and preparation method thereof | |
| CN103594376B (en) | A kind of knot modulation type tunneling field-effect transistor and preparation method thereof | |
| WO2011066726A1 (en) | Hybrid material accumulation mode cmos fet with entirely surrounding cylindrical gate | |
| CN102664192B (en) | Self-adaptive composite mechanism tunneling field effect transistor (TFET) and preparation method thereof | |
| CN102945861B (en) | Strip grate modulation type tunneling field-effect transistor and preparation method thereof | |
| WO2012116528A1 (en) | Tunneling field effect transistor and method for forming the same | |
| US20140097402A1 (en) | Semiconductor structure and method for forming the same | |
| CN103500758A (en) | Semi-gate controlled source schottky barrier type tunneling field effect transistor | |
| WO2016150335A1 (en) | Tunnelling field effect transistor and manufacturing method therefor | |
| CN103579324A (en) | Three-face-source tunneling field effect transistor and manufacturing method thereof | |
| CN103560144B (en) | Suppress the method for tunneling transistor leakage current and corresponding device and preparation method | |
| CN105633147A (en) | Tunneling field effect transistor and manufacturing method thereof | |
| CN104282750B (en) | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid | |
| CN104576721B (en) | A kind of tunneling field-effect transistor with electric field localization effects enhancing ON state current | |
| CN103531592B (en) | Three gate control type nodeless mesh body pipes of high mobility low source and drain resistance | |
| CN107611170A (en) | Longitudinal tunneling field-effect transistor of ON state current enhancing | |
| CN106558493B (en) | Method for forming fin field effect transistor | |
| CN103531636B (en) | Source grid leak controls single doping type tunneling transistor altogether | |
| CN102364690A (en) | A kind of tunneling field effect transistor and its preparation method | |
| CN103545375B (en) | The discrete control type non-impurity-doped field-effect transistor of the nearly nearly drain-gate of source grid | |
| CN104538443B (en) | The high-performance SOI nodeless mesh body pipes of non-single insulated substrate thickness degree | |
| CN104282754B (en) | High integration L-shaped grid-control Schottky barrier tunneling transistor | |
| CN107819036A (en) | Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacture method | |
| WO2013063975A1 (en) | Tunneling field effect transistor structure and forming method thereof |
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | Granted publication date:20171201 Termination date:20181025 | |
| CF01 | Termination of patent right due to non-payment of annual fee |