CN103531542B - Reduce the cmos device manufacture method of Negative Bias Temperature Instability - Google Patents

Abstract

Translated fromChinese

一种减小负偏压温度不稳定性的CMOS器件制作方法，包括：第一步骤，在衬底中进行阱注入形成P型阱以及N型阱；第二步骤，在衬底表面制作栅极氧化层；第三步骤，在栅极氧化层表面进行栅极层的淀积；第四步骤，对栅极层进行光刻以形成在P型阱上形成PMOS栅极，在N型阱上形成NMOS栅极；第五步骤，在PMOS栅极和NMOS栅极的侧边分别制作栅极侧墙一；第六步骤，进行轻掺杂注入在P型阱中形成PMOS轻掺杂源漏结构，并在N型阱中形成NMOS轻掺杂源漏结构；第七步骤，在器件表面淀积氮化硅薄膜；第八步骤，利用UV光对硅片进行照射；第九步骤，在栅极侧墙一侧边制作形成侧墙二；第十步骤，进行源漏注入形成，从而在P型阱中形成PMOS源漏极，在N型阱中形成NMOS源漏极。

A CMOS device manufacturing method for reducing negative bias temperature instability, comprising: a first step, performing well implantation in a substrate to form a P-type well and an N-type well; a second step, making a gate on the surface of the substrate Oxide layer; the third step is to deposit the gate layer on the surface of the gate oxide layer; the fourth step is to perform photolithography on the gate layer to form a PMOS gate on the P-type well, and form a PMOS gate on the N-type well. NMOS gate; the fifth step is to make gate spacers on the sides of the PMOS gate and the NMOS gate respectively; the sixth step is to perform lightly doped implantation to form a PMOS lightly doped source-drain structure in the P-type well, And form an NMOS lightly doped source-drain structure in the N-type well; the seventh step is to deposit a silicon nitride film on the surface of the device; the eighth step is to irradiate the silicon wafer with UV light; the ninth step is to Fabricate one side of the wall to form side wall two; the tenth step is to perform source and drain implantation to form PMOS source and drain in the P-type well, and form NMOS source and drain in the N-type well.

Description

Translated fromChinese

减小负偏压温度不稳定性的CMOS器件制作方法CMOS Device Manufacturing Method for Reducing Negative Bias Temperature Instability

技术领域technical field

本发明涉及半导体制造领域，更具体地说，本发明涉及一种减小负偏压温度不稳定性(NBTI：NegativeBiasTemperatureInstability)的CMOS器件制作方法。The present invention relates to the field of semiconductor manufacturing, and more specifically, the present invention relates to a CMOS device manufacturing method that reduces negative bias temperature instability (NBTI: NegativeBiasTemperatureInstability).

背景技术Background technique

随着超大规模集成电路技术的迅速发展，MOSFET器件的尺寸在不断减小。由于MOSFET晶体管尺寸的急剧减小，栅氧化层的厚度减小至2nm甚至更薄。在MOS器件按比例缩小尺寸的同时，工作电压并未相应地等比例降低，这使得MOS器件的沟道电场和氧化层电场显著增加，NBTI效应引起的退化日益显著。NBTI，即负偏压温度不稳定性，通常指PMOS管在高温、强场负栅压作用下表现得器件性能退化。电性温度在80-250度的范围内，如图1所示。NBTI退化表现为器件的关态电流(Ioff)增大，阈值电压(Vth)负向漂移，跨导(Gm)和漏电流(Ids)减小等。此外，为了提高晶体管性能，减小栅氧化层的漏电流，在栅氧化层中引入N原子已经成为一种工艺标准，但是，N原子的引入在一定程度上加剧了器件NBTI退化。With the rapid development of VLSI technology, the size of MOSFET devices is constantly decreasing. Due to the drastic reduction in the size of MOSFET transistors, the thickness of the gate oxide layer has been reduced to 2nm or even thinner. While the size of the MOS device is scaled down, the operating voltage is not proportionally reduced, which makes the channel electric field and the oxide layer electric field of the MOS device significantly increased, and the degradation caused by the NBTI effect is becoming more and more significant. NBTI, that is, negative bias temperature instability, usually refers to the performance degradation of PMOS transistors under the action of high temperature and strong field negative gate voltage. The electrical temperature is in the range of 80-250 degrees, as shown in Figure 1. NBTI degradation manifests as an increase in the off-state current (Ioff) of the device, a negative shift in the threshold voltage (Vth), and a decrease in transconductance (Gm) and leakage current (Ids). In addition, in order to improve the transistor performance and reduce the leakage current of the gate oxide layer, the introduction of N atoms into the gate oxide layer has become a process standard. However, the introduction of N atoms aggravates the NBTI degradation of the device to a certain extent.

在对NBTI退化机理的研究中，普遍认为是SiO₂/Si界面发生的Si的悬挂键引起的。在NBTI应力过程中，氧化层固定电荷和由于表面空穴参与而产生的界面陷阱(Si3ΞSi·)是引起NBTI效应的主要原因。而在固定电荷和界面陷阱造成的NBTI效应中Si-H键都起了关键的作用。在NBTI应力条件下，空穴在电场的作用下可以使Si-H键分解，从而形成界面陷阱，如图2A和图2B所示，造成器件的退化。反应方程式如下：In the research on the degradation mechanism of NBTI, it is generally believed that it is caused by the dangling bonds of Si occurring at the interface of SiO₂ /Si. During the NBTI stress process, the fixed charge of the oxide layer and the interface traps (Si3ΞSi·) generated due to the participation of surface holes are the main reasons for the NBTI effect. The Si-H bond plays a key role in the NBTI effect caused by fixed charges and interface traps. Under the NBTI stress condition, the holes can decompose the Si-H bond under the action of the electric field, thereby forming interface traps, as shown in Figure 2A and Figure 2B, resulting in the degradation of the device. The reaction equation is as follows:

界面陷拼Si₃≡SiH→Si₃≡Si·十H⁰Interfacial trap Si₃ ≡SiH→Si₃ ≡Si·+H⁰

Si₃≡SiH十H+→Si₃→Si·十H₂Si₃ ≡SiH+H+→Si₃ →Si·+H₂

氧化层电荷O₃→SiH→O₃≡Si·十H⁰Oxide charge O₃ →SiH→O₃ ≡Si·+H⁰

O₃三SiH十H+→O₃≡Si·十H₂O₃ triSiH+H+→O₃ ≡Si·+H₂

但是，在CMOS器件栅氧化层中H作为固定电荷和界面陷阱中Si的主要成键物质，是最常见和不可避免的杂质，并在NBTI反应过程中起主要作用。在现在的CMOS工艺流程中，已经采取了相关措施来抑制NBTI效应。比如在SiO₂/Si界面处通过氘(D)的缺陷钝化，在提高器件可靠性方面有很大优势。因为根据动态同位素效应，打破与氘形成的Si-D键比与氢形成的Si-H键更困难一些。但是在工艺中实现这种钝化中也存在着重要的问题。在已有的生产线上，通常是通过在通孔形成之后的氘气退火来完成界面的氘化，但是在生产线中后段执行界面的氘化。另外一种方法是，通过减少器件制作工艺中H的引入来减少SiO₂/Si界面处的Si-H键数目也能显著提高器件的NBTI性能。但是由于在器件的制作过程中，许多工艺中诸如膜淀积、刻蚀、离子注入和清洗等中存在氢，这些氢在热预算的驱动下，会扩散到SiO₂/Si界面，与Si悬挂键结合形成Si-H键，从而加剧了NBTI效应However, in the gate oxide layer of CMOS devices, H, as the main bonding species of fixed charge and Si in interface traps, is the most common and unavoidable impurity, and plays a major role in the NBTI reaction process. In the current CMOS process flow, relevant measures have been taken to suppress the NBTI effect. For example, passivation of defects by deuterium (D) at the SiO₂ /Si interface has great advantages in improving device reliability. Because according to the dynamic isotope effect, it is more difficult to break the Si-D bond formed with deuterium than the Si-H bond formed with hydrogen. But there are also important problems in achieving this passivation in the process. In the existing production line, the deuteration of the interface is usually completed by deuterium annealing after the via hole is formed, but the deuteration of the interface is performed in the later stage of the production line. Another method is that reducing the number of Si-H bonds at the SiO₂ /Si interface by reducing the introduction of H in the device fabrication process can also significantly improve the NBTI performance of the device. However, due to the presence of hydrogen in many processes such as film deposition, etching, ion implantation, and cleaning during the fabrication of the device, the hydrogen will diffuse to the SiO₂ /Si interface and hang with Si under the drive of thermal budget. bonding to form Si-H bonds, thus exacerbating the NBTI effect

因此，如何提供一种能减小MOS器件制作过程中引入氢的工艺方法，从而减少SiO₂/Si界面处Si-H键的数目，进而可以提高NBTI性能，已经成为一个比较重要的问题。Therefore, how to provide a process method that can reduce the introduction of hydrogen during the fabrication of MOS devices, thereby reducing the number of Si-H bonds at the SiO₂ /Si interface, and improving the performance of NBTI has become a relatively important issue.

发明内容Contents of the invention

本发明所要解决的技术问题是针对现有技术中存在上述缺陷，提供一种能够减小负偏压温度不稳定性的CMOS器件制作方法。The technical problem to be solved by the present invention is to provide a CMOS device manufacturing method capable of reducing the temperature instability of the negative bias voltage in view of the above-mentioned defects in the prior art.

为了实现上述技术目的，根据本发明，提供了一种减小负偏压温度不稳定性的CMOS器件制作方法，其包括：In order to achieve the above technical purpose, according to the present invention, a method for manufacturing a CMOS device that reduces negative bias temperature instability is provided, comprising:

第一步骤，在衬底中进行阱注入形成P型阱以及N型阱；The first step is to perform well implantation in the substrate to form a P-type well and an N-type well;

第二步骤，在衬底表面制作栅极氧化层；The second step is to form a gate oxide layer on the surface of the substrate;

第三步骤，在栅极氧化层表面进行栅极层的淀积；The third step is to deposit a gate layer on the surface of the gate oxide layer;

第四步骤，对栅极层进行光刻以形成在P型阱上形成NMOS栅极，在N型阱上形成PMOS栅极；The fourth step is to perform photolithography on the gate layer to form an NMOS gate on the P-type well, and form a PMOS gate on the N-type well;

第五步骤，在PMOS栅极和NMOS栅极的侧边分别制作栅极侧墙一；In the fifth step, gate spacers are respectively fabricated on the sides of the PMOS gate and the NMOS gate;

第六步骤，进行轻掺杂注入在P型阱中形成NMOS轻掺杂源漏结构，并在N型阱中形成PMOS轻掺杂源漏结构；The sixth step is to perform lightly doped implantation to form an NMOS lightly doped source-drain structure in the P-type well, and form a PMOS lightly-doped source-drain structure in the N-type well;

第七步骤，在器件表面淀积氮化硅薄膜；The seventh step is to deposit a silicon nitride film on the surface of the device;

第八步骤，利用UV光对硅片进行照射；The eighth step is to irradiate the silicon wafer with UV light;

第九步骤，在栅极侧墙一侧边制作形成侧墙二；The ninth step is to form side wall two on one side of the gate side wall;

第十步骤，进行源漏注入形成，从而在P型阱中形成NMOS源漏极，在N型阱中形成PMOS源漏极。In the tenth step, source and drain implantation is performed to form an NMOS source and drain in the P-type well, and a PMOS source and drain in the N-type well.

优选地，所述减小负偏压温度不稳定性的CMOS器件制作方法还包括：第十一步骤，用于制作金属前介质、通孔、金属插塞和金属层。Preferably, the CMOS device fabrication method for reducing the temperature instability of the negative bias voltage further includes: an eleventh step for fabricating pre-metal dielectrics, via holes, metal plugs and metal layers.

优选地，在第一步骤中，通过磷掺杂形成N阱，通过B掺杂形成P阱。Preferably, in the first step, an N well is formed by phosphorus doping, and a P well is formed by B doping.

优选地，第三步骤中，淀积的栅极层的材料是多晶硅。Preferably, in the third step, the material of the deposited gate layer is polysilicon.

优选地，在第五步骤中，栅极侧墙一的形成包括多晶硅栅的氧化和SiN的淀积。Preferably, in the fifth step, the formation of the first gate spacer includes oxidation of the polysilicon gate and deposition of SiN.

优选地，第六步骤中轻掺杂杂质为氟化硼。Preferably, the lightly doped impurity in the sixth step is boron fluoride.

优选地，第八步骤中利用UV光对硅片进行照射的温度为450-480℃，照射时间为100-150S。Preferably, in the eighth step, the temperature for irradiating the silicon wafer with UV light is 450-480° C., and the irradiation time is 100-150 seconds.

优选地，第九步骤中侧墙二的形成包括氧化物的淀积，SiN的淀积以及SiN的刻蚀。Preferably, the formation of the second spacer in the ninth step includes deposition of oxide, deposition of SiN and etching of SiN.

优选地，在第十步骤中，通过P型掺杂注入形成P型的源漏极，所述P型掺杂为硼掺杂。Preferably, in the tenth step, P-type source and drain electrodes are formed by implanting P-type doping, and the P-type doping is boron doping.

本方法提供一种半导体集成电路工艺的一种新的工艺用以改善MOS器件的NBTI效应。通过在传统的半导体MOS器件制作过程中，在干法刻蚀形成第二道氮化硅侧墙前和氮化硅膜淀积之后，用UV光对晶片进行照射以去除氮化硅薄膜中的残留的一些氢原子，氢分子以及水汽，避免形成的氮化硅侧墙中的氢元素扩散到栅极氧化层下表面SiO₂/Si界面处与界面处的Si悬挂键结合，达到减小SiO₂/Si界面处Si-H键数目，从而提高MOS器件中的NBTI性能，进而提高CMOS器件性能。与传统的工艺的NBTI改善工艺相比，该工艺具有工艺简单、易于实现等特点。The method provides a new process of a semiconductor integrated circuit process to improve the NBTI effect of the MOS device. In the traditional semiconductor MOS device manufacturing process, before the second silicon nitride sidewall is formed by dry etching and after the silicon nitride film is deposited, the wafer is irradiated with UV light to remove the silicon nitride film. Some residual hydrogen atoms, hydrogen molecules and water vapor prevent the hydrogen element in the formed silicon nitride sidewall from diffusing to the SiO₂ /Si interface on the lower surface of the gate oxide layer and combine with the Si dangling bond at the interface to reduce the SiO The number of Si-H bonds at the₂ /Si interface, thereby improving the NBTI performance in MOS devices, thereby improving the performance of CMOS devices. Compared with the NBTI improvement process of the traditional process, this process has the characteristics of simple process and easy implementation.

附图说明Description of drawings

结合附图，并通过参考下面的详细描述，将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征，其中：A more complete understanding of the invention, and its accompanying advantages and features, will be more readily understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which:

图1示意性地示出了NBTI效应。Figure 1 schematically illustrates the NBTI effect.

图2A和图2B示意性地示出了Si/SiO₂界面的成键结构。Figure 2A and Figure 2B schematically show the bonding structure of the Si/_SiO2 interface.

图3示意性地示出了根据本发明优选实施例的减小负偏压温度不稳定性的CMOS器件制作方法的流程图。FIG. 3 schematically shows a flow chart of a method for fabricating a CMOS device for reducing the temperature instability of negative bias voltage according to a preferred embodiment of the present invention.

图4-图14示意性地示出了根据本发明优选实施例的减小负偏压温度不稳定性的CMOS器件制作方法的各个步骤的器件截面图。4-14 schematically show device cross-sectional views of various steps in a method for manufacturing a CMOS device for reducing the temperature instability of a negative bias voltage according to a preferred embodiment of the present invention.

需要说明的是，附图用于说明本发明，而非限制本发明。注意，表示结构的附图可能并非按比例绘制。并且，附图中，相同或者类似的元件标有相同或者类似的标号。It should be noted that the accompanying drawings are used to illustrate the present invention, but not to limit the present invention. Note that drawings showing structures may not be drawn to scale. And, in the drawings, the same or similar elements are marked with the same or similar symbols.

具体实施方式detailed description

为了使本发明的内容更加清楚和易懂，下面结合具体实施例和附图对本发明的内容进行详细描述。In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

图3示意性地示出了根据本发明优选实施例的减小负偏压温度不稳定性的CMOS器件制作方法的流程图。FIG. 3 schematically shows a flow chart of a method for fabricating a CMOS device for reducing the temperature instability of negative bias voltage according to a preferred embodiment of the present invention.

如图3所示，根据本发明优选实施例的减小负偏压温度不稳定性的CMOS器件制作方法包括：As shown in FIG. 3 , the CMOS device fabrication method for reducing negative bias temperature instability according to a preferred embodiment of the present invention includes:

首先进行第一步骤S0，在衬底中进行阱注入形成P型阱100以及N型阱200。在本实施例中，通过磷掺杂形成N阱200；通过B掺杂形成P阱100，如图4所示。Firstly, a first step S0 is performed, performing well implantation in the substrate to form a P-type well 100 and an N-type well 200 . In this embodiment, the N well 200 is formed by phosphorus doping; the P well 100 is formed by B doping, as shown in FIG. 4 .

接着进行第二步骤S1，在衬底表面制作栅极氧化层300，如图5所示。Next, a second step S1 is performed to form a gate oxide layer 300 on the surface of the substrate, as shown in FIG. 5 .

接着继续第三步骤S2，在栅极氧化层300表面进行栅极层400的淀积，例如，淀积的栅极层400的材料是多晶硅，如图6所示。Then continue to the third step S2 , depositing the gate layer 400 on the surface of the gate oxide layer 300 , for example, the material of the deposited gate layer 400 is polysilicon, as shown in FIG. 6 .

接着继续第四步骤S3，对栅极层400进行光刻以形成在P型阱100上形成NMOS栅极401，在N型阱200上形成PMOS栅极402，如图7所示。Then continue to the fourth step S3, and perform photolithography on the gate layer 400 to form an NMOS gate 401 on the P-type well 100, and form a PMOS gate 402 on the N-type well 200, as shown in FIG. 7 .

接着继续第五步骤S4，在NMOS栅极401和PMOS栅极402的侧边分别制作栅极侧墙一11、21；例如，栅极侧墙一11、12的形成包括多晶硅栅的氧化和SiN的淀积，如图8所示。Then continue to the fifth step S4, forming gate spacers 11 and 21 on the sides of the NMOS gate 401 and the PMOS gate 402 respectively; for example, the formation of the gate spacers 11 and 12 includes oxidation of the polysilicon gate and SiN deposition, as shown in Figure 8.

接着继续第六步骤S5，进行轻掺杂注入在P型阱100中形成NMOS轻掺杂源漏结构12和13，并在N型阱200中形成PMOS轻掺杂源漏结构22和23，如图9所示。在本实施例中，所述轻掺杂杂质为氟化硼。Then continue to the sixth step S5, perform light doping implantation to form NMOS lightly doped source and drain structures 12 and 13 in the P-type well 100, and form PMOS lightly doped source and drain structures 22 and 23 in the N-type well 200, as Figure 9 shows. In this embodiment, the lightly doped impurity is boron fluoride.

接着继续第七步骤S6，在器件表面淀积氮化硅薄膜500，如图10所示Then continue to the seventh step S6, depositing a silicon nitride film 500 on the surface of the device, as shown in Figure 10

接着继续第八步骤S7，利用UV光(紫外光线)对硅片进行照射，如图11所示。在本例中，通过适当温度和适当时间的UV光照射晶片用以去除氮化硅薄膜生长过程中残留的一些氢原子，氢分子和水汽。其中UV光的合适条件非常重要，优选地，温度450-480℃，时间100-150S比较合适。过低的温度不足以驱赶氢元素和水汽：过高的温度又比较容易影响前面工艺中的阱注入和轻掺杂源漏注入的离子的激活和扩散。上述条件的UV光照射可以有效地去除氮化硅薄膜中的氢原子和氢分子，避免氮化硅侧墙形成后氢元素扩散到栅极氧化层下表面SiO₂/Si界面处与界面处的Si悬挂键结合，达到减小SiO₂/Si界面处Si-H键数目，从而提高MOS器件中的NBTI性能，进而提高CMOS器件性能。Then continue to the eighth step S7, irradiating the silicon wafer with UV light (ultraviolet light), as shown in FIG. 11 . In this example, the wafer is irradiated with UV light at an appropriate temperature and an appropriate time to remove some hydrogen atoms, hydrogen molecules and water vapor remaining during the growth of the silicon nitride film. Wherein the suitable condition of UV light is very important, preferably, the temperature is 450-480°C, and the time is 100-150S is more appropriate. Too low temperature is not enough to drive away hydrogen and water vapor: too high temperature is more likely to affect the activation and diffusion of ions in the well implantation and lightly doped source and drain implantation in the previous process. The UV light irradiation under the above conditions can effectively remove the hydrogen atoms and hydrogen molecules in the silicon nitride film, and avoid the hydrogen element from diffusing to the SiO₂ /Si interface and the interface on the lower surface of the gate oxide layer after the formation of the silicon nitride sidewall. The combination of Si dangling bonds can reduce the number of Si-H bonds at the SiO₂ /Si interface, thereby improving the performance of NBTI in MOS devices and improving the performance of CMOS devices.

接着继续第九步骤S8，在栅极侧墙一11、21侧边制作形成侧墙二14、14，如图12所示。例如，侧墙二的形成包括氧化物的淀积，SiN的淀积以及SiN的刻蚀。Then continue to the ninth step S8 , forming sidewalls 2 14 , 14 on the sides of the gate spacers 11 , 21 , as shown in FIG. 12 . For example, the formation of the second spacer includes deposition of oxide, deposition of SiN and etching of SiN.

接着继续第十步骤S9，进行源漏注入形成，从而在P型阱100中形成NMOS源漏极15、16，在N型阱200中形成PMOS源漏极25、26，如图13所示。在本实施例中，通过P型掺杂注入形成P型的源漏极，所述P型掺杂为硼掺杂。Then continue to the tenth step S9 , perform source-drain implantation to form NMOS source-drain 15 , 16 in the P-type well 100 , and form PMOS source-drain 25 , 26 in the N-type well 200 , as shown in FIG. 13 . In this embodiment, P-type source and drain electrodes are formed by implanting P-type doping, and the P-type doping is boron doping.

接着可以继续第十一步骤S10，最后制作金属前介质600、通孔700、金属插塞和金属层(未示出)等，如图14所示。Then the eleventh step S10 can be continued, and finally the pre-metal dielectric 600, the via hole 700, the metal plug and the metal layer (not shown) etc. are fabricated, as shown in FIG. 14 .

在上述的可改善NBTI的MOS管制作方法中，第八步骤S7中的UV光照射的温度和时间非常重要：一般温度450-480℃，时间100-150S比较合适。这个条件既不会出现不能驱赶走氢元素和水汽，也不会出现过高的温度会影响前面工艺中的阱(Well)注入和轻掺杂源漏(LDD)注入的离子的激活和扩散。In the above-mentioned MOS tube manufacturing method that can improve NBTI, the temperature and time of UV light irradiation in the eighth step S7 are very important: generally, the temperature is 450-480° C., and the time 100-150 s is more suitable. This condition will not cause the hydrogen element and water vapor to be driven away, nor will the excessively high temperature affect the activation and diffusion of ions implanted in the well (Well) and lightly doped source and drain (LDD) in the previous process.

本方法提供一种半导体集成电路工艺的一种新的工艺用以改善MOS器件的NBTI效应。通过在传统的半导体MOS器件制作过程中，在干法刻蚀形成第二道氮化硅侧墙前和氮化硅膜淀积之后，用UV光对晶片进行照射以去除氮化硅薄膜中的残留的一些氢原子，氢分子以及水汽，避免形成的氮化硅侧墙中的氢元素扩散到栅极氧化层下表面SiO₂/Si界面处与界面处的Si悬挂键结合，达到减小SiO_2/Si界面处Si-H键数目，从而提高MOS器件中的NBTI性能，进而提高CMOS器件性能。与传统的工艺的NBTI改善工艺相比，该工艺具有工艺简单、易于实现等特点。The method provides a new process of a semiconductor integrated circuit process to improve the NBTI effect of the MOS device. In the traditional semiconductor MOS device manufacturing process, before the second silicon nitride sidewall is formed by dry etching and after the silicon nitride film is deposited, the wafer is irradiated with UV light to remove the silicon nitride film. Some residual hydrogen atoms, hydrogen molecules and water vapor prevent the hydrogen element in the formed silicon nitride sidewall from diffusing to the SiO₂ /Si interface on the lower surface of the gate oxide layer and combine with the Si dangling bond at the interface to reduce the SiO_2/ The number of Si-H bonds at the Si interface, thereby improving the NBTI performance in MOS devices, thereby improving the performance of CMOS devices. Compared with the NBTI improvement process of the traditional process, this process has the characteristics of simple process and easy implementation.

此外，需要说明的是，除非特别说明或者指出，否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。In addition, it should be noted that, unless otherwise specified or pointed out, the terms “first”, “second”, “third” and other descriptions in the specification are only used to distinguish each component, element, step, etc. in the specification, and It is not used to represent the logical relationship or sequential relationship between various components, elements, and steps.

可以理解的是，虽然本发明已以较佳实施例披露如上，然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. reduce a cmos device manufacture method for Negative Bias Temperature Instability, it is characterized in that comprising:

First step, carries out trap in the substrate and injects formation P type trap and N-type trap;

Second step, makes grid oxic horizon at substrate surface;

Third step, carries out the deposit of grid layer on grid oxic horizon surface;

4th step, carries out photoetching to grid layer and forms NMOS grid to be formed on P type trap, N-type trap is formed PMOS grid;

5th step, makes grid curb wall one respectively at the side of PMOS grid and NMOS grid;

6th step, carries out light dope and is infused in P type trap and forms NMOS lightly-doped source drain structure, and in N-type trap, form PMOS lightly-doped source drain structure;

7th step, at device surface deposition silicon nitride film;

8th step, utilizes UV light to irradiate silicon chip, and utilize UV light to be 450-480 DEG C to the temperature that silicon chip irradiates, irradiation time is 100-150S;

9th step, makes at grid curb wall one side and forms side wall two;

Tenth step, carries out source and drain and injects formation, thus form NMOS source-drain electrode in P type trap, forms PMOS source drain electrode in N-type trap.

2. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1, characterized by further comprising: the 11 step, for making pre-metal dielectric, through hole, metal plug and metal level.

3. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in a first step, forms N trap by phosphorus doping, forms P trap by B doping.

4. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in third step, the material of the grid layer of deposit is polysilicon.

5. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 5th step, the formation of grid curb wall one comprises the oxidation of polysilicon gate and the deposit of SiN.

6. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 6th step, light dope impurity is boron fluoride.

7. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 9th step, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.

8. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the tenth step, inject by the doping of P type the source-drain electrode forming P type, described P type is doped to boron doping.