技术领域technical field
本发明涉及一种化合物半导体晶圆结构，尤其涉及一种整合异质接面双极晶体管(heterojunctionbipolartransistor；HBT)、场效晶体管(fieldeffecttransistor；FET)以与门流管晶体管(Thyristor)磊晶结构于单一晶圆，可应用于静电防护(ElectrostaticDischarge,ESD)系统的化合物半导体晶圆结构。The present invention relates to a compound semiconductor wafer structure, in particular to a method of integrating a heterojunction bipolar transistor (heterojunction bipolar transistor; HBT), a field effect transistor (field effect transistor; FET) and a gate current transistor (Thyristor) epitaxial structure A single wafer, a compound semiconductor wafer structure that can be applied to an Electrostatic Discharge (ESD) system.
背景技术Background technique
当人体碰触集成电路时，人体上累积的静电会经由集成电路的接脚进入电路中，再经由集成电路接地放电，放电过程会在短短几百奈秒(ns)时间产生数安培的瞬间电流，造成集成电路组件功能异常或损毁，因此在集成电路中通常需要设计一静电防护系统以保护电路中的组件。When the human body touches the integrated circuit, the static electricity accumulated on the human body will enter the circuit through the pins of the integrated circuit, and then discharge through the ground of the integrated circuit. The discharge process will generate a few amperes in just a few hundred nanoseconds (ns). Current may cause abnormal function or damage of integrated circuit components. Therefore, it is usually necessary to design an electrostatic protection system in integrated circuits to protect components in the circuit.
在化合物半导体单一晶圆制程中，受限于磊晶层的设计，在静电防护的设计方面，传统上多是使用pn接面二极管或萧基二极管(Schottkydiode)，在实际应用上，通常是在晶元上先制作多个二极管，再将这些二极管串接使用，因此需占据较大晶圆面积，且二极管的导通电压较小，静电防护能力因此受到限制。In the compound semiconductor single wafer process, limited by the design of the epitaxial layer, in the design of electrostatic protection, pn junction diodes or Schottky diodes (Schottkydiodes) are traditionally used. In practical applications, usually in Multiple diodes are fabricated on the wafer, and then these diodes are used in series. Therefore, a large wafer area is required, and the conduction voltage of the diodes is small, so the electrostatic protection capability is limited.
硅控整流器(silicon-controlledrectifier；SCR)为闸流管晶体管(Thyristor)的一种，其结构为pnpn结构，广泛应用于硅晶圆制程。硅控整流器具有高导通电压，而当组件进入导通状态时则具有一低持有电压(holdingvoltage)，应用于静电防护电路时可将系统电压箝制在很低的电压准位，使内部电路可以有效地被保护住，具有良好的静电防护效能。Silicon-controlled rectifier (silicon-controlled rectifier; SCR) is a kind of thyristor transistor (Thyristor), its structure is pnpn structure, widely used in silicon wafer manufacturing process. The silicon controlled rectifier has a high turn-on voltage and a low holding voltage (holding voltage) when the component enters the conduction state. When applied to the electrostatic protection circuit, the system voltage can be clamped at a very low voltage level, making the internal circuit It can be effectively protected and has good electrostatic protection performance.
目前在化合物半导体晶圆结构方面，为了提高组件积集度，已逐渐采用一种称为BiFET/BiHEMT的结构，亦即一种异质接面双极晶体管(HBT)与场效晶体管/高电子迁移率晶体管(FET/HEMT)的垂直堆栈结构，可以将HBT与FET/HEMT组件整合于同一芯片上；由于HBT具有npn或pnp接面结构，而FET/HEMT可为n型或p型，因此，如能在BiFET/BiHEMT结构中形成硅控整流器所需的pnpn结构，即可将硅控整流器与BiFET/BiHEMT结构加以整合，能更加提高单一晶圆的应用范围，同时可大幅改善静电防护能力。At present, in the compound semiconductor wafer structure, in order to increase the integration of components, a structure called BiFET/BiHEMT has been gradually adopted, that is, a heterojunction bipolar transistor (HBT) and field effect transistor/high electron The vertical stack structure of mobility transistors (FET/HEMT) can integrate HBT and FET/HEMT components on the same chip; since HBT has an npn or pnp junction structure, and FET/HEMT can be n-type or p-type, so If the pnpn structure required by the silicon controlled rectifier can be formed in the BiFET/BiHEMT structure, the silicon controlled rectifier can be integrated with the BiFET/BiHEMT structure, which can further increase the application range of a single wafer and greatly improve the electrostatic protection ability .
发明内容Contents of the invention
本发明的主要目的在于提供一种化合物半导体晶圆结构，其是在一BiFET结构中插入一n型掺杂蚀刻终止层以及一p型插入层，藉以整合场效晶体管(FET)、异质接面双极晶体管(HBT)以与门流管晶体管(Thyristor)的磊晶结构于一化合物半导体晶圆结构中；其中该闸流管晶体管可应于静电保护系统(ESD)，可大幅缩小传统利用二极管的静电保护电路晶圆使用面积，并进一步提升静电保护能力，大幅增进产品竞争力。The main purpose of the present invention is to provide a compound semiconductor wafer structure, which inserts an n-type doped etch stop layer and a p-type insertion layer into a BiFET structure, so as to integrate field effect transistors (FETs), heterojunction The epitaxial structure of the bipolar transistor (HBT) and the gate transistor (Thyristor) is in a compound semiconductor wafer structure; the thyristor transistor can be used in the electrostatic protection system (ESD), which can greatly reduce the traditional application The ESD protection circuit of the diode uses the wafer area, and further improves the ESD protection ability, greatly enhancing product competitiveness.
为达上述目的，本发明提供一种化合物半导体晶圆结构，包含一基板、一场效晶体管磊晶结构、一n型掺杂蚀刻终止层、一p型插入层以及一异质接面双极晶体管结构，其中该场效晶体管磊晶结构位于该基板之上，包含一通道层以及一n型掺杂层，其中该n型掺杂层位于该通道层之上，可用以制作n型场效晶体管；该异质接面双极晶体管磊晶结构由下而上依序包含一次集极层、一集极层、一基极层以及一射极层，其中该次集极层、该集极层以及该射极层为一n型掺杂层而该基极层为一p型掺杂层，从而构成一npn型异质接面双极晶体管磊晶结构；其中该场效晶体管磊晶结构、该n型掺杂蚀刻终止层、该p型插入层以及该异质接面双极晶体管磊晶结构的次集极层、集极层与基极层可构成一具有pnpn型接面结构的闸流管晶体管(Thyristor)磊晶结构。To achieve the above object, the present invention provides a compound semiconductor wafer structure, comprising a substrate, field effect transistor epitaxial structure, an n-type doped etch stop layer, a p-type insertion layer and a heterojunction bipolar The transistor structure, wherein the field effect transistor epitaxial structure is located on the substrate, includes a channel layer and an n-type doped layer, wherein the n-type doped layer is located on the channel layer, and can be used to make n-type field effect Transistor; the epitaxial structure of the heterojunction bipolar transistor includes a primary collector layer, a collector layer, a base layer, and an emitter layer from bottom to top, wherein the sub-collector layer, the collector Layer and the emitter layer are an n-type doped layer and the base layer is a p-type doped layer, thereby forming an npn-type heterojunction bipolar transistor epitaxial structure; wherein the field effect transistor epitaxial structure , the n-type doped etch stop layer, the p-type insertion layer, and the sub-collector layer, collector layer and base layer of the epitaxial structure of the heterojunction bipolar transistor can constitute a pnpn-type junction structure Thyristor transistor (Thyristor) epitaxial structure.
于实施时，前述结构中之n型掺杂蚀刻终止层由磷化铟镓(InGaP)所构成，其掺杂浓度为大于等于1×1015且小于等于1×1022cm-3，且其厚度为介于至之间。In practice, the n-type doped etch stop layer in the aforementioned structure is made of indium gallium phosphide (InGaP), its doping concentration is greater than or equal to 1×1015 and less than or equal to 1×1022 cm-3 , and its thickness between to between.
于实施时，前述结构中之p型插入层可包含一至数层p型掺杂层，其中两两相邻的p型掺杂层其掺杂浓度不同，该p型插入层每一层掺杂浓度为大于等于1×1015cm-3且小于等于1×1022cm-3，且其每一层厚度为介于至之间。In practice, the p-type insertion layer in the aforementioned structure may include one to several layers of p-type doped layers, wherein the doping concentrations of two adjacent p-type doped layers are different, and each layer of the p-type insertion layer is doped The concentration is greater than or equal to 1×1015 cm-3 and less than or equal to 1×1022 cm-3 , and the thickness of each layer is between to between.
于实施时，前述结构中之p型插入层可包含一p+型掺杂层以及一p-型掺杂层，其中该p+型掺杂层为一高浓度p型掺杂层，而该p-型掺杂层为一低浓度p型掺杂层，该p-型掺杂层位于该p+型掺杂层之上。In practice, the p-type insertion layer in the aforementioned structure may include a p+ type doped layer and a p-type doped layer, wherein the p+ type doped layer is a high-concentration p-type doped layer, and the p- The p-type doped layer is a low-concentration p-type doped layer, and the p-type doped layer is located on the p+-type doped layer.
于实施时，前述p+型掺杂层以及p-型掺杂层由砷化镓(GaAs)所构成。During implementation, the aforementioned p+ type doped layer and p− type doped layer are made of gallium arsenide (GaAs).
于实施时，前述p+型掺杂层的掺杂浓度为大于等于1×1018cm-3且小于等于1×1022cm-3，且其厚度为大于等于且小于等于In practice, the doping concentration of the aforementioned p+ type doped layer is greater than or equal to 1×1018 cm-3 and less than or equal to 1×1022 cm-3 , and its thickness is greater than or equal to and less than or equal to
于实施时，前述p-型掺杂层的掺杂浓度为大于等于1×1016cm-3且小于等于1×1017cm-3，且其厚度为大于等于且小于等于In practice, the doping concentration of the aforementioned p-type doped layer is greater than or equal to 1×1016 cm-3 and less than or equal to 1×1017 cm-3 , and its thickness is greater than or equal to and less than or equal to
于实施时，前述场效晶体管磊晶结构可为一n型金属半导体场效晶体管(metalsemiconductortransistor；MESFET)磊晶结构。During implementation, the aforementioned field effect transistor epitaxial structure may be an n-type metal semiconductor field effect transistor (metal semiconductor transistor; MESFET) epitaxial structure.
于实施时，前述场效晶体管磊晶结构可为一n型高电子迁移率晶体管(highelectronmobilitytransistor；HEMT)磊晶结构。During implementation, the aforementioned field effect transistor epitaxial structure may be an n-type high electron mobility transistor (high electron mobility transistor (HEMT) epitaxial structure.
于实施时，前述场效晶体管磊晶结构可为一n型伪晶型高电子迁移率晶体管(pseudomorphichighelectronmobilitytransistor；pHEMT)磊晶结构。During implementation, the aforementioned field effect transistor epitaxial structure may be an n-type pseudomorphic high electron mobility transistor (pseudomorphic high electron mobility transistor, pHEMT) epitaxial structure.
于实施时，构成前述基板的材料可为砷化镓(GaAs)或磷化铟(InP)。In practice, the material constituting the aforementioned substrate may be gallium arsenide (GaAs) or indium phosphide (InP).
本发明采用上述技术方案，具有以下优点：The present invention adopts above-mentioned technical scheme, has the following advantages:
本发明提供一种包含场效晶体管(FET)、异质接面双极晶体管(HBT)以与门流管晶体管(Thyristor)磊晶结构的单一化合物半导体晶圆结构；利用本晶圆结构制作的闸流管晶体管可用于静电保护电路(ESD)，可以大幅缩小静电保护电路使用面积，且闸流管晶体管具有较高触发电压，较低持有电压，较低的能量耗损，并且对高电流具有较佳的处理能力，因此能进一步提升静电防护能力，大幅增进产品竞争力；此外，本发明可与现有的BiFET/BiHEMT制程整合，因此可大幅降低生产制造的成本。其确具产业利用的价值。The present invention provides a single compound semiconductor wafer structure comprising a field effect transistor (FET), a heterojunction bipolar transistor (HBT) and a gate transistor (Thyristor) epitaxial structure; Thyristor transistors can be used in electrostatic protection circuits (ESD), which can greatly reduce the use area of electrostatic protection circuits, and thyristor transistors have high trigger voltage, low holding voltage, low energy consumption, and high current. The better processing ability can further improve the electrostatic protection ability and greatly enhance the product competitiveness; in addition, the present invention can be integrated with the existing BiFET/BiHEMT process, so the manufacturing cost can be greatly reduced. It does have the value of industrial utilization.
附图说明Description of drawings
图1为本发明的一种化合物半导体晶圆结构的剖面结构示意图；Fig. 1 is the cross-sectional structure schematic diagram of a kind of compound semiconductor wafer structure of the present invention;
图2为本发明的一种化合物半导体晶圆结构应用于半导体组件中的剖面结构示意图；2 is a schematic cross-sectional structure diagram of a compound semiconductor wafer structure of the present invention applied to a semiconductor component;
图3为本发明中闸流管晶体管(Thyristor)的传输线脉冲系统(TLP)测试的电流对电压变化图。FIG. 3 is a diagram of current vs. voltage variation of a transmission line pulse system (TLP) test of a thyristor transistor (Thyristor) in the present invention.
附图标记说明：基板101；场效晶体管磊晶结构110；闸流管晶体管磊晶结构120；异质接面双极晶体管磊晶结构130；通道层111；n型掺杂层112；n型掺杂蚀刻终止层121；p型插入层122；次集极层131；集极层132；基极层133；射极层134；场效晶体管210；闸流管晶体管220；异质接面双极晶体管230；源极电极201；汲极电极202；闸极电极203；基极电极204；集极电极205；射极电极206；阳极电极207；阴极电极208。Description of reference numerals: substrate 101; field effect transistor epitaxial structure 110; thyristor transistor epitaxial structure 120; heterojunction bipolar transistor epitaxial structure 130; channel layer 111; n-type doped layer 112; n-type Doped etch stop layer 121; p-type insertion layer 122; sub-collector layer 131; collector layer 132; base layer 133; emitter layer 134; field effect transistor 210; thyristor transistor 220; heterojunction double Transistor 230 ; source electrode 201 ; drain electrode 202 ; gate electrode 203 ; base electrode 204 ; collector electrode 205 ; emitter electrode 206 ; anode electrode 207 ; cathode electrode 208 .
具体实施方式detailed description
本发明所提供的整合一场效晶体管(FET)、一异质接面双极晶体管(HBT)以及一闸流管晶体管(Thyristor)的磊晶结构的化合物半导体晶圆结构，如图1所示，包含一基板101、一场效晶体管磊晶结构110、一n型掺杂蚀刻终止层121、一p型插入层122以及一异质接面双极晶体管结构130，其中该基板101的构成材料可为砷化镓(GaAs)或磷化铟(InP)等半绝缘性半导体材料，其中以砷化镓(GaAs)为较佳；该场效晶体管磊晶结构110，位于该基板101之上，包含一通道层111以及一n型掺杂层112，其中该n型掺杂层位于该信道层之上，此结构可用以制作n型场效晶体管；该n型掺杂蚀刻终止层121位于该场效晶体管磊晶结构110之上；该p型插入层122位于n型掺杂蚀刻终止层121之上；该异质接面双极晶体管磊晶结构130由下而上依序包含一次集极层131、一集极层132、一基极层133以及一射极层134，其中该次集极层131、该集极层132以及该射极层134为一n型掺杂层，而该基极层133为一p型掺杂层，从而构成一npn型异质接面双极晶体管磊晶结构130；如此一来，此化合物半导体晶圆结构由上而下具有n-p-n-p-n结构，而包含了形成一闸流管晶体管(Thyristor)所需的p-n-p-n结构，亦即，该n型场效晶体管磊晶结构、该n型掺杂蚀刻终止层、该p型插入层以及该异质接面双极晶体管磊晶结构的p型掺杂基极层、n型掺杂集极层、与n型掺杂次集极层可构成一具有pnpn型接面结构的闸流管晶体管(Thyristor)磊晶结构120。The compound semiconductor wafer structure integrating the epitaxial structure of a field effect transistor (FET), a heterojunction bipolar transistor (HBT) and a thyristor transistor (Thyristor) provided by the present invention is shown in FIG. 1 , including a substrate 101, a field effect transistor epitaxial structure 110, an n-type doped etch stop layer 121, a p-type insertion layer 122 and a heterojunction bipolar transistor structure 130, wherein the constituent materials of the substrate 101 It can be a semi-insulating semiconductor material such as gallium arsenide (GaAs) or indium phosphide (InP), among which gallium arsenide (GaAs) is preferred; the field effect transistor epitaxial structure 110 is located on the substrate 101, Including a channel layer 111 and an n-type doped layer 112, wherein the n-type doped layer is located on the channel layer, this structure can be used to make n-type field effect transistor; the n-type doped etch stop layer 121 is located on the On the field effect transistor epitaxial structure 110; the p-type insertion layer 122 is located on the n-type doped etch stop layer 121; the heterojunction bipolar transistor epitaxial structure 130 sequentially includes a primary collector from bottom to top layer 131, a collector layer 132, a base layer 133, and an emitter layer 134, wherein the sub-collector layer 131, the collector layer 132, and the emitter layer 134 are n-type doped layers, and the The base layer 133 is a p-type doped layer, thereby forming an npn-type heterojunction bipolar transistor epitaxial structure 130; thus, the compound semiconductor wafer structure has an n-p-n-p-n structure from top to bottom, and includes The p-n-p-n structure required to form a thyristor transistor (Thyristor), that is, the n-type field effect transistor epitaxial structure, the n-type doped etch stop layer, the p-type insertion layer and the heterojunction bipolar The p-type doped base layer, n-type doped collector layer, and n-type doped sub-collector layer of the transistor epitaxial structure can form a thyristor transistor (Thyristor) epitaxial structure with a pnpn junction structure 120.
于实施时，场效晶体管磊晶结构110可为一n型金属半导体场效晶体管(MESFET)、一n型高电子迁移率晶体管(HEMT)、一n型伪晶型高电子迁移率晶体管(pHEMT)或其它n型场效晶体管的磊晶结构；n型掺杂蚀刻终止层121的构成材料以磷化铟镓(InGaP)为较佳，其掺杂浓度为介于1×1015至1×1022cm-3之间，其中以介于1×1017至1×1018cm-3之间为较佳，其厚度可为介于至之间，其中以介于至之间为较佳；p型插入层122可包含一至数层p型掺杂层，其中两两相邻的p型掺杂层其掺杂浓度不同，其每一层掺杂浓度为大于等于1×1015且小于等于1×1022cm-3，且其每一层厚度为介于至之间；异质接面双极晶体管磊晶结构130之主要构成材料可为砷化镓(GaAs)，其次集极层131掺杂浓度为介于1×1015至1×1022cm-3之间，其中以大于等于1×1018cm-3且小于等于1×1022cm-3之高掺杂浓度为较佳。应用于半导体组件中，如图2所示，可于前述晶圆整合结构的n型掺杂层112上设置一源极电极201以及一汲极电极202，于源极与汲极之间的n型掺杂层凹槽内设置一连结通道层111之闸极电极203，则该通道层111、该n型掺杂层112、该源极电极201、该汲极电极202以及该闸极电极203可构成一n型场效晶体管(FET)210；于前述晶圆整合结构的基极层133上设置一基极电极204，于次集极层131上设置一集极电极205，并于射极层134上设置一射极电极206，则该次集极层131、该集极层132、该基极层133、该射极层134、该基极电极204、该集极电极205以及该射极电极206可构成一异质接面双极晶体管(HBT)230；于基极层133上设置一阳极电极207，并于n型掺杂层112上设置一阴极电极208，则该n型掺杂层112、该n型掺杂蚀刻终止层121、该p型插入层122、该次集极层131、该集极层132、该基极层133、该阳极电极207以及该阴极电极208可构成一闸流管晶体管(Thyristor)220。In practice, the field effect transistor epitaxial structure 110 can be an n-type metal semiconductor field effect transistor (MESFET), an n-type high electron mobility transistor (HEMT), an n-type pseudomorphic high electron mobility transistor (pHEMT) ) or other epitaxial structures of n-type field effect transistors; the material of the n-type doped etch stop layer 121 is preferably indium gallium phosphide (InGaP), and its doping concentration is between 1×1015 to 1× Between 1022 cm-3 , preferably between 1×1017 and 1×1018 cm-3 , the thickness can be between to between, where between to between is preferred; the p-type insertion layer 122 may include one to several layers of p-type doped layers, wherein the doping concentration of two adjacent p-type doped layers is different, and the doping concentration of each layer is greater than or equal to 1 ×1015 and less than or equal to 1×1022 cm-3 , and the thickness of each layer is between to Between; the main constituent material of the epitaxial structure 130 of the heterojunction bipolar transistor can be gallium arsenide (GaAs), and the doping concentration of the second collector layer 131 is between 1×1015 to 1×1022 cm−3 Among them, a high doping concentration of greater than or equal to 1×1018 cm-3 and less than or equal to 1×1022 cm-3 is preferred. Applied in semiconductor components, as shown in Figure 2, a source electrode 201 and a drain electrode 202 can be provided on the n-type doped layer 112 of the aforementioned wafer integration structure, and the n between the source and the drain A gate electrode 203 connecting the channel layer 111 is arranged in the groove of the n-type doped layer, then the channel layer 111, the n-type doped layer 112, the source electrode 201, the drain electrode 202 and the gate electrode 203 An n-type field effect transistor (FET) 210 can be formed; a base electrode 204 is provided on the base layer 133 of the aforementioned wafer integration structure, a collector electrode 205 is provided on the sub-collector layer 131, and the emitter An emitter electrode 206 is set on the layer 134, then the sub-collector layer 131, the collector layer 132, the base layer 133, the emitter layer 134, the base electrode 204, the collector electrode 205 and the emitter Pole electrode 206 can constitute a heterojunction bipolar transistor (HBT) 230; An anode electrode 207 is set on the base layer 133, and a cathode electrode 208 is set on the n-type doped layer 112, then the n-type doped The impurity layer 112, the n-type doped etch stop layer 121, the p-type insertion layer 122, the sub-collector layer 131, the collector layer 132, the base layer 133, the anode electrode 207 and the cathode electrode 208 can be A thyristor transistor (Thyristor) 220 is formed.
表1为本发明的化合物半导体晶圆结构的一实施例；此实施例包含一基板以及位于该基板上的14层磊晶层，其中从上而下的第1层及第2层为一高掺杂浓度的射极接触层与一覆盖层，第3至6层为射极层，包含复数层不同厚度与不同掺杂浓度的n型掺杂层；第7层为基极层，为一高掺杂浓度的p型掺杂层；第8至10层为n型掺杂的集极层与n+型掺杂的次集极层；第11、12层为p型掺杂层，分别为一p+型掺杂层及一p-型掺杂层，由砷化镓(GaAs)所构成，该p+型掺杂层为一高浓度p型掺杂层，而该p-型掺杂层为一低浓度p型掺杂层，其中该p-型掺杂层位于该p+型掺杂层之上，该p+型掺杂层的掺杂浓度可选择为大于等于1×1018cm-3且小于等于1×1022cm-3，且其厚度可为大于等于且小于等于在此实施例中该p+型掺杂层的掺杂浓度选择为1×1018cm-3，且厚度选择为而该p-型掺杂层的掺杂浓度为大于等于1×1016cm-3且小于等于1×1017cm-3，且其厚度可为大于等于且小于等于在此实施例中该p-型掺杂层的掺杂浓度选择为1×1016cm-3，且厚度选择为第13层为n型掺杂蚀刻终止层，其由磷化铟镓(InGaP)所构成，其掺杂浓度选择为3×1017cm-3，且其厚度选择为第14层为一n+型掺杂层，其掺杂浓度选择为4×1018cm-3，且其厚度选择为此实施例中的第7至14层为p-n-p-n结构，可用以制作一闸流管晶体管(Thyristor)。Table 1 is an embodiment of the compound semiconductor wafer structure of the present invention; this embodiment includes a substrate and 14 layers of epitaxial layers positioned on the substrate, wherein the first layer and the second layer from top to bottom are a high The emitter contact layer with doping concentration and a cover layer, the third to sixth layers are emitter layers, including a plurality of n-type doped layers with different thicknesses and different doping concentrations; the seventh layer is the base layer, which is a P-type doped layer with high doping concentration; the 8th to 10th layers are n-type doped collector layer and n+ type doped sub-collector layer; the 11th and 12th layers are p-type doped layers, respectively A p+ type doped layer and a p-type doped layer are made of gallium arsenide (GaAs), the p+ type doped layer is a high-concentration p-type doped layer, and the p-type doped layer is A low-concentration p-type doped layer, wherein the p-type doped layer is located on the p+ type doped layer, the doping concentration of the p+ type doped layer can be selected to be greater than or equal to 1×1018 cm-3 and Less than or equal to 1×1022 cm-3 , and its thickness may be greater than or equal to and less than or equal to In this embodiment, the doping concentration of the p+ type doped layer is selected to be 1×1018 cm−3 , and the thickness is selected to be The doping concentration of the p-type doped layer is greater than or equal to 1×1016 cm-3 and less than or equal to 1×1017 cm-3 , and its thickness can be greater than or equal to and less than or equal to In this embodiment, the doping concentration of the p-type doped layer is selected to be 1×1016 cm-3 , and the thickness is selected to be The thirteenth layer is an n-type doped etching stop layer, which is made of indium gallium phosphide (InGaP), its doping concentration is selected to be 3×1017 cm-3 , and its thickness is selected to be The 14th layer is an n+ type doped layer, its doping concentration is selected as 4×1018 cm-3 , and its thickness is selected as The 7th to 14th layers in this embodiment are pnpn structures, which can be used to make a thyristor transistor (Thyristor).
半导体集成电路的静电防护性能通常是以传输线脉冲系统(TransmissionLinePulse,TLP)进行测试，在此测试中系将一高电流脉冲讯号输入测试电路中，所测得的入射与反射脉冲讯号经过计算可得出测试电路的电压-电流变化曲线；此高电流脉冲输入讯号的能量范围与脉冲时间长度接近人体放电模式(HumanBodyModel,HBM)；图3为本发明所提供的闸流管晶体管的TLP电压-电流特性曲线(实线)，并与串接二极管的TLP电压-电流特性曲线(虚线)做一比较；图中显示应用本发明的晶圆结构所制作的闸流管晶体管的触发电压(triggervoltage)约为8伏特，持有电压(holdingvoltage)约为2伏特，组件崩溃电流(devicefailurecurrent)约为0.57安培；与先前技术中以串接二极管作为静电防护电路的TLP电压-电流特性曲线相比，本发明所提供的闸流管晶体管具有较高的触发电压，且组件触发后亦能维持较低的持有电压；此组件的触发电压与持有电压受插入的p型掺杂层的厚度与掺杂浓度影响；通过调整p型掺杂层厚度与掺杂浓度可达到更佳的组件静电防护功能。The electrostatic protection performance of semiconductor integrated circuits is usually tested with Transmission Line Pulse (TLP). In this test, a high-current pulse signal is input into the test circuit, and the measured incident and reflected pulse signals can be calculated. The voltage-current variation curve of the test circuit is obtained; the energy range and pulse time length of this high-current pulse input signal are close to the human body model (HumanBodyModel, HBM); FIG. 3 is the TLP voltage-current of the thyristor transistor provided by the present invention characteristic curve (solid line), and compare it with the TLP voltage-current characteristic curve (dotted line) of the diode connected in series; the figure shows that the trigger voltage (triggervoltage) of the thyristor transistor made by applying the wafer structure of the present invention is about It is 8 volts, the holding voltage (holding voltage) is about 2 volts, and the component breakdown current (device failure current) is about 0.57 amperes; Compared with the TLP voltage-current characteristic curve of using series connection diodes as the electrostatic protection circuit in the prior art, the present invention The provided thyristor transistor has a high trigger voltage, and the device can also maintain a low holding voltage after triggering; the trigger voltage and holding voltage of the device are affected by the thickness and doping of the inserted p-type doped layer Concentration influence; By adjusting the p-type doped layer thickness and doping concentration, better electrostatic protection function of components can be achieved.
表1Table 1
以上这些实施例仅是范例性的，并不对本发明的范围构成任何限制。本领域技术人员应该理解的是，在不偏离本发明的精神和范围下可以对本发明技术方案的细节和形式进行修改或替换，但这些修改和替换均落入本发明的保护范围内。The above embodiments are only exemplary, and do not constitute any limitation to the scope of the present invention. Those skilled in the art should understand that the details and forms of the technical solutions of the present invention can be modified or replaced without departing from the spirit and scope of the present invention, but these modifications and replacements all fall within the protection scope of the present invention.
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