Background technology
At present, at the back segment (back-end-of-line of semiconductor device, BEOL) in technique, can need to grow multiple layer metal interconnection layer on a semiconductor substrate according to difference, every layer of metal interconnecting layer comprises metal interconnecting wires and insulating barrier, and this just needs to manufacture groove (trench) and connecting hole, then plated metal in above-mentioned groove and connecting hole to above-mentioned insulating barrier, the metal of deposition is metal interconnecting wires, generally selects copper as metal interconnected wire material.Insulating barrier specifically can be arranged according to the needs of processing procedure.Such as comprise the etch stop layer formed successively on a semiconductor substrate, the silicon carbide layer of such as nitrating; Low-k (Low-K) insulation material layer, black diamond (blackdiamond, the BD) material etc. of such as, similar oxide (Oxide) containing silicon, oxygen, carbon, protium.
Form the method for groove in prior art, comprise the following steps:
Step 011, provide semi-conductive substrate, described semiconductor substrate surface comprises etch stop layer and interlayer dielectric layer from bottom to top successively, interlayer dielectric layer is coated with photoresistance glue (PR, PhotoResist) layer, and optical resistance glue layer described in patterning, the optical resistance glue layer of patterning appear the critical size (CD) of region definition groove;
Step 012, with the optical resistance glue layer of patterning for mask, dry etching interlayer dielectric layer, etch stop layer stop etching, formed groove.In existing etching technics, the method for general using plasma etching forms groove.
In groove, metallic copper is filled after the optical resistance glue layer of step 013, removal patterning.
Along with the development of integrated circuit, the number of plies of back segment metal interconnecting layer is more and more intensive, require that interlayer dielectric layer has lower K value, although interlayer dielectric layer have employed low dielectric constant insulating material layer, but the dielectric constant of BD is 2.7 ~ 3, therefore the resistance capacitance (RC) how reducing whole integrated circuit (IC) further postpones, and improves the electric property of device, becomes current problem demanding prompt solution.
Summary of the invention
In view of this, the technical problem that the present invention solves is: the RC reducing whole IC postpones.
For solving the problems of the technologies described above, technical scheme of the present invention is specifically achieved in that
The invention provides a kind of method forming airspace between groove, be applied in the last part technology of semiconductor device, the method comprises:
There is provided semi-conductive substrate in advance, described semiconductor substrate surface comprises the optical resistance glue layer of the first etch stop layer and patterning from bottom to top successively, the optical resistance glue layer of patterning appear the critical size of region definition groove;
In the optical resistance glue layer surface deposition ultralow temperature oxide layer of the first etch stop layer and patterning, and anisotropic etching is carried out to described ultralow temperature oxide layer, form the side wall layer being positioned at patterning optical resistance glue layer both sides;
Remove patterning optical resistance glue layer;
Plated metal copper also carries out cmp or plasma etching method makes copper apparent height flush with the height of side wall layer, forms the metal copper layer of sidewall layer spaces;
At metal copper layer surface deposition second etch stop layer of sidewall layer spaces, and position time initial below it on the second etch stop layer surface with patterning optical resistance glue layer forms through hole;
Remove the metal copper layer below through hole, form the airspace between groove.
The metal copper layer removed below through hole adopts the method for wet etching to carry out in the solution comprising acid solution and hydrogen peroxide.
Described acid solution is the mixed liquor of one or more in hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid or other acid solution.
The method removing patterning optical resistance glue layer comprises the method for oxygen ashing or the method for oxygen-carrying ion body etching or the method for wet etching.
The formation temperature of described ultralow temperature oxide layer is lower than 100 degrees Celsius.
After forming the airspace between groove, the method comprises the interlayer dielectric layer forming lower floor further.
The dielectric constant of described interlayer dielectric layer is 2 ~ 7.
Described interlayer dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO2one or several combination in any in layer, hydroxide silicon layer, silicon nitride layer, carbonitride of silicium SiNC layer.
As seen from the above technical solutions, between side wall layer, form metal copper layer, this metal copper layer comprises the metal copper layer in groove, also comprises follow-up needs and removes the metal copper layer forming airspace.The metal copper layer revealed by through hole is immersed in the solution comprising acid solution and hydrogen peroxide, carry out wet etching, this part copper dissolution is fallen, airspace is formed between groove, airspace instead of the interlayer dielectric layer of prior art, thus reaches the object of the RC delay reducing whole IC.And, present invention employs and be different from the method that prior art etching interlayer dielectric layer forms groove, but exposure imaging optical resistance glue layer, the CD of definition groove, there is not the process of etching interlayer dielectric layer in the groove of such formation, therefore groove has higher characteristic size uniformity.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
The present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail, for convenience of explanation, represent that the schematic diagram of structure can be disobeyed general ratio and be made partial enlargement, should in this, as limitation of the invention, in addition, in the making of reality, the three-dimensional space of length, width and the degree of depth should be comprised.
Core concept of the present invention is: between side wall layer, form metal copper layer, and this metal copper layer comprises the metal copper layer in groove, also comprises follow-up needs and removes the metal copper layer forming airspace.The metal copper layer revealed by through hole is immersed in the solution comprising acid solution and hydrogen peroxide, carry out wet etching, this part copper dissolution is fallen, airspace is formed between groove, airspace instead of the interlayer dielectric layer of prior art, thus reaches the object of the RC delay reducing whole IC.And, present invention employs and be different from the method that prior art etching interlayer dielectric layer forms groove, but exposure imaging optical resistance glue layer, the CD of definition groove, there is not the process of etching interlayer dielectric layer in the groove of such formation, therefore groove has higher characteristic size uniformity.
Form the method for airspace between embodiment of the present invention groove, its schematic flow sheet as shown in Figure 1, comprises the following steps, and below in conjunction with Fig. 2 a to Fig. 2 f, is described in detail.
Step 11, refer to Fig. 2 a, semi-conductive substrate 100 is provided in advance, described Semiconductor substrate 100 surface comprises the optical resistance glue layer 102 of the first etch stop layer 101 and patterning from bottom to top successively, the optical resistance glue layer 102 of patterning appear the critical size of region definition groove;
Step 12, refer to Fig. 2 b, in the optical resistance glue layer 102 surface deposition ultralow temperature oxide layer of the first etch stop layer 101 and patterning, and anisotropic etching is carried out to described ultralow temperature oxide layer, form the side wall layer 103 being positioned at patterning optical resistance glue layer both sides;
Ultralow temperature oxide layer is low temperature oxide layer (LowTemperatureOxide, LTO) one, why select ultralow temperature oxide layer as the side wall layer of photoresistance glue, because the formation temperature of ultralow temperature oxide layer is lower than 100 degrees Celsius, lower than the fusion temperature of photoresistance glue, be unlikely to, in the process forming side wall layer, to change the pattern of optical resistance glue layer.
Step 13, refer to Fig. 2 c, remove patterning optical resistance glue layer 102;
The method removing patterning optical resistance glue layer comprises the method for oxygen ashing or the method for oxygen-carrying ion body etching or the method for wet etching.
Step 14, refer to Fig. 2 d, plated metal copper also carries out cmp or plasma etching method makes copper apparent height flush with the height of side wall layer, forms the metal copper layer 104 of sidewall layer spaces;
Step 15, refer to Fig. 2 e, at metal copper layer 104 surface deposition second etch stop layer 105 of sidewall layer spaces, and position time initial below it on the second etch stop layer surface with patterning optical resistance glue layer forms through hole 106;
Wherein, each initial time there is patterning optical resistance glue layer position form the quantity of through hole and do not limit, a through hole is only shown in Fig. 2 e.Entire widths does not also limit, and the interlayer dielectric layer being unlikely to subsequent deposition collapses in airspace.Second etch stop layer 105 is generally carborundum, silicon nitride, one or several the combination in carbon nitrogen silicon layer.The process forming through hole is generally at the second etch stop layer 105 surface coating photoresistance glue, by size and the position of patterning photoresistance glue definition through hole, then with this patterning photoresistance glue for mask, etch the second etch stop layer 105, thus form through hole on the second etch stop layer 105.
Step 16, refer to Fig. 2 f, remove the metal copper layer below through hole 106, form the airspace 107 between groove.
This step is key of the present invention, because metal copper layer can reveal by through hole, the metal copper layer of other positions is covered by the second etch stop layer, comprise in the solution of acid solution and hydrogen peroxide so the device with this structure is immersed, wet etching is carried out to the metal copper layer revealed by through hole.Described acid solution can be the mixed liquor of one or more in hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid or other acid solution, or other can react in conjunction with hydrogen peroxide and metallic copper, the material of dissolved copper.
Wherein, take acid solution as hydrochloric acid be example, the chemical equation carrying out reacting is:
H2O2+2(HCl)+Cu=CuCl2+2(H2O)。
Like this, the metallic copper in groove still retains, and forms airspace between groove.
So far, the embodiment of the present invention achieves the method forming airspace between groove.
Further, the embodiment of the present invention can also comprise step 17, refer to Fig. 2 g, the interlayer dielectric layer 108 of deposition lower floor.Those skilled in the art can know, the interlayer dielectric layer of lower floor can make groove and connecting hole, and connecting hole can be electrically connected with metal copper layer 104, does not repeat them here.The dielectric constant of interlayer dielectric layer 108 is 2 ~ 7, can be silicon oxide carbide (SiOC) layer, silicon dioxide (SiO2) combination in any of one or more in layer, hydroxide silicon layer, silicon nitride layer or carbonitride of silicium (SiNC) layer.
At present, characteristic size uniformity (CriticalDimensionUniform, CDU) is the important indicator needing in process for fabrication of semiconductor device to investigate.Usually, in semiconductor fabrication process, after the characteristic size detecting (AfterDevelopmentInspection, ADI) deducts etching, detect the characteristic size of (AfterEtchInspection, AEI) after etch bias amount (etchbias) equals to develop.In wafer, there are several chip units (Die), in each chip unit, there is several single lines (Iso) and close line (Dense).From single line to Mi Xianchu, the spacing between groove and groove reduces gradually.The characteristic size of ADI refers to the centre position size measuring PR after exposure imaging, and the characteristic size of AEI refers to the bottom position size of the groove after measuring etching.The etch bias amount of Iso and Dense is more close, then illustrate that its characteristic size uniformity is higher, also show as Iso and Dense groove dimensions mean value more close.When prior art forms groove, need to etch interlayer dielectric layer for a long time, and the etch rate of Iso with Dense is different, causes the AEI difference of Iso and Dense larger, therefore etchbias is larger, finally causes the CDU of groove poor.And method of the present invention does not relate to etching interlayer dielectric layer, in a step 11, the optical resistance glue layer 102 of exposure imaging formation patterning is by the width of groove and highly all define out, and the groove dimensions obtained at Iso and Dense place does not have difference substantially, and therefore the CDU of groove is also higher.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.