技术领域technical field
本发明属于电子电路技术领域，涉及模拟集成电路。特别涉及一种高效率降压型DC-DC变换器，主要采用栅宽控制技术和死区预测控制技术提高系统的转换效率。The invention belongs to the technical field of electronic circuits and relates to analog integrated circuits. It particularly relates to a high-efficiency step-down DC-DC converter, which mainly adopts grid width control technology and dead zone predictive control technology to improve the conversion efficiency of the system.
背景技术Background technique
电子产品中的供电电压与电子产品内部需要的电压不一致是极其常见的。很多便携式设备采用电池供电，电池的输出电压随着电池使用时间的长短而变化，所以供电电压通常不是一个恒定的电压。而电子产品内部的芯片则需要一个稳定的供电电压，电源管理芯片就成为了电子产品不可或缺的组成部分，电源管理芯片的优劣直接影响到电子设备的技术性能指标和以及工作是否安全可靠。It is extremely common that the supply voltage in an electronic product does not match the voltage required inside the electronic product. Many portable devices are powered by batteries, and the output voltage of the batteries changes with the length of time the batteries are used, so the supply voltage is usually not a constant voltage. The chip inside the electronic product needs a stable power supply voltage, and the power management chip has become an indispensable part of the electronic product. The quality of the power management chip directly affects the technical performance index of the electronic device and whether the work is safe and reliable. .
Buck型开关电源是DC-DC变换器中的一类，其基本功能为：将输入不稳定的直流电压降压并转换为较稳定的输出直流电压。其主要优点是重载时能到达很高的转换效率。The Buck switching power supply is a type of DC-DC converter, and its basic function is to step down the input unstable DC voltage and convert it into a more stable output DC voltage. Its main advantage is that it can achieve high conversion efficiency under heavy load.
实际电路中的功率开关管存在寄生电容，所以在功率管导通与关断的切换过程，功率管上的电压和电流不是理想的瞬时跳变，而是有一个缓慢上升或下降的过程，这是由于开关管的寄生电容充放电造成的。寄生电容在过程中引入了驱动损耗。该损耗与寄生电容值大小和开关频率大小成正比。为了承载功率电路中可能出现的最大电流，通常选用宽长比W/L很大的MOS管作为功率开关管，这就使得与MOS管宽和长成正比的寄生电容较大。在轻载条件下，这部分损耗所占比例凸显，使得系统在轻载时转换效率较低。而现代的许多便携式设备大部分时间运行在低功耗的待机模式，即轻载模式。所以提高轻载条件下的转换效率是十分有必要的。The power switch tube in the actual circuit has parasitic capacitance, so in the switching process of the power tube on and off, the voltage and current on the power tube are not ideal instantaneous jumps, but have a slow rise or fall process, which It is caused by the charging and discharging of the parasitic capacitance of the switch tube. Parasitic capacitance introduces drive losses in the process. This loss is proportional to the size of the parasitic capacitance and the switching frequency. In order to carry the maximum current that may occur in the power circuit, a MOS tube with a large width-to-length ratio W/L is usually selected as a power switch tube, which makes the parasitic capacitance proportional to the width and length of the MOS tube larger. Under light load conditions, the proportion of this part of loss is prominent, making the conversion efficiency of the system low at light load. However, many modern portable devices operate in a low-power standby mode, that is, a light load mode, most of the time. Therefore, it is very necessary to improve the conversion efficiency under light load conditions.
发明内容Contents of the invention
本发明主要是解决现有技术所存在的技术问题；提供了一种可为低压用电设备将不稳定的直流电压降压并高效地转换为稳定的直流电压。当DC-DC变换器工作在轻载条件下，装置就会关闭相应的功率开关管和同步整流管，从而降低功率电路中的驱动损耗，提高轻载转换效率的一种高效率降压型DC-DC变换器。The invention mainly solves the technical problems existing in the prior art; it provides a method for stepping down an unstable DC voltage and efficiently converting it into a stable DC voltage for low-voltage electrical equipment. When the DC-DC converter works under light-load conditions, the device will turn off the corresponding power switch tube and synchronous rectifier tube, thereby reducing the driving loss in the power circuit and improving the light-load conversion efficiency. A high-efficiency step-down DC - DC converter.
本发明还有一目的是解决现有技术所存在的技术问题；提供了一种能够实时检测出多余的死区时间，并进行记录，然后通过控制死区电路加入到开关信号中死区时间的长短。从而最小化死区时间，减少多余死区时间引入的导通损耗，提高系统转换效率的一种高效率降压型DC-DC变换器。Another purpose of the present invention is to solve the technical problems existing in the prior art; to provide a method that can detect and record the redundant dead time in real time, and then add the length of the dead time to the switch signal by controlling the dead time circuit . A high-efficiency step-down DC-DC converter that minimizes the dead time, reduces the conduction loss caused by the redundant dead time, and improves the conversion efficiency of the system.
本发明的上述技术问题主要是通过下述技术方案得以解决的：Above-mentioned technical problem of the present invention is mainly solved by following technical scheme:
一种高效率降压型DC-DC变换器，其特征在于，包括功率电路和控制电路模块（101）；其中功率电路的输入端Vin即为DC-DC变换器的电源输入端，其输出端Vout即为DC-DC变换器的电源输出端，控制电路模块（101）的5bit输出端VdriveP<4:0>分别连接到功率电路的输入端，即功率开关管组SW内5组MOS管的栅极，控制电路模块（101）的5bit输出端VdriveN<4:0>分别连接到功率电路的输入端，即功率开关管组SR内5组MOS管的栅极，功率电路的输出端VSW与控制电路模块（101）的输入端相连，功率电路的输出端Vfb与控制电路模块（101）的输入端相连，功率电路的输出端VSW与控制电路模块（101）的输入端相连。A high-efficiency step-down DC-DC converter, characterized in that it includes a power circuit and a control circuit module (101); wherein the input terminal Vin of the power circuit is the power supply input terminal of the DC-DC converter, and its output terminal Vout is the power output terminal of the DC-DC converter, and the 5-bit output terminal VdriveP <4:0> of the control circuit module (101) is respectively connected to the input terminal of the power circuit, that is, the five groups of MOS tubes in the power switch tube group SW The gates of the control circuit module (101) and the 5-bit output terminal VdriveN <4:0> are respectively connected to the input terminals of the power circuit, that is, the gates of the 5 groups of MOS tubes in the power switch tube group SR, and the output terminals of the power circuit VSW is connected to the input end of the control circuit module (101), the output end Vfb of the power circuit is connected to the input end of the control circuit module (101), and the output end VSW of the power circuit is connected to the input end of the control circuit module (101). .
针对这一问题，本发明采用栅宽控制技术，根据实时监测的负载电流大小，判断决定功率开关管的沟道宽度。使得轻载条件下，功率开关管的寄生电容较小，从而减小驱动损耗。To solve this problem, the present invention adopts gate width control technology to judge and determine the channel width of the power switch tube according to the magnitude of the load current monitored in real time. Under the condition of light load, the parasitic capacitance of the power switch tube is small, thereby reducing the driving loss.
此外，为了进一步降低损耗，现在的大多功率电路中均采用同步整流管代替传统的续流二极管，因为选择合适同步整流管，其漏源两端比续流二极管两端压降要低。在负载电流较大和输出电压较低的应用条件下，这样做能有效提高转换效率。但是要严格控制同步整流管与功率开关管在工作中不会同时导通，不然会造成不必要的大电流浪涌，影响电路稳定性。所以必须为两个开关管的控制信号加入的死区。死区时间内，同步整流管与功率开关管均关断，此时，同步整流管的体二极管被强制导通，同步体二极管两端的压降即为整流管漏源两端的压降，此压降也是大于同步整流管导通时的漏源压降，所以这段死区时间是越小越好。但是传统死区控制电路是加入固定死区时间的方法，给开关控制信号加入的死区时间是电路工作中需要的最大的死区时间，以保证电路在最坏条件下也能工作。但这会使系统在正常工作时，引入多余的死区时间，引入过多不必要的导通损耗。In addition, in order to further reduce losses, most current power circuits use synchronous rectifiers instead of traditional freewheeling diodes, because the voltage drop across the drain and source is lower than that of freewheeling diodes when a suitable synchronous rectifier is selected. This can effectively improve the conversion efficiency under the application conditions of large load current and low output voltage. However, it is necessary to strictly control the synchronous rectifier tube and the power switch tube not to be turned on at the same time during work, otherwise it will cause unnecessary large current surges and affect the stability of the circuit. Therefore, a dead zone must be added to the control signals of the two switching tubes. During the dead time, both the synchronous rectifier and the power switch are turned off. At this time, the body diode of the synchronous rectifier is forced to conduct, and the voltage drop across the synchronous body diode is the voltage drop across the drain and source of the rectifier. The drop is also greater than the drain-source voltage drop when the synchronous rectifier is turned on, so the smaller the dead time, the better. However, the traditional dead zone control circuit is a method of adding a fixed dead zone time. The dead zone time added to the switch control signal is the maximum dead zone time required in the circuit work, so as to ensure that the circuit can work under the worst conditions. But this will cause the system to introduce redundant dead time and excessive unnecessary conduction loss during normal operation.
针对这一问题，本发明采用死区预测控制技术，检测出这一开关周期的死区时间，动态控制下一周期需要加入的死区时间长短，从而最小化系统工作过程中的死区时间，进而降低同步整流管的导通损耗。To solve this problem, the present invention adopts the dead zone predictive control technology to detect the dead zone time of this switching cycle, and dynamically control the length of the dead zone time that needs to be added in the next cycle, thereby minimizing the dead zone time in the working process of the system. In turn, the conduction loss of the synchronous rectifier is reduced.
在上述的一种高效率降压型DC-DC变换器所述功率电路包括功率开关管组SW、同步整流管组SR和滤波反馈电路（102）；所述功率开关管组SW的漏端、功率开关管组SW的漏端和滤波反馈电路（10）的输入端共同连接到功率电路的输出端VSW；所述功率开关管组SW包括五个宽长比相同的P型MOS管，五个P型MOS管的源极均与电源输入端Vin相连，漏极均连接到功率电路的输出端VSW，栅极分别与功率电路的输入端VdriveP<4:0>相连；所述同步整流管组SR包括五个宽长比相同的N型MOS管，五个功率开关管的漏极均连接到功率电路的输出端VSW，源极都连接到地，栅极分别与功率电路（102）的输入端VdriveN<4:0>相连。In the aforementioned high-efficiency step-down DC-DC converter, the power circuit includes a power switch tube set SW, a synchronous rectifier tube set SR, and a filter feedback circuit (102); the drain terminal of the power switch tube set SW, The drain terminal of the power switch tube group SW and the input terminal of the filter feedback circuit (10) are jointly connected to the output terminal VSW of the power circuit; the power switch tube group SW includes five P-type MOS tubes with the same width-to-length ratio, five The sources of each P-type MOS transistor are connected to the power input terminal Vin, the drains are connected to the output terminal VSW of the power circuit, and the gates are respectively connected to the input terminal VdriveP <4:0> of the power circuit; the synchronous The rectifier tube group SR includes five N-type MOS tubes with the same aspect ratio, the drains of the five power switch tubes are connected to the output terminal VSW of the power circuit, the sources are connected to the ground, and the gates are respectively connected to the power circuit ( 102) is connected to the input terminal VdriveN <4:0>.
在上述的一种高效率降压型DC-DC变换器所述滤波反馈电路（102）包括电感L、电容C、电阻R1和R2；其中，电感L的一端连接到功率电路的输出端VSW；另一端连接到DC-DC变换器的电源输出端Vout；电容C连接在电源输出端口Vout与地之间；电阻R1和R2串联连接在电源输出端口Vout与地之间，在R1和R2中间引出功率电路的输出端Vfb。In the aforementioned high-efficiency step-down DC-DC converter, the filter feedback circuit (102) includes an inductor L, a capacitor C, resistors R1 and R2; wherein, one end of the inductor L is connected to the output terminal VSW of the power circuit ;The other end is connected to the power output terminal Vout of the DC-DC converter; the capacitor C is connected between the power output port Vout and the ground; the resistors R1 and R2 are connected in series between the power output port Vout and the ground, in the middle of R1 and R2 The output terminal Vfb of the power circuit is drawn out.
在上述的一种高效率降压型DC-DC变换器所述控制电路模块（101）包括电流检测电路（103）、栅宽控制电路（104）、逻辑控制与栅极驱动电路（105）、脉冲宽度调制电路（106）、死区电路（107）和死区预测电路（108）；所述电流检测电路（103）的输入端即为控制电路模块（101）的输入端VSW，电流检测电路103的输出端Vsense连接到栅宽控制电路（104）的输入端，栅宽控制电路（104）的两个输入端DSW和DSR连接到死区电路（107）的输出端，栅宽控制电路（104）的两路5bit输出端GSW<4:0>和GSR<<4:0>分别连接到逻辑控制与栅极驱动电路（105）的输入端，逻辑控制与栅极驱动电路（105）的两路5bit输出端即为控制电路模块（101）的两路5bit输出端VdriveP<4:0>和VdriveN<4:0>；脉冲宽度调制电路（106）的输入端即为控制电路模块（101）的输入端Vfb，脉冲宽度调制电路（106）的输出端与死区电路（107）的输入端Vpwm相连，死区电路（107）的输出端Dsw和DSR分别连接到栅宽控制电路（104）的输入端，死区电路（107）的两路八8bit输入端CTL_SW<7:0>和CTL_SR<7:0>连接到的死区预测电路（108）输出端，死区预测电路（108）的两个输入端分别是控制电路模块（101）的输入端VSW和逻辑控制与栅极驱动电路（105）的一路输出电压VdriveN0。In the aforementioned high-efficiency step-down DC-DC converter, the control circuit module (101) includes a current detection circuit (103), a gate width control circuit (104), a logic control and gate drive circuit (105), Pulse width modulation circuit (106), dead zone circuit (107) and dead zone prediction circuit (108); the input terminal of the current detection circuit (103) is the input terminal VSW of the control circuit module (101), the current detection The output terminal Vsense of the circuit 103 is connected to the input terminal of the gate width control circuit (104), and the two input terminals DSW and DSR of the gate width control circuit (104) are connected to the output terminal of the dead zone circuit (107), and the gate width The two 5-bit output terminals GSW <4:0> and GSR< <4:0> of the control circuit (104) are respectively connected to the input terminals of the logic control and gate drive circuit (105), and the logic control and gate drive The two 5bit output terminals of the circuit (105) are the two 5bit output terminals VdriveP <4:0> and VdriveN <4:0> of the control circuit module (101); the input terminals of the pulse width modulation circuit (106) That is, the input terminal Vfb of the control circuit module (101), the output terminal of the pulse width modulation circuit (106) is connected to the input terminal Vpwm of the dead zone circuit (107), and the output terminals Dsw and DSR of the dead zone circuit (107) are respectively Connected to the input terminal of the gate width control circuit (104), the two-way eight 8bit input terminals CTL_SW<7:0> and CTL_SR<7:0> of the dead zone circuit (107) are connected to the output of the dead zone prediction circuit (108) The two input terminals of the dead zone prediction circuit (108) are respectively the input terminal VSW of the control circuit module (101) and an output voltage VdriveN0 of the logic control and gate drive circuit (105).
在上述的一种高效率降压型DC-DC变换器所述栅宽控制电路（104）包括基准电压子电路（301）、四个比较器com1～com4和逻辑子电路（302）组成，四个比较器的正相输入端均与栅宽控制电路（104）的输入端Vsense相连，四个比较器的反相输入端分别与基准电压子电路（301）的输出端Vref1～Vref4相连，四个比较器的输出端Vcom1_out～Vcom4_out和栅宽控制电路（104）的输入端DSW和DSR均为逻辑子电路（302）的输入端，逻辑子电路（302）的两路5bit输出端GSW<4:0>和GSR<4:0>为栅宽控制电路（104）的输出端。In the above-mentioned high-efficiency step-down DC-DC converter, the gate width control circuit (104) includes a reference voltage sub-circuit (301), four comparators com1-com4 and a logic sub-circuit (302). The non-inverting input terminals of the four comparators are all connected to the input terminal Vsense of the gate width control circuit (104), the inverting input terminals of the four comparators are respectively connected to the output terminals Vref1-Vref4 of the reference voltage sub-circuit (301), and the four comparators are respectively connected to the output terminals Vref1-Vref4 of the reference voltage sub-circuit (301). The output terminals Vcom1_out～Vcom4_out of each comparator and the input terminals DSW and DSR of the gate width control circuit (104) are both input terminals of the logic sub-circuit (302), and the two 5-bit output terminals G of the logic sub-circuit (302)SW <4:0> and GSR <4:0> are output terminals of the gate width control circuit ( 104 ).
在上述的一种高效率降压型DC-DC变换器所死区电路（107）包括两个死区通道：SW通道组（501）和SR通道组（502），两个通道并列相连，输入端均为死区电路（107）的输入端Vpwm，输出端均为死区电路（107）的输出端DSW和DSR；The dead zone circuit (107) of the above-mentioned high-efficiency step-down DC-DC converter includes two dead zone channels: SW channel group (501) and SR channel group (502), the two channels are connected in parallel, and the input Both terminals are the input terminal Vpwm of the dead zone circuit (107), and the output terminals are both output terminals DSW and DSR of the dead zone circuit (107);
所述SW通道组（501）包括第一延迟电路（503）、比较器com_SW、与门and_SW和非门Not_SW；死区电路（107）的输入端Vpwm与第一延迟电路（503）的输入端相连，第一延迟电路（503）的输出端连接到比较器com_SW的正相输入端，比较器com_SW的输出端连接到与门and_SW的输入端，与门and_SW的输出端连接到非门Not_SW的输入端，非门Not_SW的输出端即为死区电路（107）的输出端DSW；The SW channel group (501) includes a first delay circuit (503), a comparator com_SW, an AND gate and_SW and a NOT gate Not_SW; the input terminal Vpwm of the dead zone circuit (107) and the input terminal of the first delay circuit (503) The output terminal of the first delay circuit (503) is connected to the non-inverting input terminal of the comparator com_SW, the output terminal of the comparator com_SW is connected to the input terminal of the AND gate and_SW, and the output terminal of the AND gate and_SW is connected to the gate Not_SW. The input terminal, the output terminal of the NOT gate Not_SW is the output terminal DSW of the dead zone circuit (107);
所述SR通道组（502）包括非门Not_SR、第二延迟电路（504）、比较器com_SR和与门and_SR；死区电路（107）的输入端Vpwm与非门Not_SR的输入端相连，非门Not_SR的输出端与延迟电路第二（504）的输入端相连，第二延迟电路（504）的输出端连接到比较器com_SR的正相输入端，比较器com_SR的输出端连接到与门and_SR的输入端，与门and_SR的输出端即为死区电路（107）的输出端DSR。The SR channel group (502) includes a NOT gate Not_SR, a second delay circuit (504), a comparator com_SR and an AND gate and_SR; the input terminal Vpwm of the dead zone circuit (107) is connected to the input terminal of the NOT gate Not_SR, and the NOT gate The output terminal of Not_SR is connected to the input terminal of the second delay circuit (504), the output terminal of the second delay circuit (504) is connected to the non-inverting input terminal of the comparator com_SR, and the output terminal of the comparator com_SR is connected to the AND gate and_SR The input terminal and the output terminal of the AND gate and_SR are the output terminal DSR of the dead zone circuit ( 107 ).
在上述的一种高效率降压型DC-DC变换器所述死区预测电路（108）包括一个或非门Nor、延迟电路（601）、第一整形电路（602）、第二整形电路（603）、第一计数器（604）和第二计数器（605）；死区预测电路（108）的两输入端VSW和VdriveNO与或非门Nor的两输入端相连，同时，输入端VSW还与第一整形电路（602）的输入端相连，输入端VdriveNO还与第二整形电路603的输入端相连，第一整形电路（602）的输出端连接到第一计数器（604）的时钟输入端，第二整形电路（603）的输出端连接到第二计数器（605）的时钟输入端；或非门Nor的输出端与延迟电路（601）的输入端相连，第一计数器（604）和第二计数器（605）的数据输入端与延迟电路（601）的输出端Delay相连，第一计数器（604）的8bit输出端与死区预测电路（108）的输出端CTL_SW<7:0>相连，第二计数器（605）的8bit输出端与死区预测电路（108）的输出端CTL_SR<7:0>相连。In the above-mentioned high-efficiency step-down DC-DC converter, the dead zone prediction circuit (108) includes a NOR gate Nor, a delay circuit (601), a first shaping circuit (602), a second shaping circuit ( 603), the first counter (604) and the second counter (605); the two input terminals VSW and VdriveNO of the dead zone prediction circuit (108) are connected with the two input terminals of the NOR gate Nor, and at the same time, the input terminal VSW It is also connected to the input end of the first shaping circuit (602), the input end VdriveNO is also connected to the input end of the second shaping circuit 603, and the output end of the first shaping circuit (602) is connected to the clock of the first counter (604) Input terminal, the output terminal of the second shaping circuit (603) is connected to the clock input terminal of the second counter (605); the output terminal of the NOR gate Nor is connected to the input terminal of the delay circuit (601), and the first counter (604) The data input terminal of the second counter (605) is connected to the output terminal Delay of the delay circuit (601), the 8bit output terminal of the first counter (604) is connected to the output terminal CTL_SW<7:0> of the dead zone prediction circuit (108) The 8-bit output terminal of the second counter (605) is connected with the output terminal CTL_SR<7:0> of the dead zone prediction circuit (108).
因此，本发明具有如下优点：1.可为低压用电设备将不稳定的直流电压降压并高效地转换为稳定的直流电压。当DC-DC变换器工作在轻载条件下，装置就会关闭相应的功率开关管和同步整流管，从而降低功率电路中的驱动损耗，提高轻载转换效率。2.能够实时检测出多余的死区时间，并进行记录，然后通过两路8bit数据控制死区电路加入到开关信号中死区时间的长短。从而最小化死区时间，减少多余死区时间引入的导通损耗，提高系统转换效率。Therefore, the present invention has the following advantages: 1. The unstable DC voltage can be stepped down and efficiently converted into a stable DC voltage for low-voltage electrical equipment. When the DC-DC converter works under light load conditions, the device will turn off the corresponding power switch tube and synchronous rectifier tube, thereby reducing the driving loss in the power circuit and improving the light load conversion efficiency. 2. It can detect and record the redundant dead time in real time, and then control the length of the dead time added to the switch signal by the dead time circuit through two 8bit data. In this way, the dead time is minimized, the conduction loss caused by redundant dead time is reduced, and the conversion efficiency of the system is improved.
附图说明Description of drawings
图1高效率的DC-DC变换器的电路结构框图。The block diagram of the circuit structure of the high-efficiency DC-DC converter in Fig. 1.
图2功率电路结构图。Figure 2 Power Circuit Structure Diagram.
图3栅宽控制电路104的结构框图。FIG. 3 is a structural block diagram of the gate width control circuit 104 .
图4功率开关管SW1使能与否的判断波形示意图。Fig. 4 is a schematic diagram of a judgment waveform of whether the power switch tube SW1 is enabled or not.
图5死区电路结构图。Figure 5 Dead zone circuit structure diagram.
图6死区预测电路的结构框图。Figure 6 is a structural block diagram of the dead zone prediction circuit.
图7死区预测电路和死区电路中各信号的工作波形示意图。Fig. 7 is a schematic diagram of the working waveforms of the dead zone prediction circuit and each signal in the dead zone circuit.
具体实施方式detailed description
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。The technical solutions of the present invention will be further specifically described below through the embodiments and in conjunction with the accompanying drawings.
实施例：Example:
下面结合附图及实施例，对本发明作进一步详细的描述。The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
本发明中的降压型DC-DC变换器包括功率电路和控制电路101两部分。参见图1，控制电路101以外的电路即为功率电路。The step-down DC-DC converter in the present invention includes two parts: a power circuit and a control circuit 101 . Referring to FIG. 1 , the circuits other than the control circuit 101 are power circuits.
参见图1，功率电路的拓扑为降压型。包括有功率开关管SW、同步整流管SR和滤波反馈电路102。功率电路的输入端Vin即为DC-DC变换器的电源输入端，其输出端Vout即为DC-DC变换器的电源输出端。Referring to Figure 1, the topology of the power circuit is a buck type. It includes a power switch tube SW, a synchronous rectifier tube SR and a filter feedback circuit 102 . The input terminal Vin of the power circuit is the power input terminal of the DC-DC converter, and the output terminal Vout thereof is the power output terminal of the DC-DC converter.
参见图2，上述的功率开关管SW由5个宽长比相同的P型MOS管：SW4～SW0并列组成。5个P型MOS管的源极均与电源输入端Vin相连，漏极均连接到开关节点Vsw，栅极分别与控制电路101的输出端口VdriveP<4:0>相连。同样，上述的同步整流管SR由5个宽长比相同的N型MOS管：SR4～SR0并列组成。5个N型MOS管的漏极均连接到开关节点Vsw，源极都连接到地，栅极分别与控制电路101的输出端口VdriveN<4:0>相连。为保证电路正常工作，SW0和SR0始终导通，SW4～SW1和SR4～SR1参加电路工作与否取决于栅宽控制电路104对负载情况的判断。当变换器工作在输出电流最小的阶段，SW4～SW1和SR4～SR1始终处于关断状态。当变换器工作在输出电流最大的阶段，SW4～SW1和SR4～SR1均参加工作，导通时间由栅极控制信号的脉冲宽度确定。Referring to FIG. 2 , the above-mentioned power switch tube SW is composed of five P-type MOS tubes with the same width-to-length ratio: SW4-SW0 arranged side by side. The sources of the five P-type MOS transistors are all connected to the power input terminal Vin, the drains are all connected to the switch node Vsw, and the gates are respectively connected to the output port VdriveP<4:0> of the control circuit 101 . Similarly, the aforementioned synchronous rectifier SR consists of five N-type MOS transistors with the same aspect ratio: SR4-SR0 arranged side by side. The drains of the five N-type MOS transistors are all connected to the switch node Vsw, the sources are all connected to the ground, and the gates are respectively connected to the output port VdriveN<4:0> of the control circuit 101 . In order to ensure the normal operation of the circuit, SW0 and SR0 are always turned on, and whether SW4-SW1 and SR4-SR1 participate in the circuit operation depends on the judgment of the load condition by the gate width control circuit 104 . When the converter works in the stage of minimum output current, SW4~SW1 and SR4~SR1 are always in off state. When the converter works at the stage of maximum output current, SW4~SW1 and SR4~SR1 all participate in the work, and the conduction time is determined by the pulse width of the gate control signal.
上述滤波反馈电路102包括有电感L、电容Cout、电阻R1和R2。其中电感L的一端连接到开关节点Vsw，另一端连接到DC-DC变化器的电源输出端Vout。电容Cout连接在输出端口Vout与地之间，电阻R1和R2串联连接在输出端口与地之间，在R1和R2中间的输出端Vfb连接到控制电路101中脉冲宽度调制模块的输入端。The filter feedback circuit 102 includes an inductor L, a capacitor Cout , and resistors R1 and R2. One end of the inductor L is connected to the switch node Vsw, and the other end is connected to the power output terminal Vout of the DC-DC converter. The capacitor Cout is connected between the output port Vout and the ground, the resistors R1 and R2 are connected in series between the output port and the ground, and the output terminal Vfb between R1 and R2 is connected to the input terminal of the pulse width modulation module in the control circuit 101 .
上述控制电路101采用脉冲宽度调制模式。参见图1，控制电路101包括有电流检测电路103、栅宽控制电路104、逻辑控制与栅极驱动电路105、脉冲宽度调制电路106、死区电路107和死区预测电路108组成。The above-mentioned control circuit 101 adopts a pulse width modulation mode. Referring to FIG. 1 , the control circuit 101 includes a current detection circuit 103 , a gate width control circuit 104 , a logic control and gate drive circuit 105 , a pulse width modulation circuit 106 , a dead zone circuit 107 and a dead zone prediction circuit 108 .
上述电流检测电路103实时检测通过功率开关管的电流大小，并转换为电压信号，并将功率开关管导通期间的检测值进行采样保持，从而得到反映负载电流大小的检测信号Vsense，然后输入到栅宽控制电路104。电流检测电路103的输入端连接到功率电路的开关节点Vsw，输出端Vsense连接到栅宽控制电路104的输入端Vsense。The above-mentioned current detection circuit 103 detects the magnitude of the current passing through the power switch tube in real time, converts it into a voltage signal, and samples and holds the detection value during the conduction period of the power switch tube, so as to obtain a detection signal Vsense reflecting the magnitude of the load current, and then input it to Gate width control circuit 104 . The input terminal of the current detection circuit 103 is connected to the switching node Vsw of the power circuit, and the output terminal Vsense is connected to the input terminal Vsense of the gate width control circuit 104 .
上述栅宽控制电路104用于控制外部功率管的并列个数。使得功率管能够承受相应负载电流的同时具有较小的沟道尺寸，这样就动态减小了功率开关管的栅极寄生电容，从而降低了轻载条件下的驱动损耗，明显提高系统的轻载效率。参见图3，栅宽控制电路104由基准电压电路301、四个比较器com1～com4和逻辑子电路302组成。Vsense为电流检测电路输入的负载电流检测信号，Vsense分别通过四个比较器com1～com4与基准电压电路301提供的四个基准电压Vref1～Vref4进行比较，比较结果分别确定功率电路的MOS管SW和SR中SW4～SW1和SR4～SR1是否参加电路工作。对于参加工作的管子，其控制信号为死区电路输出的脉冲宽度受调制的方波信号DSW和DSR。栅宽控制电路104对功率开关管SW1参加工作与否的判断过程可参见图4。在t1～t2期间内Vsense高于Vref1，Vcom1_out为高电平，相当于SW1使能，说明负载电流大小需要SW1加入到电流的传递工作。经过逻辑子电路的处理，VdriveP1在t1～t2期间是脉冲宽度受调制的方波信号，而t0～t1和t2～t3期间内VdriveP1始终为高电平，SW1关断。同理，SW4～SW2和SR4～SR1都是按照类似的方式确定VdriveP<4:2>和VdriveN<4:1>的波形。为保证电路正常工作，SW0和SR0始终导通，所以DSW和DSR直接转为GSWO和GSRO输出到逻辑控制与驱动电路105，最后转换成为SW0和SR0的栅极控制信号VdrivePO和VdriveNO。The grid width control circuit 104 is used to control the parallel number of external power transistors. This enables the power tube to withstand the corresponding load current while having a smaller channel size, which dynamically reduces the gate parasitic capacitance of the power switch tube, thereby reducing the driving loss under light load conditions and significantly improving the light load of the system. efficiency. Referring to FIG. 3 , the gate width control circuit 104 is composed of a reference voltage circuit 301 , four comparators com1 - com4 and a logic sub-circuit 302 . Vsense is the load current detection signal input by the current detection circuit. Vsense is compared with the four reference voltages Vref1-Vref4 provided by the reference voltage circuit 301 through four comparators com1-com4 respectively, and the comparison results determine the MOS transistors SW and Whether SW4~SW1 and SR4~SR1 in SR participate in circuit work. For the working tubes, the control signals are square wave signals DSW and DSR output by the dead zone circuit with modulated pulse width. Refer to FIG. 4 for the process of judging whether the power switch tube SW1 is working or not by the gate width control circuit 104 . During the period from t1 to t2, Vsense is higher than Vref1, and Vcom1_out is at a high level, which is equivalent to enabling SW1, indicating that the magnitude of the load current requires SW1 to be added to the current transfer work. After processing by the logic sub-circuit, VdriveP1 is a square wave signal whose pulse width is modulated during t1~t2, while VdriveP1 is always at high level during t0~t1 and t2~t3, and SW1 is turned off. Similarly, SW4-SW2 and SR4-SR1 determine the waveforms of VdriveP<4:2> and VdriveN<4:1> in a similar manner. In order to ensure the normal operation of the circuit, SW0 and SR0 are always turned on, so DSW and DSR are directly converted into GSWO and GSRO to output to the logic control and drive circuit 105, and finally converted into gate control signals VdrivePO and VdriveNO .
上述逻辑控制与栅极驱动电路105由一些常用的门级电路和反相器构成，主要用于增强开关信号的驱动能力，其输入信号为两路5bit数据GSW<4:0>和GSR<4:0>；两路5bit输出信号VdriveP<4:0>和VdriveN<4:0>直接驱动对应的功率开关管和同步整流管。The above-mentioned logic control and gate drive circuit 105 is composed of some commonly used gate-level circuits and inverters, and is mainly used to enhance the driving capability of switching signals, and its input signals are two 5-bit data GSW<4:0> and GSR <4:0> ; two 5bit output signals VdriveP <4:0> and VdriveN <4:0> directly drive the corresponding power switch tube and synchronous rectifier tube.
上述脉冲宽度调制电路106根据功率电路中的输出电压反馈信号Vfb调制脉宽固定的方波信号，得到加入死区时间之前的开关信号，即脉冲宽度调制信号Vpwm。脉冲宽度调制电路106的输入端为控制电路的输入端Vfb，输出端Vpwm与死区电路107的输入端相连。The pulse width modulation circuit 106 modulates the square wave signal with fixed pulse width according to the output voltage feedback signal Vfb in the power circuit to obtain the switching signal before adding the dead time, that is, the pulse width modulation signal Vpwm. The input terminal of the pulse width modulation circuit 106 is the input terminal Vfb of the control circuit, and the output terminal Vpwm is connected with the input terminal of the dead zone circuit 107 .
上述死区电路107用于给开关信号加入一定长度的死区时间，包括有两个通道组：SW通道组和SR通道组，分别将Vpwm的上升沿和下降沿进行延迟。这段延迟时间就是死区时间，而延迟时间长短由死区预测电路108输出的两路8bit数据CTL_SW<7:0>和CTL_SR<7:0>控制。参见图6，501为SW通道组，包括有延迟电路503、比较器com_SW、与门and_SW和非门Not_SW组成。502为SW通道组，包括有非门Not_SR、延迟电路504、比较器com_SR和与门and_SR组成。延迟电路503由电容RSW、电容CSWO～CSW7和开关K0～K7组成，电容CSWO～CSW7分别与开关K0～K7串联，K0～K7的导通与关断由预测电路105输出的8bit数据CTL_SW<7:0>控制。当K0导通时电容CSWO并联入延迟电路，从而增加了延迟电路的时间常数，使得延迟时间增加，最后增加了开关信号的死区时间。同理，K1～K7的工作方式也是类似的，K0～K7中导通的开关越多，开关信号中加入的死区时间越长。延迟电路503输出的延迟信号经过比较器com_SW整形后与Vpwm信号相与，以消除第一延迟电路503对Vpwm信号下降沿的影响。与门and_SW输出的信号再经过非门not_SW进行逻辑同步后，得到加入死区的开关信号DSW。SR通道的工作原理也类似，只是非门Not_SR是加到延迟电路之前，用于将Vpwm的下降沿变为上升沿。最后得到加入死区的开关信号DSR。The above-mentioned dead zone circuit 107 is used to add a certain length of dead zone time to the switch signal, including two channel groups: SW channel group and SR channel group, respectively delaying the rising edge and falling edge of Vpwm. This delay time is the dead time, and the length of the delay time is controlled by two channels of 8-bit data CTL_SW<7:0> and CTL_SR<7:0> output by the dead time prediction circuit 108 . Referring to FIG. 6 , 501 is a SW channel group, including a delay circuit 503 , a comparator com_SW, an AND gate and_SW and a NOT gate Not_SW. 502 is a SW channel group, including a NOT gate Not_SR, a delay circuit 504, a comparator com_SR and an AND gate and_SR. The delay circuit 503 is composed of capacitors RSW , capacitors CSWO to CSW7 and switches K0 to K7. Capacitors CSWO to CSW7 are respectively connected in series with switches K0 to K7. The on and off of K0 to K7 are output by the prediction circuit 105 8bit data CTL_SW<7:0> control. When K0 is turned on, the capacitor CSWO is connected in parallel to the delay circuit, thereby increasing the time constant of the delay circuit, increasing the delay time, and finally increasing the dead time of the switching signal. Similarly, the working methods of K1-K7 are similar, the more switches in K0-K7 are turned on, the longer the dead time added to the switching signal. The delayed signal output by the delay circuit 503 is shaped by the comparator com_SW and then ANDed with the Vpwm signal, so as to eliminate the influence of the first delay circuit 503 on the falling edge of the Vpwm signal. After the signal output by the AND gate and_SW is logically synchronized by the NOT gate not_SW, the switching signal DSW added to the dead zone is obtained. The working principle of the SR channel is also similar, except that the NOT gate Not_SR is added before the delay circuit to change the falling edge of Vpwm into a rising edge. Finally, the switching signal DSR added to the dead zone is obtained.
上述死区预测电路108检测出开关信号在该周期存在的死区。然后将实际工作条件下的最佳死区时间长短记录到计数器，计数器输出的两路8bit数据输出到死区电路107。参见图5，死区预测电路108包括或非门Nor、延迟电路601、第一整形电路602、第二整形电路603、第一计数器604和第二计数器605组成。两个输入信号分别是开关节点电压Vsw和第0个同步整流管SR0的栅极驱动电压VdriveNO。Vsw和VdriveNO进行或非后得到Nor_out，Nor_out经过延迟电路601后为Delay。然后在Vsw整形后的上升沿时刻，若Delay为高电平，则第一计数器604减1，否则第一计数器604加1；同样，在VdriveNO整形后的上升沿检测延迟信号Delay，若Delay为高电平，则第二计数器605减1，否则第二计数器605加1。这样在电路稳定工作时，第一计数器604和第二计数器605分别记录Vpwm信号在上升沿和下降沿处的应该加入的最佳死区时间长度。The dead zone predicting circuit 108 detects the dead zone existing in the cycle of the switching signal. Then record the optimal dead zone time under the actual working conditions to the counter, and the two channels of 8-bit data output by the counter are output to the dead zone circuit 107 . Referring to FIG. 5 , the dead zone prediction circuit 108 includes a NOR gate Nor, a delay circuit 601 , a first shaping circuit 602 , a second shaping circuit 603 , a first counter 604 and a second counter 605 . The two input signals are the switch node voltage Vsw and the gate drive voltage VdriveNO of the 0th synchronous rectifier SR0 . Nor_out is obtained after Vsw and VdriveNO are NORed, and Nor_out is Delay after passing through the delay circuit 601 . Then at the rising edge moment after Vsw shaping, if Delay is high level, then the first counter 604 will be decremented by 1, otherwise the first counter 604 will add 1; similarly, the delay signal Delay will be detected on the rising edge of VdriveNO shaping, if Delay is a high level, the second counter 605 is decremented by 1, otherwise the second counter 605 is decremented by 1. In this way, when the circuit works stably, the first counter 604 and the second counter 605 respectively record the optimal dead time lengths that should be added at the rising edge and falling edge of the Vpwm signal.
死区预测电路108和死区电路107中各信号的工作波形可参见图7，Vpwm是脉冲宽度调制模块输出的脉冲宽度调制信号。VdrivePO和VdriveNO分别是DSW和DSR增强驱动能力后的信号。Vsw是开关节点电压。Nor_out是死区预测电路中或非门Nor的输出波形，显示开关信号当前周期内死区存在情况。死区电路107根据第一计数器604中的数据，在Vpwm上升沿加入了死区td1成为DSW；根据第二计数器605中的数据，在Vpwm下降沿加入了死区td2成为DSR。死区预测电路108中Vsw和VdriveNO进行或非后得到的Nor_out，Nor_out中的脉冲即为检测到的死区。其中的死区①、③和⑤是由死区电路107中的SW通路组控制，而死区②和④是由死区电路107中的SR通路组控制。Delay是Nor_out经过延迟电路601后的输出波形。在Vsw上升沿处，Delay是高电平，则死区电路107中的第一计数器604会减1，这意味着死区电路107中延迟电路的时间常数减小。所以Nor_out中T2的死区③比T1的死区①窄，这样一个周期减少一些死区时间，直到死区时间刚好过少时，正如死区②那样，经过延迟的后的波形无法在计数器的时钟跳变沿检测到，此时第二计数器605会加1，死区时间增加。所以在T2周期中的死区④比T1周期的死区②宽。这样动态预测调整死区时间长短，使得开关信号中的死区长短处于最佳长度，减少了不必要的死区浪费。这样的死区预测电路不受电路中其他工作条件的影响，仅关心死区长短是否最小化。The working waveforms of the signals in the dead zone prediction circuit 108 and the dead zone circuit 107 can be seen in FIG. 7 , and Vpwm is the pulse width modulation signal output by the pulse width modulation module. VdrivePO and VdriveNO are the signals after DSW and DSR enhance the driving ability respectively. Vsw is the switch node voltage. Nor_out is the output waveform of the NOR gate Nor in the dead zone prediction circuit, which shows the existence of the dead zone in the current cycle of the switching signal. According to the data in the first counter 604, the dead zone circuit 107 adds a dead zone td1 to become DSW at the rising edge of Vpwm; according to the data in the second counter 605, adds a dead zone td2 to become DSR at the falling edge of Vpwm. Nor_out is obtained after Vsw and VdriveNO are ORed in the dead zone prediction circuit 108, and the pulse in Nor_out is the detected dead zone. The dead zones ①, ③ and ⑤ are controlled by the SW channel group in the dead zone circuit 107, while the dead zones ② and ④ are controlled by the SR channel group in the dead zone circuit 107. Delay is the output waveform of Nor_out after passing through the delay circuit 601 . At the rising edge of Vsw, Delay is at a high level, and the first counter 604 in the dead zone circuit 107 will decrease by 1, which means that the time constant of the delay circuit in the dead zone circuit 107 decreases. Therefore, the dead zone ③ of T2 in Nor_out is narrower than the dead zone ① of T1. Such a cycle reduces some dead zone time until the dead zone time is just too small. Just like the dead zone ②, the delayed waveform cannot be displayed on the clock of the counter. When the transition edge is detected, the second counter 605 will add 1, and the dead time will increase. Therefore, the dead zone ④ in the T2 period is wider than the dead zone ② in the T1 period. In this way, the length of the dead zone is dynamically predicted and adjusted, so that the length of the dead zone in the switching signal is at an optimal length, reducing unnecessary waste of the dead zone. Such a dead zone prediction circuit is not affected by other working conditions in the circuit, and only cares about whether the length of the dead zone is minimized.
本发明提供一种高效率的DC-DC变换器，能将输入的不稳定直流电压降压并高效地转换为较稳定的输出直流电压。该装置中的控制电路101和功率电路中的功率开关管SW和SR可集成到便携电子设备的芯片中，功率电路的其他部分可用分立元件放置在芯片外。The invention provides a high-efficiency DC-DC converter, which can step down an input unstable direct-current voltage and efficiently convert it into a relatively stable output direct-current voltage. The control circuit 101 in the device and the power switch tubes SW and SR in the power circuit can be integrated into the chip of the portable electronic device, and other parts of the power circuit can be placed outside the chip with discrete components.
本文中所描述的具体实施例仅仅是对本发明精神作举例说明。本发明所属技术领域的技术人员可以对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代，但并不会偏离本发明的精神或者超越所附权利要求书所定义的范围。The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which the present invention belongs can make various modifications or supplements to the described specific embodiments or adopt similar methods to replace them, but they will not deviate from the spirit of the present invention or go beyond the definition of the appended claims range.
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| CN201310320182.6ACN103368394B (en) | 2013-07-26 | 2013-07-26 | A kind of efficient voltage reducing type DC-DC converter |
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