技术领域technical field
本发明涉及一种显露穿硅通孔(through silicon via,TSV)的方法。The invention relates to a method for exposing through silicon vias (through silicon via, TSV).
背景技术Background technique
穿硅通孔是一种贯穿硅基材的导体结构，主要功能是用来互连集成电路芯片，其制作方法大体上是先在各芯片预定处形成垂直通孔，再于各通孔内形成绝缘层，于绝缘层上形成晶种层，然后以电镀方法将通孔填满金属，再以晶背研磨使穿硅通孔的一端显露出来。采用这种方式可以大幅缩小芯片尺寸，提高芯片的晶体管密度，改善层间电气互联性能，提升芯片运行速度，降低芯片的功耗。Through-silicon via is a conductor structure that runs through the silicon substrate. Its main function is to interconnect integrated circuit chips. Insulation layer, forming a seed layer on the insulation layer, then filling the through hole with metal by electroplating, and then exposing one end of the TSV through crystal back grinding. In this way, the size of the chip can be greatly reduced, the transistor density of the chip can be increased, the performance of electrical interconnection between layers can be improved, the operating speed of the chip can be increased, and the power consumption of the chip can be reduced.
图1及图2例示一种显露穿硅通孔的公知方法。在完成穿硅通孔的制作后，穿硅通孔20的一端会稍微突出于半导体基板10或硅晶圆的底面，如图1所示，穿硅通孔20包括铜金属层21、阻障层22及绝缘层23，在绝缘层23上最后会覆盖氮化硅层31及硅氧层32。如图2所示，接着，为了显露出穿硅通孔20的铜金属层21，通常会进行化学机械研磨(chemical mechanicalpolishing,CMP)工艺，将硅氧层32、部分的氮化硅层31、绝缘层23及阻障层22磨平去除，其中，氮化硅层31作为一研磨停止层。1 and 2 illustrate a known method for revealing TSVs. After the TSV is completed, one end of the TSV 20 will slightly protrude from the bottom surface of the semiconductor substrate 10 or the silicon wafer. As shown in FIG. 1 , the TSV 20 includes a copper metal layer 21, a barrier The layer 22 and the insulating layer 23 are finally covered with a silicon nitride layer 31 and a silicon oxide layer 32 on the insulating layer 23 . As shown in FIG. 2 , next, in order to expose the copper metal layer 21 of the TSV 20, a chemical mechanical polishing (CMP) process is usually performed, and the silicon oxide layer 32, part of the silicon nitride layer 31, The insulating layer 23 and the barrier layer 22 are ground and removed, wherein the silicon nitride layer 31 serves as a polishing stop layer.
然而，上述晶背研磨或CMP工艺的缺点是会造成浅碟效应。也就是在显露出来的铜金属层21的表面会轻微的向内陷入，此外，也无法显露出穿硅通孔20的部分侧壁，因此最终的穿硅通孔结构并不利于在进行三维立体芯片封装时，实现垂直方向的相互连接。However, the disadvantage of the above-mentioned backgrinding or CMP process is the shallow dish effect. That is, the surface of the exposed copper metal layer 21 will be slightly sunken inward. In addition, part of the sidewall of the TSV 20 cannot be exposed, so the final TSV structure is not conducive to the three-dimensional When the chip is packaged, the interconnection in the vertical direction is realized.
发明内容Contents of the invention
本发明于是提供一种显露穿硅通孔的方法，以解决先前技艺之不足与缺点。The present invention thus provides a method for revealing TSVs to solve the deficiencies and shortcomings of the prior art.
根据本发明一优选实施例，本发明披露一种显露穿硅通孔的方法。首先提供半导体基板，包括第一面及第二面；于所述半导体基板的第一面形成一孔洞；于所述半导体基板的第一面上沉积绝缘层，使绝缘层共形的覆盖住孔洞的侧壁及底面；进行蚀刻工艺，将孔洞底部的绝缘层去除，显露出孔洞底部；于所述孔洞内，包括显露出来的孔洞底部上，覆盖阻障层；于所述孔洞内，填入金属层；于所述半导体基板的第一面上进行化学机械研磨工艺，将所述孔洞之外的金属层、阻障层及绝缘层磨平去除；研磨半导体基板的第二面，去除掉部分厚度的所述半导体基板，从第二面显露出位于孔洞底部的阻障层及部分的绝缘层；进行氮化处理，将显露出的阻障层变为氮化阻障层，将显露出的绝缘层部分氮化变成氮化绝缘层；以及进行蚀刻工艺，分别将所述氮化钽层及氮氧化硅层去除，于所述半导体基板的第二面上显露出穿硅通孔结构的金属层及部分的阻障层的侧壁。According to a preferred embodiment of the present invention, the present invention discloses a method for revealing through silicon vias. First, a semiconductor substrate is provided, including a first surface and a second surface; a hole is formed on the first surface of the semiconductor substrate; an insulating layer is deposited on the first surface of the semiconductor substrate, so that the insulating layer conformally covers the hole The sidewall and bottom surface of the hole; the etching process is performed to remove the insulating layer at the bottom of the hole to reveal the bottom of the hole; in the hole, including the exposed bottom of the hole, cover the barrier layer; in the hole, fill metal layer; performing a chemical mechanical polishing process on the first surface of the semiconductor substrate to remove the metal layer, barrier layer and insulating layer outside the hole; grinding the second surface of the semiconductor substrate to remove part thickness of the semiconductor substrate, the barrier layer and part of the insulating layer at the bottom of the hole are exposed from the second surface; Nitriding treatment is performed to change the exposed barrier layer into a nitrided barrier layer, and the exposed part of the insulating layer is nitrided to become a nitrided insulating layer; and an etching process is performed to remove the tantalum nitride layer and the silicon oxynitride layer respectively, revealing the through-silicon via structure on the second surface of the semiconductor substrate sidewalls of the metal layer and part of the barrier layer.
为让本发明上述目的、特征及优点能更明显易懂，下文特举较佳实施方式，并配合所附图式，作详细说明如下。然而如下的较佳实施方式与图式仅供参考与说明用，并非用来对本发明加以限制者。In order to make the above objects, features and advantages of the present invention more comprehensible, preferred implementation modes are specifically cited below, together with the attached drawings, and described in detail as follows. However, the following preferred embodiments and drawings are for reference and illustration only, and are not intended to limit the present invention.
附图说明Description of drawings
图1及图2例示一种显露穿硅通孔的公知方法。1 and 2 illustrate a known method for revealing TSVs.
图3至图8例示本发明一优选实施例。3 to 8 illustrate a preferred embodiment of the present invention.
其中，附图标记说明如下：Wherein, the reference signs are explained as follows:
10 半导体基底 20 穿硅通孔10 Semiconductor Substrate 20 Through Silicon Via
21 铜金属层 22 阻障层21 Copper metal layer 22 Barrier layer
23 绝缘层 31 氮化硅层23 insulating layer 31 silicon nitride layer
32 硅氧层 100 半导体基底32 Silicon oxide layer 100 Semiconductor substrate
100a 第一面 100b 第二面100a 1st side 100b 2nd side
102 孔洞 112 绝缘层102 Hole 112 Insulation layer
114 阻障层 116 铜金属层114 Barrier layer 116 Copper metal layer
120 穿硅通孔结构 112a 氮化绝缘层120 Through silicon via structure 112a Nitriding insulating layer
114a 氮化阻障层 130 氮化硅层114a Nitride barrier layer 130 Silicon nitride layer
具体实施方式Detailed ways
图3至图8例示本发明一优选实施例。如图3所示，首先提供半导体基板100，包括第一面100a及第二面(或晶圆背面)100b。接着于半导体基板100的第一面100a形成一孔洞102，然后，于半导体基板100的第一面100a上沉积绝缘层112，例如，利用亚常压热化学气相沉积(Sub-Atmospheric PressureThermal Chemical Vapor Deposition，SACVD)形成的TEOS硅氧层，使绝缘层112共形的覆盖住孔洞的侧壁及底面。绝缘层112同时覆盖住半导体基板100的第一面100a。3 to 8 illustrate a preferred embodiment of the present invention. As shown in FIG. 3 , firstly, a semiconductor substrate 100 is provided, including a first surface 100 a and a second surface (or wafer back surface) 100 b. Next, a hole 102 is formed on the first surface 100a of the semiconductor substrate 100, and then an insulating layer 112 is deposited on the first surface 100a of the semiconductor substrate 100, for example, by using sub-atmospheric pressure thermal chemical vapor deposition (Sub-Atmospheric Pressure Thermal Chemical Vapor Deposition) , SACVD) formed TEOS silicon oxide layer, so that the insulating layer 112 conformally covers the sidewall and bottom surface of the hole. The insulating layer 112 also covers the first surface 100 a of the semiconductor substrate 100 .
如图4所示，进行蚀刻工艺，例如各向异性刻蚀，将孔洞102底部的绝缘层112去除，显露出孔洞102底部。之后，如图5所示，继续在孔洞102内，包括显露出来的孔洞102底部上，覆盖阻障层114，例如厚度约600埃(angstrom)的钽(Ta)金属，再填入铜金属层116，使铜金属层116填满孔洞102。然后，进行化学机械研磨(CMP)工艺，将孔洞102之外，位于半导体基板100的第一面100a上的多余铜金属层116、阻障层114及绝缘层112磨平去除。此时，初步完成穿硅通孔结构120，包括铜金属层116、阻障层114及绝缘层112。As shown in FIG. 4 , an etching process, such as anisotropic etching, is performed to remove the insulating layer 112 at the bottom of the hole 102 to reveal the bottom of the hole 102 . Afterwards, as shown in FIG. 5 , continue to cover the barrier layer 114 in the hole 102, including the exposed bottom of the hole 102, such as tantalum (Ta) metal with a thickness of about 600 angstrom, and then fill it with a copper metal layer. 116 , making the copper metal layer 116 fill the hole 102 . Then, a chemical mechanical polishing (CMP) process is performed to remove the redundant copper metal layer 116 , the barrier layer 114 and the insulating layer 112 on the first surface 100 a of the semiconductor substrate 100 outside the hole 102 . At this point, the TSV structure 120 is preliminarily completed, including the copper metal layer 116 , the barrier layer 114 and the insulating layer 112 .
如图6所示，接着，进行晶圆背面研磨(wafer backside grinding)工艺或化学机械研磨工艺，研磨半导体基板100的第二面100b，去除掉部分厚度的半导体基板100，从第二面100b显露出位于孔洞102底部的阻障层114及部分的绝缘层112。As shown in FIG. 6, then, a wafer backside grinding (wafer backside grinding) process or a chemical mechanical grinding process is carried out to grind the second surface 100b of the semiconductor substrate 100, remove the semiconductor substrate 100 with a partial thickness, and expose it from the second surface 100b The barrier layer 114 and part of the insulating layer 112 at the bottom of the hole 102 are exposed.
如图7所示，接着，针对半导体基板100的第二面100b进行氮化处理，将显露出的阻障层114变为氮化阻障层114a，例如氮化钽层，并将显露出的绝缘层112变为氮化绝缘层112a，例如氮氧化硅层，同时于半导体基板100的第二面100b上形成氮化硅层130。As shown in FIG. 7, then, nitriding treatment is performed on the second surface 100b of the semiconductor substrate 100, and the exposed barrier layer 114 is changed into a nitrided barrier layer 114a, such as a tantalum nitride layer, and the exposed The insulating layer 112 becomes a nitrided insulating layer 112 a, such as a silicon oxynitride layer, and a silicon nitride layer 130 is formed on the second surface 100 b of the semiconductor substrate 100 .
如图8所示，接着，进行蚀刻工艺，分别将氮化阻障层114a及氮化绝缘层112a去除，即于半导体基板100的第二面100b上显露出穿硅通孔结构120的铜金属层116及部分的阻障层114的侧壁。As shown in FIG. 8, an etching process is then performed to remove the nitride barrier layer 114a and the nitride insulating layer 112a respectively, that is, the copper metal of the TSV structure 120 is exposed on the second surface 100b of the semiconductor substrate 100. layer 116 and part of the sidewalls of barrier layer 114 .
本发明的优点在于能够显露出穿硅通孔的部分侧壁，而避免了浅碟现象。于半导体基板100的第二面100b上显露出来的穿硅通孔，其稍微突出于绝缘层112，故在进行三维立体芯片封装时，能够可靠的实现垂直方向的相互连接。The advantage of the present invention is that part of the sidewall of the TSV can be exposed, and the shallow dish phenomenon is avoided. The TSVs exposed on the second surface 100 b of the semiconductor substrate 100 slightly protrude from the insulating layer 112 , so that vertical interconnections can be reliably achieved during three-dimensional chip packaging.
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210102680.9ACN103367241B (en) | 2012-04-09 | 2012-04-09 | Method to expose through-silicon vias |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210102680.9ACN103367241B (en) | 2012-04-09 | 2012-04-09 | Method to expose through-silicon vias |
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| CN103367241A CN103367241A (en) | 2013-10-23 |
| CN103367241Btrue CN103367241B (en) | 2015-05-27 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201210102680.9AActiveCN103367241B (en) | 2012-04-09 | 2012-04-09 | Method to expose through-silicon vias |
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| US10734308B2 (en)* | 2018-11-20 | 2020-08-04 | Nanya Technology Corporation | Semiconductor device and method for manufacturing the same |
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| CN102157365A (en)* | 2010-02-12 | 2011-08-17 | 台湾积体电路制造股份有限公司 | Methods of Thinning Wafers |
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| CN101752336A (en)* | 2008-12-10 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN102157365A (en)* | 2010-02-12 | 2011-08-17 | 台湾积体电路制造股份有限公司 | Methods of Thinning Wafers |
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