CN103354416A

Movatterモバイル変換

Info

Publication number: CN103354416A
Application number: CN2013102932523A
Authority: CN
Inventors: 郑儒富
Original assignee: Individual
Current assignee: Individual
Priority date: 2013-07-14
Filing date: 2013-07-14
Publication date: 2013-10-16

Abstract

A switch power supply circuit comprises an input voltage source providing an input voltage, an inductor, a power switch tube and an average-mode constant current control circuit, wherein the inductor possesses a first terminal and a second terminal, and the first terminal is coupled with the input voltage source; the power switch tube possesses the first terminal, the second terminal and a third terminal, and the first terminal is coupled with the second terminal of the inductor; the average-mode constant current control circuit is coupled with the second terminal and the third terminal of the power switch tube. The average-mode constant current control circuit comprises a current detection circuit, an average value circuit, a comparison circuit, a timing circuit and a latch circuit, wherein the current detection circuit possesses the first terminal and the second terminal, the first terminal is coupled with the third terminal of the power switch tube, the second terminal is coupled with reference ground, and the current detection circuit is used to detect a current which flows through the power switch tube and output a current detection signal; the average value circuit is coupled with the current detection signal and the second terminal of the power switch tube and outputs an average value signal; the comparison circuit is coupled with the average value signal and the current detection signal and outputs a reset signal; the timing circuit outputs a setting signal; the latch circuit is coupled with the setting signal and the reset signal and outputs a pulse width modulation signal; the pulse width modulation signal is coupled with the second terminal of the power switch tube and the average value circuit.

Description

A kind of average mode constant-current control circuit and control method

Technical field

The present invention relates to constant current control technology field, relate in particular to a kind of average mode constant-current control circuit and control method.

Background technology

In the switching power circuit, because the non-ideal characteristic of control loop time-delay and actual power switching tube switch causes output current or voltage in the time of (also claiming input voltage, supply voltage), to have inconsistent phenomenon at not collinear voltage; Its essential reason is that control loop exists inherent delay, cause the current detection signal set point that surpasses reference voltage in various degree on the current sense resistor, shown in Figure 1A, thereby the value that output current or voltage and reference voltage are set is different, and the impact that not collinear voltage produces is also different.Traditional solution is to compensate the output bias that causes under the not collinear voltage by the direct-detection input line voltage.A kind of specific implementation circuit of prior art switching power circuit as shown in Figure 1B, switching power circuit comprisesinput voltage source 101,load circuit 102,inductance 103, fly-wheel diode 104,power switch pipe 105,current sense resistor 106 and theexisting control circuit 100 that input voltage is provided; Also comprise simultaneously the first compensatingresistance 107 and the second compensatingresistance 108 of realizing linevoltage compensation.By resistance 107 andresistance 108 proportional sampling input voltages, on thecurrent sense resistor 106 that then is added to, the voltage drop on thecurrent sense resistor 106 is compared with busbar voltage and can be ignored.

Ideally, if there is not the control loop time-delay, the voltage on the current sense resistor is only determined by the reference voltage Vref of comparator:

(1)

In fact the voltage relationship on reference voltage and the current sense resistor is:

(2)

Non-ideal factor causes the voltage overshoot on the current sense resistor to be:

(3)

Prior art sampling busbar voltage, the available relation of compensation overshoot voltage is as follows:

(4)

Wherein Vm is input voltage, and Vm/L is the inductive current slope, and Ton is the closing time of power switch pipe, and Rcs is the resistance ofcurrent sense resistor 106, is the inherent delay of control loop.Can find out, the overshoot voltage on the current sense resistor is relevant with the absolute value of busbar voltage, inductance value, inherent delay and current sense resistor.Traditional line voltage replenishes technology by detecting busbar voltage Vm, adjust simultaneously the value of compensating resistance Rc1 and Rc2, can eliminate overcharged voltage under certain condition, if but inductance value changes, or detect the value that resistance changes all needs to readjust compensating resistance, and the compensating resistance of traditional line voltage compensation technology also can increase cost and the power consumption of constant-current control circuit, reduces conversion efficiency.In the small-power switching power-supply system of being particular about efficient and cost, traditional method is more and more improper.

Summary of the invention

In order to solve the shortcoming of prior art, the present invention proposes a kind of average mode constant-current control circuit and control method, can solve well that prior art faces problem.

The present invention at first discloses a kind of switching power circuit, and described switching power circuit comprises at least: the input voltage source that input voltage is provided; Inductance has first end and the second end, and first end and input voltage source couple; Power switch pipe has first end, the second end and the 3rd end, and second of first end and inductance couples; Described switching power circuit also comprises the average mode constant-current control circuit that couples with power switch pipe the second end and the 3rd end, described average mode constant-current control circuit comprises: current detection circuit, have first end and the second end, the 3rd end of first end and power switch pipe couples, couple to the second end and reference, for detection of the electric current that flows through power switch pipe, and export a current detection signal; Averaging circuit couples with the second end of described current detection signal and power switch pipe, exports an average value signal; Comparison circuit couples with described average value signal and current detection signal, exports a reset signal; Timing circuit is exported an asserts signal; And latch cicuit, couple with described asserts signal and reset signal, export a pulse width modulating signal, the second end and the averaging circuit of described pulse width modulating signal and power switch pipe couple.

In one embodiment, the input voltage that provides of described input voltage source comprises: direct voltage or the alternating voltage of the direct voltage of AC-DC converter output, DC-to-DC converter output directly pass through the later direct voltage of rectifier bridge.

In one embodiment, described power switch pipe comprises: field-effect transistor (FET), bipolar transistor (BJT).

In one embodiment, described current detection circuit is a resistance.

In one embodiment, described averaging circuit comprises: sampling control circuit, and pulse width modulating signal, reference voltage and the current detection signal of input and the output of described latch cicuit couple, and export the first sampled signal and the second sampled signal; Error amplifying circuit has two inputs, couples with two output signals of described sampling control circuit, exports an average value signal.

In one embodiment, described sampling control circuit comprises: the first inverter, and the input of inverter and described pulse width modulating signal couple, the inverted signal of output output pulse width modulation signal; The first switch, first end and the reference voltage of switch couple, and the second end and pulse width modulating signal couple, and the 3rd end is exported the first sampled signal; Second switch, the first end of switch and the first sampled signal couple, and the inverted signal of the second end and pulse width modulating signal couples, and couples to the 3rd end and reference; The 3rd switch, first end and the current detection signal of switch couple, and the second end and pulse width modulating signal couple, and the 3rd end is exported the second sampled signal; The 4th switch, the first end of switch and the second sampled signal couple, and the inverted signal of the second end and pulse width modulating signal couples, and couples to the 3rd end and reference.

In one embodiment, described error amplifying circuit comprises: the first error amplifier with two inputs and an output, the first input end of error amplifier and the first sampled signal couple, and the second input and the second sampled signal couple, and output is exported an average value signal; Integrating capacitor, the output of the first end of electric capacity and the first error amplifier couples, and couples to the second end and reference.

In one embodiment, described comparison circuit comprises a comparator, comparator has two inputs and an output, first input end and described average value signal couple, the second input and described current detection signal couple, during more than or equal to average value signal, export a reset signal at current detection signal.

In one embodiment, timing circuit is a fixed frequency oscillating circuit, produces a fixed time period T, through after the set time T, exports an asserts signal.

In one embodiment, timing circuit is a set time delay circuit, and after pulse width modulating signal became logic low, timing circuit was delayed time after a set time, exported an asserts signal.

In one embodiment, timing circuit detects the valley of inductive current, when the valley point current that detects inductive current is a set point, exports an asserts signal.

In one embodiment, latch cicuit comprises a rest-set flip-flop at least, and set end and the described asserts signal of trigger couple, and the reset terminal of trigger and described reset signal couple, and the Q output of trigger is exported a pulse width modulating signal.

In one embodiment, described switching power circuit also comprises the fly-wheel diode that couples with inductance in parallel, and with the load circuit of inductance coupled in series.

In one embodiment, described switching power circuit also comprises the fly-wheel diode that couples with inductance in parallel, and with the load circuit of fly-wheel diode coupled in series.

In one embodiment, described switching power circuit comprises the transformer that has at least a main winding and a level winding, first end and the input voltage source of transformer main winding couple, the first end of the second end and described power switch pipe couples, one end of the first end of secondary winding and fly-wheel diode couples, couple to the second end and reference

In one embodiment, described timing circuit detects the valley of transformer secondary output winding current, when the valley that detects the transformer secondary output winding current is a set point, exports an asserts signal.

According to embodiments of the invention, a kind of control method of average mode constant-current control circuit has also been proposed, adopt the switching power circuit of described control method to comprise at least power switch pipe and the inductance or the transformer that are coupled to described power switch pipe, closed and disconnected along with power switch pipe, described inductance or transformer storage and output energy, the control method of described average mode constant-current control circuit may further comprise the steps:

A. inductive current or transformer main winding current detecting step: at the power switch pipe period of contact, detect and flow through the electric current of described power switch pipe, and produce a current detection signal;

B. reference voltage sampling step: at the power switch pipe period of contact, the sampling reference voltage, and produce the first sampled signal;

C. inductive current or transformer main winding current sampling step: at the power switch pipe period of contact, the sample rate current detection signal, and generate the second sampled signal;

D. mean value calculation step: to the first sampled signal and the second sampled signal value of averaging computing, and produce an average value signal;

E. inductive current or transformer main winding current peak value control step: compare with average value signal and current detection signal, when current detection signal during more than or equal to average value signal, power switch pipe is disconnected;

F. inductive current or transformer secondary output winding current valley are controlled step, and after power switch pipe disconnected, timing circuit was closed with power switch pipe after a special time;

G. steps A-F consists of the cycle of operation, and at described switching power circuit duration of work, steps A-F repetitive cycling operation realizes average mode constant current control.

In one embodiment, the timing circuit that adopts the switching power circuit of described control method is a fixed frequency oscillating circuit, produces a fixed time period T, and is through after the set time T, that power switch pipe is closed.

In one embodiment, the timing circuit that adopts the switching power circuit of described control method is a set time delay circuit, after pulse width modulating signal PWM became logic low, timing circuit was delayed time after the set time Tdelay, and power switch pipe is closed.

In one embodiment, adopt the timing circuit of the switching power circuit of described control method to detect the valley of inductive current, or transformer secondary output winding current valley, when detecting valley point current and be a set point, that power switch pipe is closed.

Compared with prior art, the helpfulness effect of technology provided by the present invention is: not only eliminated output voltage or current deviation that not collinear voltage causes, and can eliminate current sense resistor and inductance value and change the output bias that causes, power loss and cost that the extra resistance that also having eliminated simultaneously increases is brought increase, and have also improved the reliability of system simultaneously.

Description of drawings

Figure 1A is depicted as the current detection signal overshoot oscillogram that causes because of the control loop inherent delay.

Figure 1B is depicted as the application block diagram of a kind of switching power circuit that adopts prior art.

Fig. 2 A is depicted as the circuit structure diagram according to the first embodiment of the present invention.

Fig. 2 B is depicted as according to averaging circuit structure chart of the present invention.

Fig. 2 C is depicted as according to the first oscillogram of the present invention.

Fig. 2 D is depicted as according to the second oscillogram of the present invention.

Fig. 2 E is depicted as according to the 3rd oscillogram of the present invention.

Figure 3 shows that the circuit structure diagram according to the second embodiment of the present invention.

Figure 4 shows that the circuit structure diagram according to the third embodiment of the present invention.

Drawing reference numeral

100 existing control circuits; 101 input voltage sources; 102 load circuits; 103 inductance; 104 fly-wheel diodes; 105 power switch pipes; 106 current detection circuits; 107 first compensating resistances; 108 second compensating resistances; 200 control circuits of the present invention; 201 averaging circuits; 202 comparison circuits; 203 latch cicuits; 204 timing circuits; 210 error amplifying circuits; 211 integrating capacitors; 212 first error amplifiers; 220 sampling control circuits; 221 first switches; 222 second switches; 223 the 3rd switches; 224 the 4th switches; 225 first inverters; 300 control circuits of the present invention; 301 transformers; 400 control circuits of the present invention

Embodiment

The below will describe specific embodiments of the invention in detail, should be noted that the embodiments described herein only is used for illustrating, and be not limited to the present invention.In the following description, in order to provide thorough understanding of the present invention, a large amount of specific detail have been set forth.Yet, it is evident that for those of ordinary skills: needn't adopt these specific detail to carry out the present invention.In other embodiments, for fear of obscuring the present invention, do not specifically describe known circuit, material or method.

In whole specification, " embodiment ", " embodiment ", " example " or mentioning of " example " are meaned: special characteristic, structure or characteristic in conjunction with this embodiment or example description are comprised among at least one embodiment of the present invention.Therefore, phrase " in one embodiment ", " in an embodiment ", " example " or " example " that occurs in each place of whole specification differs to establish a capital and refers to same embodiment or example.In addition, can with any suitable combination and/or sub-portfolio with specific feature, structure or characteristic, be combined in one or more embodiment or the example.In addition, it should be understood by one skilled in the art that at this accompanying drawing that provides all be for illustrative purposes, and accompanying drawing is drawn in proportion not necessarily.Should be appreciated that when claiming element " connection ", " being connected to " or " coupling ", " being couple to " another element, it can be directly to connect or be couple to another element or can have intermediary element.On the contrary, when claiming element " to be directly connected to " or during " being directly coupled to " another element, not having intermediary element.The identical identical element of Reference numeral indication.Term used herein " and/or " comprise any and all combinations of one or more relevant projects of listing.

Fig. 2 A is depicted as the structure chart according to a kind of switching power circuit of the present invention, and Fig. 2 B is respectively its electronic circuit: the structure chart ofsampling control circuit 220 anderror amplifying circuit 210, Fig. 2 C-Fig. 2 E are according to work wave schematic diagram of the present invention.Set forth operation principle of the present invention below in conjunction with Fig. 2 A-Fig. 2 E.

Comprise according to switching power circuit of the present invention: theinput voltage source 101 that input voltage Vm is provided;Load circuit 102 has first end and the second end, and first end andinput voltage source 101 couple;Inductance 103 has first end and the second end, and the second end of first end andload circuit 102 couples;Power switch pipe 105 has first end, the second end and the 3rd end, and the second end of first end andinductance 103 couples; Fly-wheel diode 104 has first end and the second end, and the common node of first end andinput voltage source 101 andload circuit 102 couples, and the common node of the second end andinductance 103 andpower switch pipe 105 couples; Described switching power circuit also comprises the average mode constant-current control circuit 200 that couples withpower switch pipe 105 second ends and the 3rd end, described average mode constant-current control circuit 200 comprises:current detection circuit 106, have first end and the second end, the 3rd end of first end andpower switch pipe 105 couples, couple to the second end and reference, for detection of the electric current that flows throughpower switch pipe 105, and export a current detection signal Vcs; Averagingcircuit 201 couples with the second end of described current detection signal Vcs andpower switch pipe 105, exports an average value signal Veao;Comparison circuit 202 couples with described average value signal Veao and current detection signal Vcs, exports a reset signal Rset;Timing circuit 204 is exported an asserts signal Set; Andlatch cicuit 203, couple with described asserts signal Set and reset signal Rset, export a pulse width modulating signal PWM, the second end and theaveraging circuit 201 of described pulse width modulating signal PWM andpower switch pipe 105 couple.

In one embodiment, the input voltage Vm that provides of describedinput voltage source 101 comprises: direct voltage or the alternating voltage of the direct voltage of AC-DC converter output, DC-to-DC converter output directly pass through the later direct voltage of rectifier bridge.

In one embodiment, describedpower switch pipe 105 comprises: field-effect transistor (FET), bipolar transistor (BJT).

In one embodiment, describedcurrent detection circuit 106 is a resistance.

In one embodiment, describedaveraging circuit 201 comprises:sampling control circuit 220, pulse width modulating signal PWM, reference voltage Vref and the current detection signal Vcs of input and 203 outputs of described latch cicuit couple, and export the first sampled signal Vrefon and the second sampled signal Vcson;Error amplifying circuit 210 has two inputs, couples with two output signals of describedsampling control circuit 220, exports an average value signal Veao.

In one embodiment, described sampling control circuit 220 comprises: the first inverter 225, and the input of inverter 225 and described pulse width modulating signal PWM couple the inverted signal PWMB of output pulse width modulation signal; The first switch 221, first end and the reference voltage Vref of switch 221 couple, and the second end and pulse width modulating signal PWM couple, and the 3rd end is exported the first sampled signal Vrefon; Second switch 222, the first end of switch 222 and the first sampled signal Vrefon couple, and the inverted signal PWMB of the second end and pulse width modulating signal couples, and couples to the 3rd end and reference; The 3rd switch 223, the first end of switch 223 and current detection signal Vcs couple, and the second end and pulse width modulating signal PWM couple, and the 3rd end is exported the second sampled signal Vcson; The 4th switch 224, the first end of switch 224 and the second sampled signal Vcson couple, and the inverted signal PWMB of the second end and pulse width modulating signal couples, and couples to the 3rd end and reference.During pulse width modulating signal PWM is logic high, the first switch 221 and the 3rd switch 223 are closed simultaneously, second switch 222 and the 4th switch 224 disconnect simultaneously, so pulse width modulating signal PWM be logic high during, the first sampled signal Vrefon equals reference voltage Vref; The second sampled signal Vcson equals current detection signal.Error amplifying circuit 210 the mean value error accumulation between the first sampled signal Vrefon and the second sampled signal Vcson in integrating capacitor 211; During pulse width modulating signal PWM is logic low, the first switch 221 and the 3rd switch 223 disconnect simultaneously, second switch 222 and the 4th switch 224 are closed simultaneously, so pulse width modulating signal PWM be logic low during, the first sampled signal Vrefon equals the second sampled signal Vcson level that equals zero, and the mean value error between the first sampled signal Vrefon and the second sampled signal Vcson is zero; So in the whole cycle, by the reference voltage Vref decision, the mean value error accumulation between the two is in integrating capacitor 211 fully for the current average of inductance 103 at pulse width modulating signal PWM.The effect of timing circuit 204 is the mode of operations that determine whole switching power circuit, and described mode of operation has determined the electric current valley of inductive current.In one embodiment, timing circuit 204 is the oscillator of a fixed frequency, produces a fixed time period T, produces an asserts signal Set at the rising edge of fixed time period T, and closed power switching tube 105 begins inductance 103 chargings.The time of inductance 103 charging is designated as Ton, and the time of inductance 103 discharges is designated as Toff, as fixed time period T〉during Ton+Toff, whole switching power circuit works in discontinous mode (DCM pattern), shown in Fig. 2 C; When fixed time period T=Ton+Toff, whole switching power circuit works in critical current mode conduction mode (CRM pattern), shown in Fig. 2 E; When fixed time period T＜Ton+Toff, whole switching power circuit works in continuous current mode pattern (CCM pattern), shown in Fig. 2 D.In one embodiment, timing circuit 204 is a set time delay circuit, after pulse width modulating signal PWM becomes logic low, behind set time Tdelay of timing circuit 204 time-delays, export an asserts signal Set, closed power switching tube 105 begins inductance 103 chargings.The time of inductance 103 charging is designated as Ton, and the time of inductance 103 discharges is designated as Toff, as delay time Tdelay〉during Ton+Toff, whole switching power circuit works in discontinous mode (DCM pattern), shown in Fig. 2 C; When delay time Tdelay=Ton+Toff, whole switching power circuit works in critical current mode conduction mode (CRM pattern), shown in Fig. 2 E; When delay time Tdelay＜Ton+Toff, whole switching power circuit works in continuous current mode pattern (CCM pattern), shown in Fig. 2 D.In one embodiment, timing circuit 204 detects the inductive current valleies, when detecting the inductive current valley and be a set point, exports an asserts signal Set, and closed power switching tube 105 begins inductance 103 chargings.When described electric current valley greater than zero the time, whole switching power circuit works in continuous current mode pattern (CCM pattern), shown in Fig. 2 D; When described electric current valley equalled zero, whole switching power circuit worked in critical current mode conduction mode (CRM pattern), shown in Fig. 2 E; When described electric current valley less than zero the time, whole switching power circuit works in discontinous mode (DCM pattern), shown in Fig. 2 C.

In one embodiment, describederror amplifying circuit 210 comprises: thefirst error amplifier 212 with two inputs and an output, the first input end oferror amplifier 212 and the first sampled signal Vrefon couple, the second input and the second sampled signal Vcson couple, and output is exported an average value signal Veao; Integratingcapacitor 211, the output of the first end ofelectric capacity 211 and thefirst error amplifier 212 couples, and couples to the second end and reference.The mean value error of accumulation the first sampled signal Vrefon and the second sampled signal Vcson in the integratingcapacitor 211.

In one embodiment, describedcomparison circuit 202 comprises a comparator, comparator has two inputs and an output, first input end and described average value signal Veao couple, the second input and described current detection signal Vcs couple, and during more than or equal to average value signal Veao, export a reset signal Rset at current detection signal Vcs, disconnectpower switch pipe 105, stopinductance 103 chargings.Therefore the peak current ILpk ofinductance 103 is only determined by described average value signal Veao.

In one embodiment, latchcicuit 203 comprises a rest-set flip-flop at least, set end and the described asserts signal Set of trigger couple, and the reset terminal of trigger and described reset signal Rset couple, and the Q output of trigger is exported a pulse width modulating signal PWM.

In one embodiment, described switching power circuit also comprises the fly-wheel diode 104 withinductance 103 coupled in parallel, and with theload circuit 102 ofinductance 103 coupled in series, such as Fig. 2 A.

In one embodiment, described switching power circuit also comprises the fly-wheel diode 104 withinductance 103 coupled in parallel, and with theload circuit 102 of fly-wheel diode 104 coupled in series, such as Fig. 4.

In one embodiment, described switching power circuit comprises the transformer 301 that has at least a main winding and a level winding, first end and theinput voltage source 101 of transformer 301 main windings couple, the first end of the second end and describedpower switch pipe 105 couples, the first end of transformer 301 secondary winding and an end of fly-wheel diode 104 couple, couple to the second end and reference, such as Fig. 3.

According to embodiments of the invention, a kind of control method of average mode constant-current control circuit has also been proposed, adopt the switching power circuit of described control method to comprise at leastpower switch pipe 105 and theinductance 103 or the transformer 301 that are coupled to describedpower switch pipe 105, closed and disconnected along withpower switch pipe 105, describedinductance 103 or transformer 301 storages and output energy, the control method of described average mode constant-current control circuit may further comprise the steps:

A. inductance 103 electric currents or transformer 301 main winding current detecting steps: atpower switch pipe 105 periods of contact, detect and flow through the electric current of describedpower switch pipe 105, and produce a current detection signal Vcs;

B. reference voltage Vref sampling step: atpower switch pipe 105 periods of contact, the sampling reference voltage Vref, and produce the first sampled signal Vrefon;

C. inductance 103 electric currents or transformer 301 main winding current sampling step: atpower switch pipe 105 periods of contact, sample rate current detection signal Vcs, and generate the second sampled signal Vcson;

D. mean value calculation step: to the first sampled signal Vrefon and the second sampled signal Vcsoon value of averaging computing, and produce an average value signal Veao;

E. inductance 103 electric currents or transformer 301 main winding current peak values control step: compare with average value signal Veao and current detection signal Vcs, as current detection signal Vcs during more than or equal to average value signal Veao, withpower switch pipe 105 disconnections;

F. inductance 103 electric currents or transformer 301 secondary winding electric current valleies control step, afterpower switch pipe 105 disconnects,timing circuit 204 after a special time withpower switch pipe 105 closures;

In one embodiment, adopting thetiming circuit 204 of the switching power circuit of described control method is a fixed frequency oscillating circuit, produces a fixed time period T, through after the set time T, withpower switch pipe 105 closures.

In one embodiment, thetiming circuit 204 that adopts the switching power circuit of described control method is a set time delay circuit, after pulse width modulating signal PWM becomes logic low, after thetiming circuit 204 time-delays one set time Tdelay, withpower switch pipe 105 closures.

In one embodiment, adopt thetiming circuit 204 of the switching power circuit of described control method to detect the valley ofinductance 103 electric currents, or transformer 301 secondary winding electric current valleies, when detecting valley point current and be a set point, withpower switch pipe 105 closures.

Although described the present invention with reference to several exemplary embodiments, should be appreciated that used term is explanation and exemplary, nonrestrictive term.Because the present invention is implementation and do not break away from spirit or the essence of invention in a variety of forms, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and should be in the spirit and scope that the claim of enclosing limits explain widely, therefore fall into whole variations in claim or its equivalent scope and remodeling and all should be the claim of enclosing and cover.

Claims

1. switching power circuit, described switching power circuit comprises:

The input voltage source of input voltage is provided;

Inductance has first end and the second end, and first end and input voltage source couple;

Power switch pipe has first end, the second end and the 3rd end, and second of first end and inductance couples; Described switching power circuit also comprises the average mode constant-current control circuit that couples with power switch pipe the second end and the 3rd end, and described average mode constant-current control circuit comprises:

Current detection circuit has first end and the second end, and the 3rd end of first end and power switch pipe couples, and couples to the second end and reference, and for detection of the electric current that flows through power switch pipe, and exports a current detection signal;

Averaging circuit couples with the second end of described current detection signal and power switch pipe, exports an average value signal;

Comparison circuit couples with described average value signal and current detection signal, exports a reset signal;

Timing circuit is exported an asserts signal; And

Latch cicuit couples with described asserts signal and reset signal, exports a pulse width modulating signal, and the second end and the averaging circuit of described pulse width modulating signal and power switch pipe couple.

2. switching power circuit according to claim 1, it is characterized in that, the input voltage that described input voltage source provides comprises: direct voltage or the alternating voltage of the direct voltage of AC-DC converter output, DC-to-DC converter output directly pass through the later direct voltage of rectifier bridge.

3. switching power circuit according to claim 1 is characterized in that, described power switch pipe comprises: field-effect transistor (FET), bipolar transistor (BJT).

4. switching power circuit according to claim 1 is characterized in that, described current detection circuit is a resistance.

5. switching power circuit according to claim 1 is characterized in that, described averaging circuit comprises:

Sampling control circuit, pulse width modulating signal, reference voltage and the current detection signal of input and the output of described latch cicuit couple, and export the first sampled signal and the second sampled signal;

Error amplifying circuit has two inputs, couples with two output signals of described sampling control circuit, exports an average value signal.

6. switching power circuit according to claim 5 is characterized in that, described sampling control circuit comprises: the first inverter, and the input of inverter and described pulse width modulating signal couple, the inverted signal of output pulse width modulation signal; The first switch, first end and the reference voltage of switch couple, and the second end and pulse width modulating signal couple, and the 3rd end is exported the first sampled signal; Second switch, the first end of switch and the first sampled signal couple, and the inverted signal of the second end and pulse width modulating signal couples, and couples to the 3rd end and reference; The 3rd switch, first end and the current detection signal of switch couple, and the second end and pulse width modulating signal couple, and the 3rd end is exported the second sampled signal; The 4th switch, the first end of switch and the second sampled signal couple, and the inverted signal of the second end and pulse width modulating signal couples, and couples to the 3rd end and reference.

7. switching power circuit according to claim 5, it is characterized in that, described error amplifying circuit comprises: the first error amplifier with two inputs and an output, the first input end of error amplifier and the first sampled signal couple, the second input and the second sampled signal couple, and output is exported an average value signal; Integrating capacitor, the output of the first end of electric capacity and the first error amplifier couples, and couples to the second end and reference.

8. switching power circuit according to claim 1, described comparison circuit comprises a comparator, comparator has two inputs and an output, first input end and described average value signal couple, the second input and described current detection signal couple, during more than or equal to average value signal, export a reset signal at current detection signal.

9. switching power circuit according to claim 1, described timing circuit is a fixed frequency oscillating circuit, produces a fixed time period T, through after the set time T, exports an asserts signal.

10. switching power circuit according to claim 1, described timing circuit is a set time delay circuit, after pulse width modulating signal became logic low, timing circuit was delayed time after a set time, exported an asserts signal.