CN103346787A - Phase-locked loop frequency synthesizer structure with automatic frequency correction - Google Patents

Abstract

Translated fromChinese

本发明公开了一种带有自动频率校正电路的锁相环频率综合器电路结构，它通过对流片生产后的锁相环电路的各个频带范围进行测量，得出对压控振荡器选择不同频带的控制编码对应的实际频率范围，由于实际中锁相环频率综合器通过改变反馈回路的分频比来控制输出信号的频率，得到控制编码对应的实际频率范围之后据此建立分频比编码到频带控制编码的查找表，相比已有的锁相环频率综合器，可以实现通过一次测试校正之后，在运行时实现快速获得正确的频带控制编码。

The invention discloses a phase-locked loop frequency synthesizer circuit structure with an automatic frequency correction circuit. It measures the range of each frequency band of the phase-locked loop circuit after tape-out production, and obtains that different frequency bands can be selected for the voltage-controlled oscillator. The actual frequency range corresponding to the control code, because in practice, the phase-locked loop frequency synthesizer controls the frequency of the output signal by changing the frequency division ratio of the feedback loop, and after obtaining the actual frequency range corresponding to the control code, the frequency division ratio code is established accordingly. The look-up table of the frequency band control code, compared with the existing phase-locked loop frequency synthesizer, can quickly obtain the correct frequency band control code during operation after passing a test and correction.

Description

Translated fromChinese

一种带有自动频率校正的锁相环频率综合器结构A PLL Frequency Synthesizer Structure with Automatic Frequency Correction

技术领域technical field

本发明涉及一种改进的带自动频率校正电路的锁相环频率综合器结构，尤其涉及一种能够使电路对工艺偏差更不敏感及使自动频率校正电路更快速地确定压控振荡器的控制编码的电路。The invention relates to an improved structure of a phase-locked loop frequency synthesizer with an automatic frequency correction circuit, in particular to a control that can make the circuit less sensitive to process deviations and enable the automatic frequency correction circuit to determine the voltage-controlled oscillator more quickly encoded circuit.

背景技术Background technique

随着CMOS工艺特征尺寸不断减小，CMOS电路对工艺偏差的敏感性越来越强，这使得实际生产出的电路性能发布不均匀，从而导致设计压力增大、功耗提高、良率降低。具体到锁相环频率综合器电路中，由于工艺偏差的存在，使得实际制造的电容与设计值存在差距，这会导致锁相环对应的频带实际范围与设计不一致。另外，为了获得较好的相位噪声性能，压控振荡器的Kvco值必须足够小，又由于压控振荡器的输出频率必须覆盖足够大的范围，所以通常采用通过数字位（即控制编码）选通不同大小的电容来实现不同输出频带的切换。由于工艺偏差使得频带实际范围变化，因此需要自动频率校正电路对实际制造出的电路进行校正，在运行时选择合适控制编码才能输出预想的频率的信号。As the feature size of the CMOS process continues to decrease, CMOS circuits are more and more sensitive to process deviations, which makes the performance of the actual produced circuits uneven, resulting in increased design pressure, increased power consumption, and reduced yield. Specifically, in the phase-locked loop frequency synthesizer circuit, due to the existence of process deviation, there is a gap between the actual manufactured capacitance and the design value, which will cause the actual range of the frequency band corresponding to the phase-locked loop to be inconsistent with the design. In addition, in order to obtain better phase noise performance, the Kvco value of the voltage-controlled oscillator must be small enough, and since the output frequency of the voltage-controlled oscillator must cover a large enough range, it is usually selected by digital bits (ie control code) Capacitors of different sizes are used to switch between different output frequency bands. Due to process deviations, the actual range of the frequency band changes, so an automatic frequency correction circuit is required to correct the actual manufactured circuit, and an appropriate control code is selected during operation to output a signal of the expected frequency.

发明内容Contents of the invention

为了实现在存在一定工艺偏差的条件下快速找到合适的压控振荡器控制编码。In order to quickly find the appropriate voltage-controlled oscillator control code under the condition of certain process deviation.

本发明所采用的技术方案是：一种带有自动频率校正的锁相环频率综合器结构，其特征在于，整个电路由鉴频鉴相器、电荷泵、低通滤波器、压控振荡器、分频器、频率计数器、查找表电路、多路选择器、控制电路构成；其中鉴频鉴相器的两路输入信号为参考频率信号和压控振荡器输出经过分频器分频之后的信号，输出信号作为电荷泵的输入信号；电荷泵的输入信号为鉴频鉴相器的输出信号，输出信号作为低通滤波器的输入信号；低通滤波器的输入信号为电荷泵输出信号，输出信号经过可控开关作为压控振荡器的输出信号；压控振荡器有三个输入信号，分别为低通滤波器的输出信号、多路选择器输出的控制编码、通过可控开关选通的电源/地电位，压控振荡器的输出信号同时是整个电路的输出信号、分频器输入信号、计数器输入信号，压控振荡器输出经过可控开关之后作为计数器输入信号；分频器的输入信号包括压控振荡器的输出信号和外加的分频比编码，输出信号作为鉴频鉴相器的一路输入；计数器的输入信号由压控振荡器经过可控开关加入，输出信号作为查找表输入；查找表电路的两个输入信号分别为计数器输出和分频器分频比编码，输出信号作为多路选择器的一路输出信号；多路选择器的一路输入为查找表输出，另一路为控制电路输出的测试用控制编码，选择信号来自控制电路，输出作为压控振荡器的控制编码；控制电路输出包括测试用压控振荡器控制编码、多路选择器选择信号、整个电路中的所有可控开关。The technical solution adopted in the present invention is: a phase-locked loop frequency synthesizer structure with automatic frequency correction, characterized in that the whole circuit consists of a frequency detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator , a frequency divider, a frequency counter, a look-up table circuit, a multiplexer, and a control circuit; the two input signals of the frequency and phase detector are the reference frequency signal and the output of the voltage-controlled oscillator after frequency division by the frequency divider signal, the output signal is used as the input signal of the charge pump; the input signal of the charge pump is the output signal of the frequency and phase detector, and the output signal is used as the input signal of the low-pass filter; the input signal of the low-pass filter is the output signal of the charge pump, The output signal passes through the controllable switch as the output signal of the voltage-controlled oscillator; the voltage-controlled oscillator has three input signals, which are the output signal of the low-pass filter, the control code output by the multiplexer, and the signal gated by the controllable switch. Power supply/ground potential, the output signal of the voltage-controlled oscillator is the output signal of the entire circuit, the input signal of the frequency divider, and the input signal of the counter, and the output of the voltage-controlled oscillator is used as the input signal of the counter after passing through the controllable switch; The signal includes the output signal of the voltage-controlled oscillator and the external frequency division ratio code. The output signal is used as an input of the frequency and phase detector; the input signal of the counter is added by the voltage-controlled oscillator through a controllable switch, and the output signal is used as a look-up table input. ; The two input signals of the look-up table circuit are the counter output and the frequency division ratio code of the frequency divider respectively, and the output signal is used as one output signal of the multiplexer; one input of the multiplexer is the output of the look-up table, and the other is the control The test control code output by the circuit, the selection signal comes from the control circuit, and the output is used as the control code of the voltage-controlled oscillator; the output of the control circuit includes the control code of the voltage-controlled oscillator for test, the selection signal of the multiplexer, and all possible control switch.

本发明的有益效果是，本发明提出了一种新的带有自动频率校正的锁相环频率综合器结构，能够以比现有的锁相环电路更短的时间完成对合适的压控振荡器控制编码的搜索，实现更加快速的频率切换。The beneficial effect of the present invention is that the present invention proposes a new PLL frequency synthesizer structure with automatic frequency correction, which can complete the proper voltage-controlled oscillation in a shorter time than the existing PLL circuit The controller controls the search of the code to achieve faster frequency switching.

附图说明Description of drawings

图1是本发明新型自动频率校正锁相环频率综合器结构系统框图。Fig. 1 is a structural system block diagram of the novel automatic frequency correction phase-locked loop frequency synthesizer of the present invention.

具体实施方式Detailed ways

本发明的原理是：通过实用测试用控制编码对流片后的锁相环频率综合器电路进行测试，获得各个控制编码对应频带的实际频率范围，据此建立分频比编码到压控振荡器控制编码的查找表，从而实现快速控制编码的快速确定，进而实现比现有锁相环频率综合器电路更快速的频率切换。The principle of the present invention is to test the phase-locked loop frequency synthesizer circuit after tape-out by using the control codes for practical testing, obtain the actual frequency ranges of the frequency bands corresponding to each control code, and establish frequency division ratio codes to control the voltage-controlled oscillator accordingly. Coded look-up table, so as to realize fast determination of fast control codes, and then realize faster frequency switching than existing phase-locked loop frequency synthesizer circuits.

下面结合附图对本发明的方法进一步说明。The method of the present invention will be further described below in conjunction with the accompanying drawings.

图1所示为新型自动频率校正锁相环频率综合器结构系统框图，整个电路由鉴频鉴相器、电荷泵、低通滤波器、压控振荡器、分频器、频率计数器、查找表电路、多路选择器、控制电路构成；其中鉴频鉴相器的两路输入信号为参考频率信号和压控振荡器输出经过分频器分频之后的信号，输出信号作为电荷泵的输入信号；电荷泵的输入信号为鉴频鉴相器的输出信号，输出信号作为低通滤波器的输入信号；低通滤波器的输入信号为电荷泵输出信号，输出信号经过可控开关作为压控振荡器的输出信号；压控振荡器有三个输入信号，分别为低通滤波器的输出信号、多路选择器输出的控制编码、通过可控开关选通的电源/地电位，压控振荡器的输出信号同时是整个电路的输出信号、分频器输入信号、计数器输入信号，压控振荡器输出经过可控开关之后作为计数器输入信号；分频器的输入信号包括压控振荡器的输出信号和外加的分频比编码，输出信号作为鉴频鉴相器的一路输入；计数器的输入信号由压控振荡器经过可控开关加入，输出信号作为查找表输入；查找表电路的两个输入信号分别为计数器输出和分频器分频比编码，输出信号作为多路选择器的一路输出信号；多路选择器的一路输出为查找表输出，另一路为控制电路输出的测试用控制编码，输出作为压控振荡器的控制编码；控制电路输出包括测试用压控振荡器控制编码和整个电路中的所有可控开关。Figure 1 shows the block diagram of the new automatic frequency correction phase-locked loop frequency synthesizer structure system, the whole circuit consists of frequency detector phase detector, charge pump, low-pass filter, voltage-controlled oscillator, frequency divider, frequency counter, look-up table circuit, multiplexer, and control circuit; the two input signals of the frequency and phase detector are the reference frequency signal and the voltage-controlled oscillator output signal after frequency division by the frequency divider, and the output signal is used as the input signal of the charge pump ; The input signal of the charge pump is the output signal of the frequency and phase detector, and the output signal is used as the input signal of the low-pass filter; the input signal of the low-pass filter is the output signal of the charge pump, and the output signal is used as a voltage-controlled oscillation through a controllable switch The output signal of the device; the voltage-controlled oscillator has three input signals, which are the output signal of the low-pass filter, the control code output by the multiplexer, the power/ground potential gated by the controllable switch, and the voltage-controlled oscillator. The output signal is the output signal of the entire circuit, the input signal of the frequency divider, and the input signal of the counter. The output signal of the voltage-controlled oscillator is used as the input signal of the counter after passing through the controllable switch; The frequency-division ratio code is added, and the output signal is used as an input of the frequency and phase detector; the input signal of the counter is added by the voltage-controlled oscillator through a controllable switch, and the output signal is used as the input of the look-up table; the two input signals of the look-up table circuit are respectively It is coded for the counter output and frequency division ratio of the frequency divider, and the output signal is used as an output signal of the multiplexer; one output of the multiplexer is the output of the lookup table, and the other is the control code for the test output of the control circuit, and the output is used as The control code of the voltage-controlled oscillator; the output of the control circuit includes the control code of the voltage-controlled oscillator for testing and all controllable switches in the entire circuit.

本发明中使用的各个模块，除了控制电路之外，均可使用现有的实现方式。本发明中使用的控制电路的实现，需要根据实际实现时的具体技术指标要求和其他模块的参数才能确定，控制电路的实现可以根据工作原理的描述，通过verilog HDL或VHDL等硬件描述语言进行描述并综合出电路图，这对于从事集成电路设计的技术人员是不难做到的。Each module used in the present invention, except the control circuit, can use the existing implementation. The realization of the control circuit used in the present invention needs to be determined according to the specific technical index requirements and the parameters of other modules during actual realization, and the realization of the control circuit can be described by hardware description languages such as verilog HDL or VHDL according to the description of the working principle And synthesize the circuit diagram, which is not difficult for technicians engaged in integrated circuit design.

本发明中提出的锁相环频率综合器工作过程为：开始运行前，首先要对压控振荡器各频带实际频率范围进行测试：低通滤波器与压控振荡器之间的可控开关断开，多路选择器选通控制电路产生的测试用控制编码，压控振荡器与计数器之间的可控开关闭合，控制电路控制计数器在某一固定时间内对压控振荡器产生的正弦波进行计数，与此同时，控制开关逐个输出不同的控制编码，并先后通过可控开关来给压控振荡器控制电压加上电源电位或地电位，由此通过计数器对每个频带的最高和最低频率进行测量。根据测量到的实际频带频率范围、参考信号频率、分频比范围，通过简单的组合逻辑电路设计可以得出不同分频比编码对应的压控振荡器控制编码，据此建立查找表，至此测试过程结束，电路开始运行。多路选择器选通查找表输出的控制编码，压控振荡器与计数器之间的可控开关断开，控制电路输出到压控振荡器控制电压端的电源/地电位的可控开关断开，低通滤波器与压控振荡器之间的可控开关闭合，电路正常运行。现有的锁相环频率综合器在分频比改变后要重新搜索合适的控制编码，这会花费很长时间，难以实现快速锁定。本发明给出的新的锁相环电路结构可以完成测试后，在分频比改变时在极短的时间（仅为查找表传播延时）内确定合适的压控振荡器控制编码，实现快速的频率切换。The working process of the phase-locked loop frequency synthesizer proposed in the present invention is as follows: before starting to run, the actual frequency range of each frequency band of the voltage-controlled oscillator is first tested: the controllable switch between the low-pass filter and the voltage-controlled oscillator is turned off Open, the control code generated by the multiplexer gating control circuit for testing, the controllable switch between the voltage-controlled oscillator and the counter is closed, the control circuit controls the counter to generate sine waves generated by the voltage-controlled oscillator within a certain fixed time At the same time, the control switch outputs different control codes one by one, and successively through the controllable switch to add the power supply potential or ground potential to the control voltage of the voltage controlled oscillator, so that the highest and lowest of each frequency band can be calculated by the counter frequency to measure. According to the measured actual frequency band frequency range, reference signal frequency, and frequency division ratio range, the voltage-controlled oscillator control codes corresponding to different frequency division ratio codes can be obtained through simple combinational logic circuit design, and a look-up table is established based on this, so far the test The process is over and the circuit starts running. The multiplexer strobes the control code output by the look-up table, the controllable switch between the voltage-controlled oscillator and the counter is disconnected, the control circuit outputs the controllable switch of the power supply/ground potential to the voltage-controlled oscillator control voltage terminal, and The controllable switch between the low-pass filter and the voltage-controlled oscillator is closed, and the circuit operates normally. The existing phase-locked loop frequency synthesizer has to re-search for a suitable control code after the frequency division ratio is changed, which will take a long time and it is difficult to achieve fast locking. The new phase-locked loop circuit structure provided by the present invention can determine the appropriate voltage-controlled oscillator control code in a very short time (only the look-up table propagation delay) when the frequency division ratio is changed after the test is completed, realizing fast frequency switching.

Claims (1)

1. phase-locked loop frequency integrator structure that has automatic frequency correction, it is characterized in that entire circuit is made of phase frequency detector, charge pump, low pass filter, voltage controlled oscillator, frequency divider, frequency counter, lut circuits, MUX, control circuit; Wherein the two-way input signal of phase frequency detector is reference frequency signal and voltage controlled oscillator output process frequency divider frequency division signal afterwards, and output signal is as the input signal of charge pump; The input signal of charge pump is the output signal of phase frequency detector, and output signal is as the input signal of low pass filter; The input signal of low pass filter is charge pump output signal, and output signal is through the output signal of gate-controlled switch as voltage controlled oscillator; Voltage controlled oscillator has three input signals, be respectively the control coding of output signal, the MUX output of low pass filter, the power supply/earth potential by the gate-controlled switch gating, the output signal of voltage controlled oscillator is output signal, frequency divider input signal, the counter input signal of entire circuit simultaneously, and voltage controlled oscillator output process gate-controlled switch is afterwards as the counter input signal; The frequency dividing ratio coding that the input signal of frequency divider comprises the output signal of voltage controlled oscillator and adds, output signal is as one tunnel input of phase frequency detector; The input signal of counter is added through gate-controlled switch by voltage controlled oscillator, and output signal is imported as look-up table; Two input signals of lut circuits are respectively counter output and frequency divider frequency dividing ratio coding, and output signal is as one tunnel output signal of MUX; A road of MUX is input as look-up table output, and another road is that the test of control circuit output is encoded with control, selects signal from control circuit, and output is as the control coding of voltage controlled oscillator; Control circuit output comprises that test selects all gate-controlled switches in signal, the entire circuit with voltage controlled oscillator control coding, MUX.