CN103346119A - Method for decreasing critical size of copper-connection groove - Google Patents

Abstract

The invention relates to the field of integrated circuit manufacturing, in particular to a method for decreasing the critical size of a copper-connection groove. In the manufacturing process of a mask of the copper-connection groove, after a traditional process is used for etching to a dielectric layer to form a first groove, a polymer layer is deposited on the surface of a device by the adoption of a plasma deposition process, the first groove is filled with the polymer layer, then plasma etching is conducted, the polymer layer is partially removed, the polymer layer with a certain thickness is reserved on the inner wall of the first groove, so that a second groove which is smaller in size compared with the critical size of an original pattern is formed, afterwards, the second groove is used for etching until a metal through hole area inside a substrate is exposed out of the substrate, and finally the polymer layer left in the groove is removed through the way of wet process cleaning so that the subsequent processes can be continued. According to the technical scheme, in the preparation technology of the copper-connection groove, the critical size of the groove can be decreased, the device performance can be enhanced, meanwhile production cost is low, and therefore the method for decreasing the critical size of the copper-connection groove is suitable for application and popularization.

Description

A kind of method that reduces copper-connection groove critical size

Technical field

The present invention relates to integrated circuit and make the field, be specifically related to a kind of method of dwindling copper-connection groove critical size.

Background technology

Continuous development along with technology, the critical size of semiconductor device is also more and more littler, the more for a short time raising that means device performance of the critical size of device, those skilled in the art endeavour research always and adopt which kind of technology reducing the device critical size, and then the boost device performance.

Fig. 1-3 is the flow chart of the copper-connection groove critical size manufacture craft of microelectronic in the prior art, generally comprise photoetching, metal hard mask etching and three step: step a of metal valley etching: provide semiconductor structure, this semiconductor structure comprises asubstrate 1,substrate 1 is formed with dielectric layer and metal hardmask 5(TiN_MHM from bottom to top successively) and oxide layer 6(OX), wherein, dielectric layer comprises the first dielectric layer 2(SiCN from bottom to top successively), the second dielectric layer 3(SiCOH), the 3rd dielectric layer 4(TEOS); In addition,substrate 1 has a metalthrouth hole district 9, in copper-connection groove critical size manufacture craft, need to make a groove exposing thismetal throuth hole 9 fully, and then is satisfying follow-up through hole connecting line technics.At first apply one deckanti-reflecting layers 7 earlier onoxide layer 6 surface, be covered in the upper surface ofanti-reflecting layer 7 applying one deck photoresistance then, carry out exposure imaging technology after, in photoresistance, form the window of etching, form structure shown in Figure 1; Step b: be that mask is etched to dielectric layer withresidue photoresistance 8 then, after the formation pattern of windows, removeresidue photoresistance 8 andanti-reflecting layer 7, form structure as shown in Figure 2; Step c: the pattern that utilizes dielectric layer to form carries out metal valley and is etched to substrate, exposes the metalthrouth hole district 9 ofsubstrate 1, forms structure shown in Figure 3.

Because the analytic ability of conventional lithography machine is relatively poor, after exposure imaging technology, the pattern of windows size of leaving is bigger; In follow-up trench etch process, be to carry out etching with the pattern of windows of photoetching, and then caused the channel patterns size that etches also bigger, and groove dimensions is more big, the performance of device is also decreased.Therefore guaranteeing that the metal throuth hole that etching groove can exposesubstrate 1 in fully goes in 9, reducing groove dimensions as far as possible and be those skilled in the art and constantly endeavour the direction studied.

In the prior art, in order to reduce the critical size of groove, can adopt mask aligner of new generation to realize this scheme, Fig. 4-6 is for to utilize mask aligner of new generation to prepare the flow chart of the interconnected groove of copper, as shown in the figure, because preparation technology is same as the prior art, so do not repeat them here.Because the mask aligner analytic ability of a new generation is stronger, can in photoresistance, form the littler pattern of windows of size through behind the exposure imaging, and then in subsequent technique, can produce the groove of littler critical size, in the through hole in exposingsubstrate 1, reduced the size of the key of groove, thus the boost device performance.But the mask aligner cost of a new generation is very expensive, though utilize mask aligner of new generation can reduce the critical size of groove, because the mask aligner of a new generation involves great expense, if adopt greatly increase production cost of photoetching machine of new generation.Therefore, under the prerequisite of control production cost, the critical size that how to reduce device trenches becomes the direction of those skilled in the art's research.

Chinese patent (application number: 201210432507.5) disclose a kind of manufacture craft of copper interconnection line, wherein, may further comprise the steps: step S1: after the upper surface of a silicon substrate deposited a low dielectric coefficient medium layer, first photoresist that coating can form hard mask covered described low dielectric coefficient medium layer; Step S2: after exposure, the development, remove the first unnecessary photoresist, form the first hard mask photoresistance with metallic channel structure; Step S3: the coating curing materials covers the surface of the described first hard mask photoresistance, solidify to form barrier film; Step S4: second photoresist that coating can form hard mask is full of described metallic channel structure and covers the upper surface of described hard mask photoresistance; Step S5: after exposure, the development, remove the second unnecessary photoresist, form the second hard mask photoresistance with through-hole structure; Step S6: adopt etching technics, after successively the metallic channel structure in the through-hole structure in the described second hard mask photoresistance and the described first hard mask photoresistance being transferred to described low dielectric coefficient medium layer, continue metal deposition process and grinding technics, to form lead metal and via metal; Wherein, after the coating curing materials solidify to form described barrier film among the step S3, adopt acid solution to handle unnecessary curing materials earlier, remove this unnecessary curing materials again, form the described barrier film that covers the described first hard mask photoresistance surface.

This invention is to form barrier film by crossing to adopt between the two-layer photoresistance of polyamine compounds material in double-exposure technique in the interconnected technology of the preferential copper of groove, and successively the through hole in the photoresistance and metallic channel structure are transferred to dielectric layer, thereby substituted tradition metallic channel etching and via etch are divided into the existing technology of two independent processes, thereby reduce etch step.But this invention is by adopting photoetching process to form behind the window etching groove again, because the analytic ability of conventional lithography machine is relatively poor, pattern of windows behind the exposure imaging is bigger, this is disadvantageous to the boost device performance, if and adopt mask aligner cost of new generation very high, influenced the development of the interconnected technology of copper.

Summary of the invention

The present invention provides a kind of method that reduces the groove critical size according to the deficiencies in the prior art, after the conventional lithography machine forms pattern and etching, again at semiconductor device surface deposition one layer of polymeric layer, eat-back this polymeric layer then, form certain thickness polymeric layer and in window, form a less pattern of windows at the window sidewall, carry out etching groove then, remove the interior residual polymer of window after etching is finished and carry out follow-up technology.Owing to be formed with polymeric layer at the window sidewall, after carrying out etching groove, can form the less groove of a size, reduce the critical size of device trenches, and then be conducive to the lifting of device performance.

The technical solution used in the present invention is:

A kind of method that reduces the device trenches critical size is applied to wherein, may further comprise the steps among the interconnected groove preparation technology of copper:

One semiconductor structure with metal hard mask and dielectric layer is provided, and described metal hard mask covers the surface of described dielectric layer;

Part is removed described metal hard mask and is formed first groove;

Deposited polymer layer covers the surface of residual metallic hard mask and fills described first groove;

Eat-back described polymeric layer, in described first trenched side-wall, form sidewall structure;

Be the described dielectric layer of mask etching with residual metallic hard mask and described sidewall structure, in described dielectric layer, form second groove;

Wherein, the bottom of described first groove in described sidewall structure cover part.

Above-mentioned method wherein, may further comprise the steps:

S1, after preparing an anti-reflecting layer, described metal hard mask surface applies one deck photoresistance again, use mask aligner to carry out exposure imaging technology, form a pattern of windows at photoresistance, and guarantee that this pattern of windows and described through hole overlap and form overlapping, and this pattern of windows width is greater than the size of through hole;

S2, utilize described pattern of windows to be etched to described dielectric layer, form first groove, and remove the remaining photoresistance in top and anti-reflecting layer;

S3, deposition one polymeric layer cover described metal hard mask upper surface and fill first groove, eat-back described polymeric layer then, remove the polymeric layer of described metal hard mask upper surface, and keep the first trenched side-wall partial polymer layer, form second groove, and the bottom width of this second groove is less than the bottom width of first groove;

S4, utilize described second groove to carry out etching, stop after the via top to the substrate;

Remaining polymeric layer in S5, the removal window, and carry out follow-up technology.

Method according toclaim 2, wherein, the using plasma deposition forms described polymeric layer.

Method according toclaim 2, wherein, 30～80 ℃ of temperature, pressure is 20～300mtorr, and radio-frequency power is under the condition of 1000～2500w, and feeding flow is the CO gas of 200～1000sccm, and flow is the N of 200～2000sccm₂Gas aggradation forms described polymeric layer.

Above-mentioned method wherein, adopts plasma etching industrial to eat-back described polymeric layer.

Above-mentioned method wherein, is controlled the thickness of the residual polymer layer of described first trench wall according to the reaction condition of process requirements adjustment plasma etching.

Above-mentioned method wherein, adopts wet-cleaned to remove the residual polymer of window inwall.

Above-mentioned method wherein, adopts ST250 solution to remove the remaining polymeric layer of first trenched side-wall.

Owing to adopted above technical scheme, eat-back after after device forms first groove, depositing a polymeric layer again, and the polymer that keeps the window sidewall forms and carries out etching again behind second groove and can form the narrower groove of a width, and then reduced the critical size of device trenches, be conducive to the lifting of device performance.

Description of drawings

By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.

Fig. 1-3 utilizes conventional lithography mechanism for prior art and is equipped with the flow chart of the interconnected groove of copper;

Fig. 4-6 utilizes mask aligner of new generation to prepare the flow chart of the interconnected groove of copper in the prior art;

Fig. 7-12 is a kind of flow chart that dwindles the preparation method of copper-connection etching groove critical size provided by the invention.

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described:

Just the invention provides an embodiment below and further set forth, Fig. 7-12 is a kind of flow chart that dwindles the preparation method of copper-connection etching groove critical size provided by the invention, specifically may further comprise the steps:

Step S1, provide semiconductor structure, this semiconductor structure comprises asubstrate 1,substrate 1 is formed with dielectric layer and metal hardmask 5(TiN_MHM from bottom to top successively) and oxide layer 6(OX), wherein, dielectric layer comprises the first dielectric layer 2(SiCN from bottom to top successively), the second dielectric layer 3(SiCOH), the 3rd dielectric layer 4(TEOS); One metalthrouth hole district 9 is arranged in thesubstrate 1, and these 9 parts, metal throuth hole district are filled with tungsten.In the interconnected trench etch process of copper, need leave a plurality of grooves in the device corresponding position, and guarantee that one of them groove must expose the via hole image of substrate fully, to satisfy the requirement of the follow-up interconnected technology of copper; Simultaneously for the boost device performance, the groove critical size is also the smaller the better, namely it would be desirable when guaranteeing that channel patterns exposes throughhole area 9 in thesubstrate 1 fully, reduces the critical size of groove simultaneously as far as possible, and then the boost device performance.Behind surface preparation oneanti-reflecting layer 7 ofoxide layer 3, surface-coated one deck photoresistance behindanti-reflecting layer 7 again, adopt the conventional lithography machine in photoresistance, to form pattern of windows through behind the exposure imaging, type guarantees that this pattern of windows and described through hole overlap and form overlapping, and this pattern of windows width is greater than the size of through hole.After finishing, this step forms structure as shown in Figure 7.

Step S2, to utilizeresidue photoresistance 8 be mask, stops after being etched down to the 3rddielectric layer 4 certain depth places, formsfirst groove 10, removes the anti-reflecting layer at top and remain photoresistance.Form structure shown in Figure 8.As shown in Figure 8, because traditional mask aligner analytic ability is relatively poor, be subjected to the process conditions restriction, bigger at the channel patterns that photoresistance forms through photoetching process, and then it is also bigger to form corresponding trench openings pattern in etched features; Form groove if directly carry out etching with this pattern, the critical size of the final device trenches that forms is also bigger, and then reduced device performance, and technical purpose to be solved by this invention be guarantee production cost with production technology the time, reduce the size that etching forms groove as far as possible, and then the boost device performance.

Step S3, using plasma deposit apolymeric layer 11 be covered in residue oxide layer 6 ' the surface and fill first groove 10.In an embodiment of the present invention, 30～80 ℃ of temperature (as 30 ℃, 40 ℃, 50 ℃, 60 ℃, 70 ℃, 80 ℃ of equivalences), pressure is 20～300mtorr(such as 20mtorr, 50mtorr, 100mtorr, 200mtorr, 300mtorr equivalence), radio-frequency power is 1000～2500w(such as 1000w, 1500w, 2000w, the 2500w equivalence) under the condition, feeding flow is the CO gas of 200～1000sccm, and flow is the N of 200～2000sccm₂Gas aggradation forms polymeric layer 11.After finishing, this step forms structure as shown in Figure 9.

Step S4, adopt plasma etching industrial thatpolymeric layer 11 is eat-back, remove residue oxide layer 6 ' thepolymer 11 on surface, and theresidual polymer 11 of first groove, 10 sidewall reserve parts '.Since first groove, 10 sidewalls kept certain thickness residual polymer 11 ', and then first groove 10 in formation one critical size less thansecond groove 20, the structure as shown in figure 10 of first groove 10.Simultaneously, size according to metal throuth hole district in thesubstrate 1, reaction condition by adjusting plasma etching and then control residual polymer 11 ' thickness, make the size ofsecond groove 20 equate with the size in metalthrouth hole district 9, and then continuing to guarantee when downward etching forms groove that groove is in complete exposing metal through hole area, size is also enough little, and then the boost device performance.

Step S5, utilizesecond groove 20 to be etched tosubstrate 1 to stop, exposing the metalthrouth hole district 9 in thesubstrate 1, form the interconnected groove of copper, as shown in figure 11 structure.Because having controlled the plasma condition of eat-backing in step S4 makessecond groove 20 equate with the size in metalthrouth hole district 9 as far as possible, can obtain the measure-alike interconnected groove of copper of one andsecond groove 20 utilizingsecond groove 20 to carry out etching, when exposing metalthrouth hole district 9, reduced the critical size of the interconnected groove of copper as much as possible, the lifting that reduces then to mean device performance of the critical size that copper is interconnected; Simultaneously, the present invention need not to adopt the mask aligner of a new generation, adopts technique scheme also can obtain reducing the purpose of the critical size of the interconnected groove of copper equally, has saved production cost greatly, and use is promoted the use of.

Step S6, wet-cleaned removeresidual polymer 11 infirst groove 10 '.In an embodiment of the present invention, can adopt the ST250 cleaning fluid to clean the removal residual polymer, wherein, this ST250 solution is by organic substance, NH₄F and additive are formulated according to a certain percentage, use this cleaning fluid can obtain best cleaning performance.Because polymer is that the relative molecular weight that mainly formed with covalent bonds by numerous atoms or atomic group is at the compound more than 10,000, when wet-cleaned, can be easy to be cleaned thoroughly removal of back by sulfuric acid or hydrogen peroxide, if and adopt other materials to form side wall at the inwall of first groove, in wet-cleaned and be not easy to be removed, influenced production technology.

In sum, because the present invention has adopted above technical scheme, the window that traditional handicraft utilizes photoetching to form be etched to form first groove in the semiconductor device after, prepare surface and window that a polymeric layer covers semiconductor device, eat-back polymeric layer then, the polymeric layer that keeps the window madial wall forms one and forms the second less groove of first groove than original etching, utilizes this second groove to carry out etching then and forms groove; Because the size of second groove is utilized second groove to carry out can forming the less pattern of a size after the etching, and then has been reduced the critical size of device trenches less than the size of first groove, is conducive to the performance of boost device; The present invention simultaneously need not to adopt mask aligner of new generation, also can prepare the channel patterns of a reduced size, has controlled production cost when having improved production technology.

More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, wherein the equipment of not describing in detail to the greatest extent and structure are construed as with the common mode in this area and are implemented; Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.

Claims (8)

1. a method that reduces the device trenches critical size is applied to it is characterized in that among the interconnected groove preparation technology of copper, may further comprise the steps:

One semiconductor structure with metal hard mask and dielectric layer is provided, and described metal hard mask covers the surface of described dielectric layer;

Be etched to dielectric layer and form first groove;

Deposited polymer layer covers the surface of residual metallic hard mask and fills described first groove;

Eat-back described polymeric layer, in described first trenched side-wall, form sidewall structure;

Be the described dielectric layer of mask etching with residual metallic hard mask and described sidewall structure, in described dielectric layer, form second groove structure;

Wherein, the bottom of described first groove in described sidewall structure cover part.

2. method according to claim 1 is characterized in that, may further comprise the steps:

S1, after preparing an anti-reflecting layer, described metal hard mask surface applies one deck photoresistance again, the use mask aligner exposes, developing process, in described photoresistance, form a pattern of windows, and guarantee that this pattern of windows and described through hole overlap and form overlapping, and this pattern of windows width is greater than the size of through hole;

S2, utilize described pattern of windows to be etched to described dielectric layer, form first groove, and remove the remaining photoresistance in top and anti-reflecting layer;

S3, deposition one polymeric layer cover described metal hard mask upper surface and fill first groove, eat-back described polymeric layer then, remove the polymeric layer of described metal hard mask upper surface, and keep the first trenched side-wall partial polymer layer, form second groove;

S4, utilize described second groove to carry out etching, stop after the via top to the substrate;

Remaining polymeric layer in S5, the removal window, and carry out follow-up technology.

3. method according to claim 2 is characterized in that, the using plasma depositing operation forms described polymeric layer.

4. method according to claim 2 is characterized in that, 30～80 ℃ of temperature, pressure is 20～300mtorr, and radio-frequency power is under the condition of 1000～2500w, and feeding flow is the CO gas of 200～1000sccm, and flow is the N of 200～2000sccm₂Gas aggradation forms described polymeric layer.

5. method according to claim 2 is characterized in that, adopts plasma etching industrial to eat-back described polymeric layer.

6. method according to claim 5 is characterized in that, controls the thickness of the residual polymer layer of described first trench wall according to the reaction condition of process requirements adjustment plasma etching.

7. method according to claim 2 is characterized in that, adopts wet-cleaned to remove the residual polymer of window inwall.

8. method according to claim 7 is characterized in that, adopts ST250 solution to remove the remaining polymeric layer of first trenched side-wall.

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