技术领域technical field
本发明涉及半导体技术领域，特别涉及一种半导体发光二极管的外延片及其制造方法。The invention relates to the technical field of semiconductors, in particular to an epitaxial wafer of a semiconductor light emitting diode and a manufacturing method thereof.
背景技术Background technique
以氮化镓(GaN)、氮化铟(InN)、氮化铝(AlN)为代表的III族氮化物和它们的合金铟镓氮(InGaN)，因其良好的物理和化学性质，被广泛的应用于发光二极管。Group III nitrides represented by gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN) and their alloy indium gallium nitride (InGaN) are widely used because of their good physical and chemical properties. applied to light-emitting diodes.
发光二极管外延片包括衬底和依次层叠在衬底上的低温缓冲层、高温缓冲层、复合N型层、复合多量子阱层和复合P型层。其中复合多量子阱层包括第一多量子阱层和层叠在第一多量子阱层上的第二多量子阱层，该第一多量子阱层和该第二多量子阱层均由交替层叠的势阱层(InGaN层)和势垒层(GaN层)组成，其中，第一多量子阱层起释放应力的作用，使得第二多量子阱层的晶体质量更好，发光效率高。在制作第一多量子阱层时，由于势阱层需要低温生长，而势垒层需要高温生长，因此从低温转变到高温的过程之中，会造成势阱层分解。有人提出低温下生长氮化镓(GaN)盖层保护势阱层，进而提高势垒层的生长温度。The light-emitting diode epitaxial wafer includes a substrate and a low-temperature buffer layer, a high-temperature buffer layer, a composite N-type layer, a composite multiple quantum well layer and a composite P-type layer stacked on the substrate in sequence. Wherein the composite multi-quantum well layer comprises a first multi-quantum well layer and a second multi-quantum well layer stacked on the first multi-quantum well layer, and the first multi-quantum well layer and the second multi-quantum well layer are alternately stacked The potential well layer (InGaN layer) and the barrier layer (GaN layer) are composed of the potential well layer (InGaN layer) and the barrier layer (GaN layer), wherein the first multi-quantum well layer plays the role of releasing stress, so that the crystal quality of the second multi-quantum well layer is better and the luminous efficiency is high. When manufacturing the first multi-quantum well layer, since the potential well layer needs to be grown at low temperature and the barrier layer needs to be grown at high temperature, the potential well layer will be decomposed during the transition from low temperature to high temperature. It was proposed to grow a gallium nitride (GaN) capping layer at a low temperature to protect the potential well layer, thereby increasing the growth temperature of the barrier layer.
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:
在制作第一多量子阱层时，通过生长GaN盖层的方法提高的势垒层的生长温度，仍低于正常生长势垒层所需的温度，使得势垒层在低温下生长时，表面形成螺旋岛状结构，致使第一多量子阱层的势垒层的表面特性差，进而导致第二多量子阱层的晶体质量差、发光效率低。When making the first multi-quantum well layer, the growth temperature of the barrier layer increased by growing the GaN cap layer is still lower than the temperature required for normal growth of the barrier layer, so that when the barrier layer is grown at a low temperature, the surface A spiral island structure is formed, resulting in poor surface properties of the barrier layer of the first multi-quantum well layer, which further leads to poor crystal quality and low luminous efficiency of the second multi-quantum well layer.
发明内容Contents of the invention
本发明的目的是提供一种半导体发光二极管的外延片及其制造方法，能避免第一多量子阱层的势垒层的表面形成螺旋岛状结构，提高第一多量子阱层的势垒层的表面特性，保证第二多量子阱层的晶体质量和发光效率。The purpose of the present invention is to provide an epitaxial wafer of a semiconductor light-emitting diode and a manufacturing method thereof, which can avoid forming a spiral island structure on the surface of the barrier layer of the first multi-quantum well layer and improve the barrier layer of the first multi-quantum well layer The surface characteristics ensure the crystal quality and luminous efficiency of the second multi-quantum well layer.
为了实现上述目的，一方面，本发明实施例提供了一种半导体发光二极管的外延片，包括衬底和依次在所述衬底上生长的低温缓冲层、高温缓冲层、复合N型层、复合多量子阱层和复合P型层，所述复合多量子阱层包括第一多量子阱层和在所述第一多量子阱层上生长的第二多量子阱层，所述第一多量子阱层为多周期结构，每一周期包括势阱层和在所述势阱层上生长的势垒层，周期数为4，每一周期的所述势阱层的生长温度为780℃，每一周期的所述势阱层的生长压力为200Torr，每一周期的所述势阱层的Ⅴ/Ⅲ摩尔比为4500，每一周期的所述势阱层的厚度为2.5nm；所述第一多量子阱层每一周期的势垒层分别掺杂有Si，Si的有效掺杂浓度为2×1017/cm3，每一周期的所述势垒层的生长温度为900℃，每一周期的所述势垒层的生长压力为200Torr，每一周期的所述势垒层的Ⅴ/Ⅲ摩尔比为4500，每一周期的所述势垒层的厚度为12nm。In order to achieve the above object, on the one hand, an embodiment of the present invention provides an epitaxial wafer of a semiconductor light-emitting diode, including a substrate and a low-temperature buffer layer, a high-temperature buffer layer, a composite N-type layer, a composite A multi-quantum well layer and a composite P-type layer, the composite multi-quantum well layer includes a first multi-quantum well layer and a second multi-quantum well layer grown on the first multi-quantum well layer, the first multi-quantum well layer The well layer is a multi-period structure, and each period includes a potential well layer and a barrier layer grown on the potential well layer, the number of periods is 4, and the growth temperature of the potential well layer in each period is 780°C. The growth pressure of the potential well layer in one period is 200 Torr, the V/III molar ratio of the potential well layer in each period is 4500, and the thickness of the potential well layer in each period is 2.5nm; The barrier layers of each period of a multi-quantum well layer are respectively doped with Si, the effective doping concentration of Si is 2×1017 /cm3 , the growth temperature of the barrier layers of each period is 900°C, and each The growth pressure of the barrier layer in one period is 200 Torr, the V/III molar ratio of the barrier layer in each period is 4500, and the barrier layer in each period has a thickness of 12 nm.
在本发明的一个实施例中，在所述第一多量子阱层中，所述Si掺杂在所述势垒层之远离所述势阱层的位置。In one embodiment of the present invention, in the first multiple quantum well layer, the Si doping is at a position away from the potential well layer from the potential barrier layer.
在本发明的另一实施例中，所述势垒层厚度的10％～90％掺杂有所述Si。In another embodiment of the present invention, 10%-90% of the thickness of the barrier layer is doped with the Si.
另一方面，本发明实施例提供了一种制造半导体发光二极管外延片的方法，包括：On the other hand, an embodiment of the present invention provides a method for manufacturing a semiconductor light emitting diode epitaxial wafer, including:
提供一衬底；providing a substrate;
在所述衬底上依次生长低温缓冲层、高温缓冲层、复合N型层、复合多量子阱层和复合P型层，其中，所述复合多量子阱层包括第一多量子阱层和在所述第一多量子阱层上生长的第二多量子阱层，所述第一多量子阱层为多周期结构，每一周期包括势阱层和在所述势阱层上生长的势垒层，A low-temperature buffer layer, a high-temperature buffer layer, a composite N-type layer, a composite multi-quantum well layer, and a composite P-type layer are sequentially grown on the substrate, wherein the composite multi-quantum well layer includes the first multi-quantum well layer and the first multi-quantum well layer. The second multi-quantum well layer grown on the first multi-quantum well layer, the first multi-quantum well layer is a multi-period structure, and each period includes a potential well layer and a potential barrier grown on the potential well layer layer,
其中，周期数为4，每一周期的所述势阱层的生长温度为780℃，每一周期的所述势阱层的生长压力为200Torr，每一周期的所述势阱层的Ⅴ/Ⅲ摩尔比为4500，每一周期的所述势阱层的厚度为2.5nm；生长所述第一多量子阱层每一周期的势垒层时，在所述势垒层中掺杂Si，Si的有效掺杂浓度为2×1017/cm3，每一周期的所述势垒层的生长温度为900℃，每一周期的所述势垒层的生长压力为200Torr，每一周期的所述势垒层的Ⅴ/Ⅲ摩尔比为4500，每一周期的所述势垒层的厚度为12nm。Wherein, the number of cycles is 4, the growth temperature of the described potential well layer of each cycle is 780° C., the growth pressure of the described potential well layer of each cycle is 200 Torr, and the V/ of the described potential well layer of each cycle is The molar ratio of III is 4500, and the thickness of the potential well layer of each period is 2.5nm; when growing the barrier layer of each period of the first multi-quantum well layer, Si is doped in the barrier layer, The effective doping concentration of Si is 2×1017 /cm3 , the growth temperature of the barrier layer in each cycle is 900°C, the growth pressure of the barrier layer in each cycle is 200 Torr, and the growth pressure of the barrier layer in each cycle is 200 Torr. The V/III molar ratio of the barrier layer is 4500, and the thickness of each period of the barrier layer is 12 nm.
在本发明的一个实施例中，在所述第一多量子阱层中，所述Si掺杂在所述势垒层之远离所述势阱层的位置。In one embodiment of the present invention, in the first multiple quantum well layer, the Si doping is at a position away from the potential well layer from the potential barrier layer.
在本发明的另一实施例中，所述势垒层厚度的10％～90％掺杂有所述Si。In another embodiment of the present invention, 10%-90% of the thickness of the barrier layer is doped with the Si.
本发明实施例提供的技术方案带来的有益效果是：The beneficial effects brought by the technical solution provided by the embodiments of the present invention are:
第一多量子阱层的势垒层在低温下生长时，势垒层掺杂的Si可以抑制势垒层的表面形成螺旋岛状结构，因此势垒层的表面特性好，这进一步使得层叠在第一多量子阱层上的第二多量子阱层的晶体质量好、发光效率高。When the barrier layer of the first multi-quantum well layer was grown at a low temperature, the Si doped in the barrier layer could suppress the formation of a spiral island structure on the surface of the barrier layer, so the surface characteristics of the barrier layer were good, which further made stacking in The second multi-quantum well layer on the first multi-quantum well layer has good crystal quality and high luminous efficiency.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.
图1为本发明实施例提供的半导体发光二极管的外延片的结构示意图；1 is a schematic structural view of an epitaxial wafer of a semiconductor light-emitting diode provided by an embodiment of the present invention;
图2为图1所示外延片中复合多量子阱层的详细结构示意图；Fig. 2 is the detailed structure schematic diagram of composite multiple quantum well layer in the epitaxial wafer shown in Fig. 1;
图3为本发明实施例提供的制造半导体发光二极管外延片的方法的流程图。FIG. 3 is a flowchart of a method for manufacturing a semiconductor light emitting diode epitaxial wafer provided by an embodiment of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.
实施例一Embodiment one
本实施例提供了一种半导体发光二极管的外延片，参加图1，该外延片包括衬底1和依次层叠在衬底1上的低温缓冲层2、高温缓冲层3、复合N型层、复合多量子阱层和复合P型层。该复合多量子阱层包括第一多量子阱层8和在第一多量子阱层8上生长的第二多量子阱层9。结合图2，第一多量子阱层8为多周期结构，每一周期包括势阱层b1和在势阱层b1上生长的势垒层a1。第一多量子阱层8的每一周期的势垒层a1分别掺杂有Si，图2中斜线区域表示势垒层a1中掺杂Si的部分。This embodiment provides an epitaxial wafer of a semiconductor light-emitting diode, refer to FIG. 1, the epitaxial wafer includes a substrate 1 and a low-temperature buffer layer 2, a high-temperature buffer layer 3, a composite N-type layer, a composite Multi-quantum well layer and composite P-type layer. The composite multiple quantum well layer includes a first multiple quantum well layer 8 and a second multiple quantum well layer 9 grown on the first multiple quantum well layer 8 . Referring to FIG. 2 , the first multi-quantum well layer 8 has a multi-period structure, and each period includes a potential well layer b1 and a barrier layer a1 grown on the potential well layer b1. The barrier layer a1 of each period of the first multi-quantum well layer 8 is respectively doped with Si, and the hatched area in FIG. 2 represents the portion doped with Si in the barrier layer a1 .
进一步地，在第一多量子阱层8中，Si掺杂在势垒层a1之远离势阱层b1的位置。Further, in the first multi-quantum well layer 8 , Si is doped in the position of the barrier layer a1 away from the potential well layer b1 .
上述技术方案的优点是：在靠近势阱层的位置不掺杂Si，能避免了Si扩散到势阱层中形成非辐射复合。进一步地，势垒层厚度的10％～90％掺杂有Si，Si这样的掺杂厚度比例既能够抑制位错，又不至于Si扩散到阱中。The advantage of the above technical solution is that no Si is doped near the potential well layer, which can prevent Si from diffusing into the potential well layer to form non-radiative recombination. Furthermore, 10% to 90% of the thickness of the barrier layer is doped with Si, and such a doping thickness ratio of Si can suppress dislocations and prevent Si from diffusing into the well.
进一步地，Si的有效掺杂浓度为5×1016～1×1019/cm3，这样的有效掺杂浓度既能够抑制位错，又不至于掺杂浓度多高，带来额外的缺陷。Furthermore, the effective doping concentration of Si is 5×1016 -1×1019 /cm3 , such an effective doping concentration can suppress dislocations, but will not cause additional defects due to high doping concentration.
进一步地，势垒层的厚度为10～15nm，这样的范围能够很好的限定载流子在阱区复合，且起到了提高量子阱晶体质量的作用。Further, the thickness of the barrier layer is 10-15 nm, and such a range can well limit the recombination of carriers in the well region, and play a role in improving the quality of the quantum well crystal.
进一步地，第一多量子阱层的周期数为2～6，这样的周期数既起到了提高晶体质量的作用，又不至于周期数过多，而导致后面生长的量子阱晶体质量下降。Further, the period number of the first multi-quantum well layer is 2-6, and such a period number not only plays a role in improving the crystal quality, but also prevents too many period numbers from degrading the quality of the quantum well crystal grown later.
由上述技术方案可知，第一多量子阱层的势垒层在低温下生长时，势垒层掺杂的Si可以抑制势垒层的表面形成螺旋岛状结构，因此势垒层的表面特性好，这进一步使得层叠在第一多量子阱层上的第二多量子阱层的晶体质量好、发光效率高。It can be seen from the above technical scheme that when the barrier layer of the first multi-quantum well layer is grown at low temperature, the Si doped in the barrier layer can inhibit the surface of the barrier layer from forming a spiral island structure, so the surface properties of the barrier layer are good. , which further makes the second multi-quantum well layer stacked on the first multi-quantum well layer have good crystal quality and high luminous efficiency.
另外，势垒层掺杂Si一方面可以降低势垒层的点缺陷密度，因而能提高在低温度下生长的势垒层的晶体质量，同时可以有效屏蔽极化场。In addition, doping the barrier layer with Si can reduce the point defect density of the barrier layer on the one hand, so it can improve the crystal quality of the barrier layer grown at low temperature, and can effectively shield the polarization field at the same time.
实施例二Embodiment two
本实施例提供了一种制造半导体发光二极管外延片的方法，该方法利用ThomasSwan(AIXTRON子公司)CCS MOCVD系统实施，并且该方法以高纯氢气(H2)或氮气(N2)作为载气，以三甲基镓(TMGa)或者三乙基镓(TEGa)、三甲基铝(TMAl)、三甲基铟(TMIn)和氨气(NH3)分别作为Ga、Al、In和N源，用硅烷(SiH4)、二茂镁(Cp2Mg)分别作为N、P型掺杂剂。This embodiment provides a method for manufacturing semiconductor light-emitting diode epitaxial wafers. The method is implemented using a ThomasSwan (AIXTRON subsidiary) CCS MOCVD system, and the method uses high-purity hydrogen (H2 ) or nitrogen (N2 ) as a carrier gas , with trimethylgallium (TMGa) or triethylgallium (TEGa), trimethylaluminum (TMAl), trimethylindium (TMIn) and ammonia (NH3 ) as Ga, Al, In and N sources, respectively , using silane (SiH4 ) and dimagnesocene (Cp2Mg) as N and P type dopants respectively.
具体地，参考图3，并结合图1和图2，本实施例制造半导体发光二极管外延片的方法包括如下步骤：Specifically, referring to FIG. 3, and in combination with FIG. 1 and FIG. 2, the method for manufacturing a semiconductor light-emitting diode epitaxial wafer in this embodiment includes the following steps:
步骤S1，提供一衬底1并对衬底1进行热清洗及氮化处理：将衬底1在1050～1200℃温度范围内(例如1180℃)、纯氢气气氛里热清洗衬底1的表面，然后将衬底1降温至630℃，在该温度下进行氮化处理，本实施例中，衬底1是适合氮化镓及其它半导体外延材料生长的材料，如氮化镓单晶、蓝宝石、单晶硅、碳化硅单晶等；Step S1, provide a substrate 1 and perform thermal cleaning and nitriding treatment on the substrate 1: thermally clean the surface of the substrate 1 in the temperature range of 1050-1200°C (for example, 1180°C) in a pure hydrogen atmosphere , and then lower the temperature of the substrate 1 to 630° C., and perform nitriding treatment at this temperature. In this embodiment, the substrate 1 is a material suitable for the growth of gallium nitride and other semiconductor epitaxial materials, such as gallium nitride single crystal, sapphire , single crystal silicon, silicon carbide single crystal, etc.;
步骤S2，在衬底1上生长低温缓冲层2：衬底1处理后，将温度下降到500℃～650℃(例如630℃下),在衬底1表面生长一层低温缓冲层2(该低温缓冲层2掺杂GaN)，此生长过程中，生长压力为300～760Torr(例如生长压力为400Torr)，Ⅴ/Ⅲ摩尔比为600～3000(例如Ⅴ/Ⅲ摩尔比为900)，其中低温缓冲层2的厚度为20～30nm(例如厚度为25nm)；Step S2, growing a low-temperature buffer layer 2 on the substrate 1: after the substrate 1 is treated, lower the temperature to 500°C-650°C (for example, at 630°C), and grow a layer of low-temperature buffer layer 2 on the surface of the substrate 1 (the The low temperature buffer layer 2 is doped with GaN), during this growth process, the growth pressure is 300-760 Torr (for example, the growth pressure is 400 Torr), and the V/III molar ratio is 600-3000 (for example, the V/III molar ratio is 900), wherein the low temperature The buffer layer 2 has a thickness of 20-30 nm (for example, a thickness of 25 nm);
步骤S3，在低温缓冲层2上生长高温缓冲层3：低温缓冲层2生长结束后，停止通入TMGa(三甲基镓)，将衬底1的温度升高至1000～1200℃(例如升高至1170℃)，对低温缓冲层2进行热退火处理，热退火时间为5～10分钟(例如5分钟)，热退火处理之后，将温度调节至1000～1200℃(例如调节至1180℃)，，在低温缓冲层2上生长一层高温缓冲层3(该高温缓冲层3不掺杂GaN)，此生长过程中，生长压力为100～600Torr(例如生长压力为200Torr)，Ⅴ/Ⅲ摩尔比为300～3000(例如Ⅴ/Ⅲ摩尔比为1500)，其中高温缓冲层3的厚度为0.8～2μm(例如厚度为1.2μm)；Step S3, growing a high-temperature buffer layer 3 on the low-temperature buffer layer 2: after the growth of the low-temperature buffer layer 2 is completed, stop feeding TMGa (trimethylgallium), and raise the temperature of the substrate 1 to 1000-1200° C. up to 1170°C), the low-temperature buffer layer 2 is subjected to thermal annealing, and the thermal annealing time is 5 to 10 minutes (for example, 5 minutes), after the thermal annealing treatment, the temperature is adjusted to 1000 to 1200°C (for example, adjusted to 1180°C) , grow a layer of high-temperature buffer layer 3 on the low-temperature buffer layer 2 (the high-temperature buffer layer 3 is not doped with GaN), during this growth process, the growth pressure is 100-600 Torr (for example, the growth pressure is 200 Torr), V/III The ratio is 300-3000 (for example, the V/III molar ratio is 1500), and the thickness of the high-temperature buffer layer 3 is 0.8-2 μm (for example, the thickness is 1.2 μm);
步骤S4，在高温缓冲层3上生长第一N型层4：高温缓冲层3生长结束后，在高温缓冲层3上生长一层第一N型层4，此生长过程中，生长压力为100～600Torr(例如生长压力为150Torr)，Ⅴ/Ⅲ摩尔比为300～3000(例如Ⅴ/Ⅲ摩尔比为1800)，生长温度为1000～1200℃(例如生长温度为1180℃),其中第一N型层4的厚度在0.2～1μm(例如厚度为0.8μm)，第一N型层4掺杂有SiH4，掺杂浓度从1×1017/cm3变化到5×1018/cm3；Step S4, growing the first N-type layer 4 on the high-temperature buffer layer 3: after the growth of the high-temperature buffer layer 3 is completed, a layer of the first N-type layer 4 is grown on the high-temperature buffer layer 3. During this growth process, the growth pressure is 100 ～600Torr (for example, the growth pressure is 150Torr), the V/III molar ratio is 300～3000 (for example, the V/III molar ratio is 1800), and the growth temperature is 1000～1200°C (for example, the growth temperature is 1180°C), where the first N The thickness of the N-type layer 4 is 0.2-1 μm (for example, the thickness is 0.8 μm), the first N-type layer 4 is doped with SiH4, and the doping concentration varies from 1×1017 /cm3 to 5×1018 /cm3 ;
步骤S5，在第一N型层4上生长第二N型层5：第一N型层4生长结束后，在第一N型层4上生长一层第二N型层5，此生长过程中，生长压力为100～600Torr(例如生长压力为150Torr)，Ⅴ/Ⅲ摩尔比为300～3000(例如Ⅴ/Ⅲ摩尔比为1800)，生长温度为1000℃～1200℃(例如生长温度为1180℃),其中第二N型层5的厚度为1.2～3.5μm(例如厚度为3.5μm)，第二N型层5掺杂有SiH4，掺杂浓度稳定；Step S5, growing a second N-type layer 5 on the first N-type layer 4: after the growth of the first N-type layer 4 is completed, a layer of second N-type layer 5 is grown on the first N-type layer 4. This growth process Among them, the growth pressure is 100 to 600 Torr (for example, the growth pressure is 150 Torr), the V/III molar ratio is 300 to 3000 (for example, the V/III molar ratio is 1800), and the growth temperature is 1000°C to 1200°C (for example, the growth temperature is 1180 °C), wherein the thickness of the second N-type layer 5 is 1.2-3.5 μm (for example, the thickness is 3.5 μm), the second N-type layer 5 is doped with SiH4, and the doping concentration is stable;
步骤S6，在第二N型层5上生长第三N型层6：第二N型层5生长结束后，在第二N型层5上生长一层第三N型层6，此生长过程中，生长压力为100～600Torr(例如生长压力为150Torr)，Ⅴ/Ⅲ摩尔比为300～3000(例如Ⅴ/Ⅲ摩尔比为2800)，生长温度为1000～1200℃(例如生长温度为1180℃,)，其中第三N型层6的厚度为10～100nm(例如厚度为20nm)，第三N型层6掺杂有SiH4，掺杂浓度稳定，掺杂浓度低于第一N型层4的平均浓度，低于第二N型层5的掺杂浓度，远低于第四N型层7的掺杂浓度，其目的是为了提高载流子的迁移率；Step S6, growing a third N-type layer 6 on the second N-type layer 5: after the growth of the second N-type layer 5 is completed, a layer of third N-type layer 6 is grown on the second N-type layer 5. This growth process Among them, the growth pressure is 100-600 Torr (for example, the growth pressure is 150 Torr), the V/III molar ratio is 300-3000 (for example, the V/III molar ratio is 2800), and the growth temperature is 1000-1200°C (for example, the growth temperature is 1180°C ,), wherein the thickness of the third N-type layer 6 is 10-100nm (for example, the thickness is 20nm), the third N-type layer 6 is doped with SiH4, the doping concentration is stable, and the doping concentration is lower than that of the first N-type layer 4 The average concentration is lower than the doping concentration of the second N-type layer 5, far lower than the doping concentration of the fourth N-type layer 7, the purpose of which is to increase the mobility of carriers;
步骤S7，在第三N型层6上生长第四N型层7：第三N型层6生长结束后，在第三N型层6上生长一层第四N型层7，此生长过程中，生长压力为100～600Torr(例如生长压力为150Torr)，Ⅴ/Ⅲ摩尔比为300～3000(例如Ⅴ/Ⅲ摩尔比为2800)；生长温度为1000～1200℃(例如生长温度为1180℃)，其中第四N型层7的厚度为10～50nm(例如厚度为10nm)，第四N型层7掺杂有SiH4，掺杂浓度稳定，掺杂浓度高于第二N型层5的掺杂浓度，该第四N型层7是整个N型区域浓度最高的区域，其目的是为了获得更高的载流子浓度；Step S7, growing a fourth N-type layer 7 on the third N-type layer 6: after the growth of the third N-type layer 6 is completed, a layer of fourth N-type layer 7 is grown on the third N-type layer 6. This growth process Among them, the growth pressure is 100-600 Torr (for example, the growth pressure is 150 Torr), the V/III molar ratio is 300-3000 (for example, the V/III molar ratio is 2800); the growth temperature is 1000-1200°C (for example, the growth temperature is 1180°C ), wherein the thickness of the fourth N-type layer 7 is 10-50 nm (for example, the thickness is 10 nm), the fourth N-type layer 7 is doped with SiH4, the doping concentration is stable, and the doping concentration is higher than that of the second N-type layer 5 Doping concentration, the fourth N-type layer 7 is the region with the highest concentration in the entire N-type region, the purpose of which is to obtain a higher carrier concentration;
步骤S8，在第四N型层7上生长一层第一多量子阱(MQW)层8：N型层7生长结束后，在N型层7上生长一层第一多量子阱层8，第一多量子阱层8为多周期结构，周期数为2～6(例如周期数为4)，每一周期包括势阱层b1(InaGa1-aN层，0＜a＜1)和层叠在势阱层b1上的势垒层(GaN层)a1(例如每一周期包括In0.3Ga0.7N层和GaN层)，其中每一周期势阱层b1的生长工艺条件为：生长温度为720～850℃(例如生长温度为780℃)，生长压力为100～500Torr(例如生长压力为200Torr)，Ⅴ/Ⅲ摩尔比为300～5000(例如Ⅴ/Ⅲ摩尔比为4500)，每一周期势阱层b1的厚度为2～3nm(例如厚度为2.5nm)；每一周期的势垒层a1分别掺杂有Si，Si掺杂在势垒层a1之远离势阱层b1的位置。具体地，势垒层厚度的10％～90％(例如50％)掺杂有Si，Si的有效掺杂浓度为5×1016～1×1019/cm3(例如有效掺杂浓度为2×1017/cm3，需要说明的是，有效掺杂浓度是指能激活的最大杂质浓度，这里“激活”是通过一定手段将掺入Si中的杂质离化，形成导电机制的过程)，图2中斜线区域表示势垒层a1中掺杂Si的部分。，每一周期势垒层a1的生长工艺条件为：生长温度为820～950℃(例如生长温度为900℃)，生长压力为100～500Torr(例如生长压力为200Torr)，Ⅴ/Ⅲ摩尔比为300～5000(例如Ⅴ/Ⅲ摩尔比为4500)，每一周期势垒层a1的厚度为10～15nm(例如厚度为12nm)；Step S8, growing a first multi-quantum well (MQW) layer 8 on the fourth N-type layer 7: after the growth of the N-type layer 7 is completed, growing a first multi-quantum well layer 8 on the N-type layer 7, The first multi-quantum well layer 8 is a multi-period structure, the number of periods is 2 to 6 (for example, the number of periods is 4), and each period includes a potential well layer b1 (Ina Ga1-a N layer, 0<a<1) and the barrier layer (GaN layer) a1 stacked on the potential well layer b1 (for example, each cycle includes In0.3 Ga0.7 N layer and GaN layer), wherein the growth process conditions of each cycle of the potential well layer b1 are: growth temperature 720-850°C (for example, the growth temperature is 780°C), the growth pressure is 100-500Torr (for example, the growth pressure is 200Torr), the V/III molar ratio is 300-5000 (for example, the V/III molar ratio is 4500), each The thickness of the periodic potential well layer b1 is 2-3 nm (for example, the thickness is 2.5 nm); the barrier layer a1 of each period is respectively doped with Si, and Si is doped in the position of the potential barrier layer a1 away from the potential well layer b1. Specifically, 10% to 90% (for example, 50%) of the thickness of the barrier layer is doped with Si, and the effective doping concentration of Si is 5×1016 to 1×1019 /cm3 (for example, the effective doping concentration is 2 ×1017 /cm3 , it should be noted that the effective doping concentration refers to the maximum impurity concentration that can be activated, and here "activation" is the process of ionizing the impurities doped into Si by certain means to form a conductive mechanism), The shaded area in FIG. 2 represents the Si-doped portion of the barrier layer a1. , the growth process conditions of the barrier layer a1 in each period are as follows: the growth temperature is 820-950°C (for example, the growth temperature is 900°C), the growth pressure is 100-500Torr (for example, the growth pressure is 200Torr), and the V/III molar ratio is 300-5000 (for example, the V/III molar ratio is 4500), and the thickness of the barrier layer a1 of each period is 10-15nm (for example, the thickness is 12nm);
步骤S9，在第一多量子阱层8上生长一层第二多量子阱(MQW)层9：第一多量子阱层8生长结束后，在第一多量子阱层8上生长一层第二多量子阱层9，该第二多量子阱层9为多周期结构，周期数为3～6(例如周期数为5)，每一周期包括势阱层b2(InbGa1-bN层，0＜b＜1)和层叠在势阱层b2上的势垒层(GaN)a2(例如每一周期包括In0.3Ga0.7N层和GaN层)。其中每一周期势阱层b2的生长工艺条件为：生长温度为720～820℃(例如生长温度为780℃)，生长压力为100～500Torr(例如生长压力为200Torr)，Ⅴ/Ⅲ摩尔比为300～5000(例如Ⅴ/Ⅲ摩尔比为4500)，每一周期势阱层b2的厚度为2～3nm(例如厚度为2.5nm)；每一周期势垒层a2的生长工艺条件为：生长温度为820～920℃(例如生长温度为900℃)，生长压力为100～500Torr(例如生长压力为200Torr)，Ⅴ/Ⅲ摩尔比为300～5000(例如Ⅴ/Ⅲ摩尔比为4500)，每一周期势垒层a2的总厚度为10～15nm(例如厚度为12nm)，其中，势垒层a2不掺杂；步骤S10，在第二多量子阱层9上生长一层第一P型层10：第二多量子阱层9生长结束后，在第二多量子阱层9上生长一层第一P型层10，该第一P型层10为AlxGa1-xN材料，0＜x＜1，起到电子阻挡的作用，第一P型层10的生长过程中，生长温度为950～1080℃(例如温度为1020℃)，生长压力为50～500Torr(例如生长压力为300Torr)，Ⅴ/Ⅲ摩尔比为1000～20000(例如Ⅴ/Ⅲ摩尔比为12000)，其中第一P型层10的厚度为10～200nm(例如生长厚度为20nm)，该第一P型层10的禁带宽度为4～5.5eV，P型层10掺杂有Mg(镁)，P型层10掺杂有二茂镁(Cp2Mg)，掺杂的Mg与第一P型层10中Ga的摩尔比为1/100～1/4(例如摩尔比为：Mg/Ga＝1/4)；Step S9, growing a second multi-quantum well (MQW) layer 9 on the first multi-quantum well layer 8: after the growth of the first multi-quantum well layer 8 is completed, a second multi-quantum well layer (MQW) layer is grown on the first multi-quantum well layer 8 Two multi-quantum well layers 9, the second multi-quantum well layer 9 is a multi-period structure, the number of periods is 3 to 6 (for example, the number of periods is 5), and each period includes a potential well layer b2 (Inb Ga1-b N layer, 0<b<1) and a barrier layer (GaN) a2 laminated on the well layer b2 (for example, each period includes an In0.3 Ga0.7 N layer and a GaN layer). Wherein the growth process conditions of the potential well layer b2 in each cycle are as follows: the growth temperature is 720-820° C. (for example, the growth temperature is 780° C.), the growth pressure is 100-500 Torr (for example, the growth pressure is 200 Torr), and the V/III molar ratio is 300-5000 (for example, the V/III molar ratio is 4500), the thickness of the potential well layer b2 of each period is 2-3nm (for example, the thickness is 2.5nm); the growth process conditions of each period of the barrier layer a2 are: growth temperature 820-920°C (for example, the growth temperature is 900°C), the growth pressure is 100-500Torr (for example, the growth pressure is 200Torr), the V/III molar ratio is 300-5000 (for example, the V/III molar ratio is 4500), each The total thickness of the periodic barrier layer a2 is 10-15nm (for example, the thickness is 12nm), wherein the barrier layer a2 is not doped; step S10, growing a layer of first P-type layer 10 on the second multi-quantum well layer 9 : After the growth of the second multi-quantum well layer 9 ends, a layer of first P-type layer 10 is grown on the second multi-quantum well layer 9, the first P-type layer 10 is made of AlxGa1-xN material, 0<x<1, which acts as an electron barrier. During the growth process of the first P-type layer 10, the growth temperature is 950-1080° C. (for example, the temperature is 1020° C.), and the growth pressure is 50-500 Torr (for example, the growth pressure is 300 Torr). , the V/III molar ratio is 1000-20000 (for example, the V/III molar ratio is 12000), wherein the thickness of the first P-type layer 10 is 10-200 nm (for example, the growth thickness is 20 nm), the first P-type layer 10 The forbidden band width is 4-5.5eV, the P-type layer 10 is doped with Mg (magnesium), the P-type layer 10 is doped with dichloromagnesium (Cp2Mg), the doped Mg and the mole of Ga in the first P-type layer 10 The ratio is 1/100～1/4 (for example, the molar ratio is: Mg/Ga=1/4);
步骤S11，在第一P型层10上生长一层第二P型层11：第一P型层10生长结束后，在第一P型层10上生长一层第二P型层11，该第二P型层11为GaN材料，第二P型层11的生长过程中，生长压力200Torr，Ⅴ/Ⅲ摩尔比8000，生长温度为850～1050℃(例如生长温度1000℃)，其中第二P型层11的厚度为100～800nm(例如厚度为0.4μm)，第二P型层11掺杂有二茂镁(Cp2Mg)，掺杂的Mg与第二P型层11中Ga的摩尔比为1/100～1/4(例如摩尔比为：1/80)；Step S11, growing a second P-type layer 11 on the first P-type layer 10: after the growth of the first P-type layer 10 is completed, growing a second P-type layer 11 on the first P-type layer 10, the The second P-type layer 11 is made of GaN material. During the growth process of the second P-type layer 11, the growth pressure is 200 Torr, the V/III molar ratio is 8000, and the growth temperature is 850-1050° C. (for example, the growth temperature is 1000° C.), wherein the second The thickness of the P-type layer 11 is 100-800 nm (for example, the thickness is 0.4 μm), the second P-type layer 11 is doped with dichloromagnesium (Cp2Mg), and the molar ratio of doped Mg to Ga in the second P-type layer 11 1/100～1/4 (for example, molar ratio: 1/80);
步骤S12，在第二P型层11上生长一层第三P型层12：第二P型层11生长结束后，在第二P型层11上生长一层第三P型层12，该第三P型层12为GaN材料，是接触层，第三P型层12的生长过程中，生长压力为100～760Torr(例如生长压力为200Torr)，Ⅴ/Ⅲ摩尔比为1000～20000(例如Ⅴ/Ⅲ摩尔比10000)，生长温度为850～1050℃之间(例如生长温度为1050℃)，其中第三P型层12的厚度为5～20nm(例如厚度为15nm)，第三P型层10掺杂有二茂镁(Cp2Mg)，掺杂的Mg与第三P型层12中Ga的摩尔比为1/100～1/4(例如摩尔比为：Mg/Ga＝1/50)；Step S12, growing a third P-type layer 12 on the second P-type layer 11: after the growth of the second P-type layer 11 is completed, growing a third P-type layer 12 on the second P-type layer 11, the The third P-type layer 12 is a GaN material, which is a contact layer. During the growth process of the third P-type layer 12, the growth pressure is 100-760 Torr (for example, the growth pressure is 200 Torr), and the V/III molar ratio is 1000-20000 (for example, Ⅴ/Ⅲ molar ratio 10000), the growth temperature is between 850～1050°C (for example, the growth temperature is 1050°C), wherein the thickness of the third P-type layer 12 is 5～20nm (for example, the thickness is 15nm), the third P-type Layer 10 is doped with magnesocene (Cp2Mg), and the molar ratio of doped Mg to Ga in the third P-type layer 12 is 1/100-1/4 (for example, the molar ratio is: Mg/Ga=1/50) ;
步骤S13，后期处理：第三P型层12生长结束后，将反应腔的温度降至650～850℃(例如降至800℃)，在纯氮气氛围进行退火处理5～15min(例如处理10min)，然后降至室温，至此，半导体发光二极管的外延片制作完成。Step S13, post-processing: after the growth of the third P-type layer 12 is completed, reduce the temperature of the reaction chamber to 650-850° C. (for example, to 800° C.), and perform annealing treatment in a pure nitrogen atmosphere for 5-15 minutes (for example, 10 minutes). , and then lowered to room temperature, so far, the epitaxial wafer of the semiconductor light emitting diode is fabricated.
需要说明的是，半导体发光二极管的外延片制作完成后，在第三P型层12上生长一层透明导电层(ITO)13，在透明导电层13上焊接一个P电极14，在第二N型层5上焊接一个N电极15，这样半导体发光二极管制作完成。半导体发光二极管经过清洗、沉积、光刻和刻蚀等半导体加工工艺制程后，分割成尺寸大小为11×11mil的LED芯片。经LED芯片测试，测试电流20mA，单颗小芯片光输出功率为11.5mW或11.0mW。而传统的外延生长方式，相同芯片制程的单颗小芯片光的输出功率为10.2mW。It should be noted that after the epitaxial wafer of the semiconductor light emitting diode is fabricated, a layer of transparent conductive layer (ITO) 13 is grown on the third P-type layer 12, a P electrode 14 is welded on the transparent conductive layer 13, and a P electrode 14 is welded on the second N-type layer 12. An N electrode 15 is welded on the type layer 5, and the semiconductor light-emitting diode is manufactured like this. Semiconductor light-emitting diodes are divided into LED chips with a size of 11×11mil after being processed by semiconductor processing processes such as cleaning, deposition, photolithography and etching. After the LED chip test, the test current is 20mA, and the light output power of a single small chip is 11.5mW or 11.0mW. In the traditional epitaxial growth method, the light output power of a single small chip with the same chip manufacturing process is 10.2mW.
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.
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| Publication number | Priority date | Publication date | Assignee | Title |
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