CN103280196A - Shifting register and thin film transistor liquid crystal display - Google Patents

Abstract

Translated fromChinese

本发明提供一种移位寄存器及薄膜晶体管液晶显示器，所述移位寄存器包括多级由九个晶体管和一个电容组成的移位寄存电路，所述移位寄存电路包括信号输出模块的上拉晶体管、第一下拉晶体管、第二下拉晶体，第三下拉晶体管、开关晶体管，第一电容，复位晶体管，和辅助下拉模块的第一辅助下拉晶体管、第二辅助下拉晶体管和并联连接的第三辅助下拉晶体管和第二电容。第二电容作为缓冲器件，能够过滤输出信号中多余的毛刺信号，减少了信号串扰，同时由于第一下拉晶体管和第二下拉晶体管各自在半个下拉周期工作，也抑制了因晶体管宽长比过大的阈值电压的漂移，进而保证了电路的稳定性。通过设置辅助下拉模块，能够使第二节点的输出波形更加稳定。

The invention provides a shift register and a thin film transistor liquid crystal display, the shift register includes a multi-stage shift register circuit composed of nine transistors and a capacitor, and the shift register circuit includes a pull-up transistor of a signal output module , the first pull-down transistor, the second pull-down crystal, the third pull-down transistor, the switch transistor, the first capacitor, the reset transistor, and the first auxiliary pull-down transistor of the auxiliary pull-down module, the second auxiliary pull-down transistor and the third auxiliary pull-down transistor connected in parallel pull-down transistor and second capacitor. As a buffer device, the second capacitor can filter the redundant burr signal in the output signal, reducing signal crosstalk. At the same time, since the first pull-down transistor and the second pull-down transistor work in half of the pull-down period, it also suppresses the problem caused by the width-to-length ratio of the transistor. Excessive threshold voltage drift, thereby ensuring the stability of the circuit. By setting the auxiliary pull-down module, the output waveform of the second node can be made more stable.

Description

Translated fromChinese

一种移位寄存器及薄膜晶体管液晶显示器A kind of shift register and thin film transistor liquid crystal display

技术领域technical field

本发明涉及液晶平板显示技术，尤其涉及一种移位寄存器及薄膜晶体管液晶显示器。The invention relates to liquid crystal flat panel display technology, in particular to a shift register and a thin film transistor liquid crystal display.

背景技术Background technique

以TFT-LCD(Thin film transistor-Liquid crystal display，薄膜晶体管液晶显示器)为代表的FPD(平板显示器件)技术自20世纪90年代开始迅速发展并逐步走向成熟。由于TFT-LCD具有高清晰、低功耗、轻薄、便于携带等优点，已被广泛应用于上述信息显示产品中，使LCD进入高画质、高彩色显示的新阶段，具有广阔的市场前景。目前几乎所有高档的LCD中都毫无例外地使用了TFT有源矩阵。TFT(Thin film transistor)有源矩阵主要包括A-Si(amorphous silicon)TFT有源矩阵和P-Si(poly-silicon)TFT有源矩阵两种。与P-Si TFT技术相比，A-Si TFT技术发展比较成熟，均匀性好且成本较低，但其迁移率较低，一般在0.1～1.0cm²/V·s，P-Si TFT的迁移率则可达50～200cm²/V·s。由于A-Si TFT迁移率比较低，致使其驱动电路速度较慢。The FPD (Flat Panel Display Device) technology represented by TFT-LCD (Thin film transistor-Liquid crystal display) has developed rapidly since the 1990s and gradually matured. Since TFT-LCD has the advantages of high definition, low power consumption, thinness, and portability, it has been widely used in the above-mentioned information display products, making LCD enter a new stage of high-quality, high-color display, and has broad market prospects. At present, almost all high-end LCDs use TFT active matrix without exception. TFT (Thin film transistor) active matrix mainly includes A-Si (amorphous silicon) TFT active matrix and P-Si (poly-silicon) TFT active matrix. Compared with P-Si TFT technology, A-Si TFT technology is relatively mature, with good uniformity and low cost, but its mobility is low, generally 0.1-1.0cm² /V s, P-Si TFT The mobility can reach 50-200cm² /V·s. Due to the relatively low mobility of the A-Si TFT, the speed of its driving circuit is relatively slow.

中小尺寸LCD主要应用于便携式产品，因此在技术性能要求上与大尺寸LCD有所不同。中小尺寸产品更加强调显示器的轻、薄、器件的集成能力、更好的可靠性以及低成本。目前，市场对LCD的分辨率也提出了更高要求，为了使小型化LCD具有高分辨率，减少TFT-LCD驱动IC的数目是非常必要的。通常，当LCD的分辨率高于QVGA(240×RGB×320)时，TFT面板需要超过1000条外部引线。当产品分辨率进一步增加时，在有限的空间内制作更多的外引线就变得非常困难。Small and medium-sized LCDs are mainly used in portable products, so their technical performance requirements are different from those of large-sized LCDs. Small and medium-sized products put more emphasis on the lightness and thinness of the display, the integration capability of the device, better reliability and low cost. At present, the market also puts forward higher requirements on the resolution of LCD. In order to make the miniaturized LCD have high resolution, it is very necessary to reduce the number of TFT-LCD driver ICs. Usually, when the resolution of the LCD is higher than QVGA (240×RGB×320), the TFT panel requires more than 1000 external leads. When the product resolution is further increased, it becomes very difficult to make more external leads in a limited space.

以上技术问题可以通过将驱动电路(gate driver circuits或source driver circuits)集成在有源矩阵LCD基板上来解决。这种技术可以使显示器成本更低、结构更紧凑、机械可靠性更高从而使其具有更大的市场竞争力。The above technical problems can be solved by integrating the driver circuits (gate driver circuits or source driver circuits) on the active matrix LCD substrate. This technology can make the display lower cost, more compact structure, higher mechanical reliability and thus make it more competitive in the market.

并且随着技术的发展，扫描电路趋向于电路集成化，越来越多的公司采用移位寄存器代替了扫描驱动IC，从而减小了LCD的显示边框大小，同时由于电路集成在显示面板上，也降低了IC的使用数量，从而大大降低了显示面板的制作成本。And with the development of technology, the scanning circuit tends to be circuit integrated. More and more companies use shift registers instead of scanning driver ICs, thereby reducing the size of the LCD display frame. At the same time, because the circuit is integrated on the display panel, It also reduces the number of ICs used, thereby greatly reducing the production cost of the display panel.

随着高端产品越来越追求窄边框和轻型化，因此移位寄存电路的尺寸要求不断减小，同时移位寄存电路为作为驱动电路控制有源矩阵LCD基板的显示，故要求移位寄存电路能够提供稳定的电流。As high-end products are increasingly pursuing narrow borders and light weight, the size of the shift register circuit is continuously reduced. At the same time, the shift register circuit is used as a drive circuit to control the display of the active matrix LCD substrate, so the shift register circuit is required Can provide stable current.

因此，提供一种晶体管数量少使整体尺寸小且工作提供的信号波形稳定的移位寄存器和由该种移位寄存器级联形成的薄膜晶体管液晶显示器成为业界广泛关注的问题。Therefore, providing a shift register with a small number of transistors, a small overall size and stable signal waveforms and a thin film transistor liquid crystal display formed by cascading such shift registers has become an issue of widespread concern in the industry.

发明内容Contents of the invention

本发明所要解决的技术问题是提供一种晶体管数量少、工作波形稳定的移位寄存器和由该种移位寄存器级联形成的薄膜晶体管液晶显示器。The technical problem to be solved by the present invention is to provide a shift register with a small number of transistors and a stable working waveform and a thin film transistor liquid crystal display formed by cascading the shift register.

为解决上述问题，本发明提供一种移位寄存器，包括多级级联的移位寄存电路，每一移位寄存电路，包括：In order to solve the above problems, the present invention provides a shift register, including multi-stage cascaded shift register circuits, and each shift register circuit includes:

主输入端和主输出端；main input and main output;

信号输出模块，包括分别耦接于所述主输出端的上拉晶体管、第一下拉晶体管、第二下拉晶体管，所述上拉晶体管的输入端接第一节点，所述上拉晶体管用以在开启时产生高电平的输出信号至所述主输出端，所述第一下拉晶体管和第二下拉晶体管用以在开启时交替产生低电平的输出信号至所述主输出端，所述第二下拉晶体管的输入端接第二节点；The signal output module includes a pull-up transistor, a first pull-down transistor, and a second pull-down transistor respectively coupled to the main output terminal, the input terminal of the pull-up transistor is connected to the first node, and the pull-up transistor is used for When turned on, a high-level output signal is generated to the main output terminal, and the first pull-down transistor and the second pull-down transistor are used to alternately generate a low-level output signal to the main output terminal when turned on. The input terminal of the second pull-down transistor is connected to the second node;

开关晶体管，耦接于所述主输入端和所述第一节点之间，用以根据主时钟信号和主输入端的输入信号控制所述上拉晶体管的开启；a switch transistor, coupled between the main input terminal and the first node, and used to control the turn-on of the pull-up transistor according to a main clock signal and an input signal at the main input terminal;

第一电容，耦接于所述第一节点和所述主输出端之间，用以利用电容自举效应为所述上拉晶体管提供稳定电压；a first capacitor, coupled between the first node and the main output terminal, for providing a stable voltage for the pull-up transistor by utilizing a capacitive bootstrap effect;

复位晶体管，耦接于所述第一节点，用以控制所述上拉晶体管的关闭和所述主输出端输出的输出信号的重置；以及a reset transistor, coupled to the first node, for controlling the shutdown of the pull-up transistor and the reset of the output signal output by the main output terminal; and

下拉辅助模块，耦接于所述主输出端和所述第二节点，用以实现所述第一下拉晶体管和第二下拉晶体管交替产生低电平的输出信号，所述下拉辅助模块包括：第一辅助下拉晶体管，用以根据主时钟信号快速释放所述第二节点的高电平；第二辅助下拉晶体管，用以根据所述主输出端的输出信号为反馈控制所述第二节点的电平，进而稳定所述主输出端的电平；以及第三辅助下拉晶体管，用以根据所述从时钟信号拉高所述第二节点的电平，所述从时钟信号与所述主时钟信号反相；所述信号输出模块还包括第三下拉晶体管，所述第三下拉晶体管的输入端接第一节点，用于根据所在移位寄存电路的前一移位寄存电路的第二节点下拉第一节点的电平。The pull-down auxiliary module, coupled to the main output terminal and the second node, is used to realize that the first pull-down transistor and the second pull-down transistor alternately generate low-level output signals, and the pull-down auxiliary module includes: The first auxiliary pull-down transistor is used to quickly release the high level of the second node according to the main clock signal; the second auxiliary pull-down transistor is used to control the voltage of the second node according to the output signal of the main output terminal as feedback Level, thereby stabilizing the level of the main output terminal; and a third auxiliary pull-down transistor, used to pull up the level of the second node according to the slave clock signal, the slave clock signal is opposite to the master clock signal Phase; the signal output module also includes a third pull-down transistor, the input terminal of the third pull-down transistor is connected to the first node, and is used to pull down the first The level of the node.

进一步的，在所述移位寄存器中，第一级移位寄存电路的开关晶体管接收初始信号，其后每级移位寄存电路的开关晶体管耦接于其前级移位寄存电路的主输出端；最后一级移位寄存电路的开关晶体管接收最终复位信号，其他每级移位寄存电路的复位晶体管耦接于其后级移位寄存电路的主输出端。Further, in the shift register, the switch transistors of the first-stage shift register circuit receive the initial signal, and then the switch transistors of each stage shift register circuit are coupled to the main output terminal of the preceding stage shift register circuit ; The switching transistor of the last stage of shift register circuit receives the final reset signal, and the reset transistors of each stage of shift register circuit are coupled to the main output terminal of the subsequent stage of shift register circuit.

进一步的，所述上拉晶体管、第一下拉晶体管、第二下拉晶体管、第三下拉晶体管、开关晶体管、复位晶体管、第一辅助下拉晶体管、第二辅助下拉晶体管以及第三辅助下拉晶体管均为薄膜场效应晶体管。Further, the pull-up transistor, the first pull-down transistor, the second pull-down transistor, the third pull-down transistor, the switch transistor, the reset transistor, the first auxiliary pull-down transistor, the second auxiliary pull-down transistor, and the third auxiliary pull-down transistor are all thin film field effect transistor.

进一步的，在每一移位寄存电路中：在所述信号输出模块中：所述上拉晶体管的栅极接第一节点、源极接所述从时钟信号、漏极接所述主输出端；所述第一下拉晶体管的栅极接所述主时钟信号、源极接所述主输出端、漏接接低电平端；所述第二下拉晶体管的栅极接第二节点、源极接所述主输出端、漏极接低电平端；所述第三下拉晶体管的源极接第一节点、栅极接其所在移位寄存电路的前一移位寄存电路的第二节点下拉第二节点、漏极接低电平端；所述开关晶体管的栅极接所述主时钟信号、源极接所述主输入端、漏极接所述第一节点；所述复位晶体管的栅极接后一移位寄存电路的主输出端、源极接所述第一节点、漏极接低电平端；以及在所述下拉辅助模块中：所述第一辅助下拉晶体管的栅极接所述主时钟信号、源极接所述第二节点、漏极接所述低电平端；所述第二辅助下拉晶体管的栅极接所述主输出端、源极接所述第二节点、漏极接所述低电平端；所述第三辅助下拉晶体管的栅极和漏极接所述从时钟信号、源极接所述第二节点。Further, in each shift register circuit: in the signal output module: the gate of the pull-up transistor is connected to the first node, the source is connected to the slave clock signal, and the drain is connected to the main output terminal The gate of the first pull-down transistor is connected to the main clock signal, the source is connected to the main output terminal, and the drain is connected to the low level end; the gate of the second pull-down transistor is connected to the second node, the source connected to the main output terminal, and the drain to the low level terminal; the source of the third pull-down transistor is connected to the first node, and the gate is connected to the second node of the previous shift register circuit of the shift register circuit where it is located to pull down the second node Two nodes, the drain is connected to the low level terminal; the gate of the switching transistor is connected to the main clock signal, the source is connected to the main input terminal, and the drain is connected to the first node; the gate of the reset transistor is connected to the first node The main output end of the latter shift register circuit, the source is connected to the first node, and the drain is connected to the low level end; and in the pull-down auxiliary module: the gate of the first auxiliary pull-down transistor is connected to the main clock signal, the source is connected to the second node, and the drain is connected to the low-level end; the gate of the second auxiliary pull-down transistor is connected to the main output terminal, the source is connected to the second node, and the drain is connected to the second node. The low level end; the gate and drain of the third auxiliary pull-down transistor are connected to the slave clock signal, and the source is connected to the second node.

进一步的，所述第三辅助下拉晶体管的宽长比大于所述第二辅助下拉晶体管的宽长比。Further, the aspect ratio of the third auxiliary pull-down transistor is greater than that of the second auxiliary pull-down transistor.

进一步的，所述第三辅助下拉晶体管的宽长比大于所述第二辅助下拉晶体管的宽长比的十倍。Further, the width-to-length ratio of the third auxiliary pull-down transistor is greater than ten times the width-to-length ratio of the second auxiliary pull-down transistor.

进一步的，所述第一电容接所述第一节点和主输出端之间。Further, the first capacitor is connected between the first node and the main output terminal.

进一步的，所述第一下拉晶体管和第二下拉晶体管的工作时间分别为下拉周期的一半。Further, the working time of the first pull-down transistor and the second pull-down transistor is half of the pull-down period respectively.

进一步的，所述移位寄存器中移位寄存电路分为奇数级移位寄存电路和偶数级移位寄存电路，所述奇数级移位寄存电路接收的主时钟信号与所述偶数级移位寄存电路接收的主时钟信号反相。Further, the shift register circuit in the shift register is divided into an odd-numbered shift register circuit and an even-numbered shift register circuit, and the master clock signal received by the odd-numbered shift register circuit is the same as that of the even-numbered shift register circuit. The master clock signal received by the circuit is inverted.

本发明还提供一种薄膜晶体管液晶显示器，包括显示阵列和栅极驱动电路，所述用以产生多个栅极信号来控制所述显示阵列，所述栅极驱动电路包括前述的移位寄存器。The present invention also provides a thin film transistor liquid crystal display, including a display array and a gate drive circuit, which is used to generate a plurality of gate signals to control the display array, and the gate drive circuit includes the aforementioned shift register.

综上所述，本发明所述的移位寄存器的移位寄存电路利用输出信号作为反馈进一步控制信号稳定输出，从而达到电流稳定控制下拉电压的目的，同时采用双下拉晶体管对输出端进行下拉，且能够利用100％的下拉周期进行充分下拉，避免了浮空状态，进而时电路稳定。In summary, the shift register circuit of the shift register of the present invention uses the output signal as feedback to further control the stable output of the signal, thereby achieving the purpose of stabilizing the current and controlling the pull-down voltage, and at the same time using a double pull-down transistor to pull down the output terminal. Moreover, the 100% pull-down period can be used to perform full pull-down, avoiding the floating state, and then the circuit is stable.

进一步的，本发明所述移位寄存器增加设置所述第三下拉晶体管，所述第三下拉晶体管能够根据所在移位寄存电路的前一移位寄存电路的第二节点的电压控制当前移位寄存电路的第一节点的电平的下拉，从而保持第一节点的下拉电位，进而优化移位寄存器的整体驱动能力。Further, the shift register of the present invention is additionally provided with the third pull-down transistor, and the third pull-down transistor can control the voltage of the second node of the previous shift register circuit where the shift register circuit is located. The level of the first node of the circuit is pulled down to maintain the pull-down potential of the first node, thereby optimizing the overall driving capability of the shift register.

本发明还提供一种由前述的移位寄存器组成的薄膜晶体管液晶显示器，所述薄膜晶体管液晶显示器包括显示阵列和栅极驱动电路，所述移位寄存器用以产生多个栅极信号来控制所述显示阵列，所述栅极驱动电路包括采用前述的移位寄存器。采用本发明所述的移位寄存器组成的薄膜晶体管液晶显示器的显示更加稳定，反应速度更快，且减小了面板尺寸，实现高端轻薄产品的顺利量产，进一步降低生产成本。The present invention also provides a thin film transistor liquid crystal display composed of the aforementioned shift register, the thin film transistor liquid crystal display includes a display array and a gate drive circuit, the shift register is used to generate a plurality of gate signals to control the In the above display array, the gate drive circuit includes the aforementioned shift register. The thin film transistor liquid crystal display composed of the shift register of the present invention has more stable display, faster response speed, reduced panel size, smooth mass production of high-end light and thin products, and further reduces production costs.

附图说明Description of drawings

图1为本发明一实施例中移位寄存器的结构示意图。FIG. 1 is a schematic structural diagram of a shift register in an embodiment of the present invention.

图2为本发明一实施例中移位寄存电路的结构示意图。FIG. 2 is a schematic structural diagram of a shift register circuit in an embodiment of the present invention.

图3为本发明一实施例中移位寄存器工作过程中的信号时序图。FIG. 3 is a timing diagram of signals during the working process of the shift register in an embodiment of the present invention.

图4为本发明一实施例中移位寄存器与现有技术一移位寄存电路的工作过程的信号时序图。FIG. 4 is a signal timing diagram of a working process of a shift register in an embodiment of the present invention and a shift register circuit in the prior art.

具体实施方式Detailed ways

为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例，本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应以此作为对本发明的限定。Secondly, the present invention is described in detail by means of schematic diagrams. When describing the examples of the present invention in detail, for the convenience of explanation, the schematic diagrams are not partially enlarged according to the general scale, which should not be used as a limitation of the present invention.

图1为本发明一实施例中移位寄存器的结构示意图，如图1所示，所述移位寄存器的移位寄存电路依次产生栅极信号控制显示阵列进行图像显示。其中，在本实施例中，所述移位寄存器中移位寄存电路分为奇数级移位寄存电路和偶数级移位寄存电路，所述奇数级移位寄存电路接收的主时钟信号与所述偶数级移位寄存电路接收的主时钟信号反相，即奇数级移位寄存电路接收的主时钟信号CK1对应接收第一时钟信号CLK，相应所述偶数级移位寄存电路接收的主时钟信号CK2对应接收第二时钟信号CLKB，第一时钟信号CLK与第二时钟信号CLKB反相。并且第一级移位寄存电路的开关晶体管M1接收初始信号STP，其后每级移位寄存电路的开关晶体管M1耦接于其前级移位寄存电路的主输出端OUT，即第N+1级移位寄存电路的开关晶体管M1耦接于第N级移位寄存电路的主输出端OUT，其中N为小于移位寄存电路总数的正整数；最后一级移位寄存电路的复位晶体管M2接收最终复位信号，其他每级移位寄存电路的复位晶体管M2耦接于其后级移位寄存电路的主输出端OUT，从而实现每一移位寄存电路的输出信号控制其后一移位寄存电路的开启，每一移位寄存电路的输出信号控制其前一移位寄存电路的复位，使移位寄存器中的移位寄存电路依次输出输出信号。FIG. 1 is a schematic structural diagram of a shift register in an embodiment of the present invention. As shown in FIG. 1 , the shift register circuit of the shift register sequentially generates gate signals to control the display array to display images. Wherein, in this embodiment, the shift register circuit in the shift register is divided into an odd-numbered shift register circuit and an even-numbered shift register circuit, and the master clock signal received by the odd-numbered shift register circuit is the same as the The master clock signal received by the even-numbered shift register circuit is inverted, that is, the master clock signal CK1 received by the odd-numbered shift register circuit corresponds to the first clock signal CLK, and the master clock signal CK2 received by the even-numbered shift register circuit corresponds to Corresponding to receiving the second clock signal CLKB, the first clock signal CLK is inverted from the second clock signal CLKB. And the switch transistor M1 of the first stage shift register circuit receives the initial signal STP, and then the switch transistor M1 of each stage shift register circuit is coupled to the main output terminal OUT of the previous stage shift register circuit, that is, the N+1th The switch transistor M1 of the stage shift register circuit is coupled to the main output terminal OUT of the Nth stage shift register circuit, where N is a positive integer less than the total number of shift register circuits; the reset transistor M2 of the last stage shift register circuit receives The final reset signal, the reset transistor M2 of each other shift register circuit is coupled to the main output terminal OUT of the subsequent shift register circuit, so that the output signal of each shift register circuit controls the next shift register circuit is turned on, the output signal of each shift register circuit controls the reset of its previous shift register circuit, so that the shift register circuits in the shift register output the output signals in sequence.

图2为本发明一实施例中移位寄存电路的结构示意图。结合图1和图2，本发明提供一种移位寄存器，包括多级级联的移位寄存电路，每一移位寄存电路，包括：主输入端IN和主输出端OUT、信号输出模块100、开关晶体管M1、第一电容C1、复位晶体管M2和辅助下拉模块200。FIG. 2 is a schematic structural diagram of a shift register circuit in an embodiment of the present invention. 1 and 2, the present invention provides a shift register, including multi-stage cascaded shift register circuits, each shift register circuit includes: a main input terminal IN and a main output terminal OUT, a signal output module 100 , a switch transistor M1 , a first capacitor C1 , a reset transistor M2 and an auxiliary pull-down module 200 .

所述信号输出模块100包括分别耦接于所述主输出端OUT的上拉晶体管M3、第一下拉晶体管M6和第二下拉晶体管M8，所述上拉晶体管M3的输入端接第一节点，所述上拉晶体管M3用以在开启时产生高电平的输出信号至所述主输出端Out，所述第一下拉晶体管M6和第二下拉晶体管M8用以在开启时交替产生低电平的输出信号至所述主输出端Out，所述第二下拉晶体管M8的输入端接第二节点Q；The signal output module 100 includes a pull-up transistor M3, a first pull-down transistor M6, and a second pull-down transistor M8 respectively coupled to the main output terminal OUT, the input terminal of the pull-up transistor M3 is connected to the first node, The pull-up transistor M3 is used to generate a high-level output signal to the main output terminal Out when turned on, and the first pull-down transistor M6 and the second pull-down transistor M8 are used to alternately generate a low level when turned on The output signal of the main output terminal Out, the input terminal of the second pull-down transistor M8 is connected to the second node Q;

所述开关晶体管M1耦接于所述主输入端和所述第一节点P之间，用以根据主时钟信号CK1和主输入端IN的输入信号控制所述上拉晶体管M3的开启；The switch transistor M1 is coupled between the main input terminal and the first node P, and is used for controlling the turn-on of the pull-up transistor M3 according to the main clock signal CK1 and the input signal of the main input terminal IN;

所述第一电容C1耦接于所述第一节点P和所述主输出端OUT之间，用以利用电容自举效应为所述上拉晶体管M3提供稳定电压；The first capacitor C1 is coupled between the first node P and the main output terminal OUT, and is used to provide a stable voltage for the pull-up transistor M3 by utilizing a capacitor bootstrap effect;

所述复位晶体管M2耦接于所述第一节点P，用以控制所述上拉晶体管M3的关闭和所述主输出端IN输出的输出信号的重置；以及The reset transistor M2 is coupled to the first node P, and is used to control the closing of the pull-up transistor M3 and the reset of the output signal output from the main output terminal IN; and

所述辅助下拉模块200耦接于所述主输出端IN和所述第二节点Q，用以实现所述第一下拉晶体管M6和第二下拉晶体管M8交替产生低电平的输出信号，所述辅助下拉模块包括：第一辅助下拉晶体管M5，用以根据主时钟信号快速释放所述第二节点Q的高电平；第二辅助下拉晶体管M7，用以根据所述主输出端OUT的输出信号为反馈控制所述第二节点Q的电平，进而稳定所述主输出端OUT的电平；以及第三辅助下拉晶体管M4，用以根据所述从时钟信号拉高所述第二节点的电平，其中所述从时钟信号与所述主时钟信号反相。此外，所述信号输出模块还包括第三下拉晶体管M9，所述第三下拉晶体管M9的输入端接第一节点P，用于根据所在移位寄存电路的前一移位寄存电路的第二节点下拉第一节点P的电平。通过前一级移位寄存电路的第二节点Q的信号下拉本级移位寄存电路的第一节点P的电平，从而使移位寄存电路更加稳定。The auxiliary pull-down module 200 is coupled to the main output terminal IN and the second node Q to realize that the first pull-down transistor M6 and the second pull-down transistor M8 alternately generate low-level output signals, so The auxiliary pull-down module includes: a first auxiliary pull-down transistor M5, used to quickly release the high level of the second node Q according to the main clock signal; a second auxiliary pull-down transistor M7, used to The signal is to feedback control the level of the second node Q, thereby stabilizing the level of the main output terminal OUT; and the third auxiliary pull-down transistor M4, used to pull up the level of the second node according to the slave clock signal level, wherein the slave clock signal is inverted from the master clock signal. In addition, the signal output module further includes a third pull-down transistor M9, the input terminal of the third pull-down transistor M9 is connected to the first node P, and is used to pull down the level of the first node P. The level of the first node P of the shift register circuit of the present stage is pulled down by the signal of the second node Q of the shift register circuit of the previous stage, thereby making the shift register circuit more stable.

同时，所述移位寄存电路中辅助下拉模块200均为并联电阻的结构，因此第二节点Q的输出波形能够更快达到高电平，进而使信号反应速度更快，使最终输出波形更加稳定。At the same time, the auxiliary pull-down module 200 in the shift register circuit is a structure of parallel resistors, so the output waveform of the second node Q can reach a high level faster, thereby making the signal response faster and making the final output waveform more stable .

本发明所述移位寄存器有多个级联的移位寄存电路，每一级移位寄存电路包括九个晶体管和一个电容，即9T1C的电路结构。其中，M1是开关晶体管，M2是复位晶体管，M3是上拉晶体管，M6是第一下拉晶体管，M8是第二下拉晶体管，M5、M7和M4分别为第一至第三辅助下拉晶体管，M9是第三下拉晶体管。本发明所述的移位寄存电路所使用晶体管数目少，可以有效降低边框大小，减小面板的尺寸，并有效降低了面板的成本；同时，保证了移位寄存电路正常工作，电路稳定，并提高反应速度。在本实施例中，所述上拉晶体管M3、第一下拉晶体管M6、第二下拉晶体管M8、第三下拉晶体管M9、开关晶体管M1、复位晶体管M2、第一辅助下拉晶体管M5、第二辅助下拉晶体管M6以及第三辅助下拉晶体管M4均为薄膜场效应晶体管。The shift register of the present invention has multiple cascaded shift register circuits, and each stage of shift register circuits includes nine transistors and one capacitor, that is, the circuit structure of 9T1C. Wherein, M1 is a switch transistor, M2 is a reset transistor, M3 is a pull-up transistor, M6 is a first pull-down transistor, M8 is a second pull-down transistor, M5, M7 and M4 are respectively the first to third auxiliary pull-down transistors, M9 is the third pull-down transistor. The number of transistors used in the shift register circuit of the present invention is small, which can effectively reduce the size of the frame, reduce the size of the panel, and effectively reduce the cost of the panel; at the same time, it ensures that the shift register circuit works normally, the circuit is stable, and Improve reaction speed. In this embodiment, the pull-up transistor M3, the first pull-down transistor M6, the second pull-down transistor M8, the third pull-down transistor M9, the switch transistor M1, the reset transistor M2, the first auxiliary pull-down transistor M5, the second auxiliary Both the pull-down transistor M6 and the third auxiliary pull-down transistor M4 are thin film field effect transistors.

在每一移位寄存电路中：在所述信号输出模块中：所述上拉晶体管M3的栅极接第一节点P、源极接所述时钟信号CK2、漏极接所述主输出端OUT；所述第一下拉晶体管M6的栅极接所述主时钟信号CK1、源极接所述主输出端、漏接接低电平端；所述第二下拉晶体管M8的栅极接第二节点Q、源极接所述主输出端OUT、漏极接低电平端VGL；所述开关晶体管M1的栅极接所述主时钟信号CK1、源极接所述主输入端IN、漏极接所述第一节点P；所述复位晶体管M2的栅极接后一移位寄存电路的主输出端OUT、源极接所述第一节点P、漏极接低电平端VGL；以及在所述辅助下拉模块中：所述第一辅助下拉晶体管M5的栅极接所述主时钟信号CK1、源极接所述第二节点Q、漏极接所述低电平端VGL；所述第二辅助下拉晶体管M7的栅极接所述主输出端OUT、源极接所述第二节点Q、漏极接所述低电平端VGL；所述第三辅助下拉晶体管M4的栅极和漏极接所述从时钟信号CK2、源极接所述第二节点Q。所述移位寄存电路中辅助下拉模块均为并联电阻的结构，因此Q点的输出波形能够更快达到高电平，进而使信号反应速度更快，提高反应速度并使最终输出波形更加稳定。In each shift register circuit: in the signal output module: the gate of the pull-up transistor M3 is connected to the first node P, the source is connected to the clock signal CK2, and the drain is connected to the main output terminal OUT The gate of the first pull-down transistor M6 is connected to the main clock signal CK1, the source is connected to the main output terminal, and the drain is connected to the low level end; the gate of the second pull-down transistor M8 is connected to the second node Q. The source is connected to the main output terminal OUT, the drain is connected to the low-level terminal VGL; the gate of the switching transistor M1 is connected to the main clock signal CK1, the source is connected to the main input terminal IN, and the drain is connected to the the first node P; the gate of the reset transistor M2 is connected to the main output terminal OUT of a shift register circuit, the source is connected to the first node P, and the drain is connected to the low level terminal VGL; and in the auxiliary In the pull-down module: the gate of the first auxiliary pull-down transistor M5 is connected to the main clock signal CK1, the source is connected to the second node Q, and the drain is connected to the low-level terminal VGL; the second auxiliary pull-down transistor The gate of M7 is connected to the main output terminal OUT, the source is connected to the second node Q, and the drain is connected to the low-level terminal VGL; the gate and drain of the third auxiliary pull-down transistor M4 are connected to the slave The source of the clock signal CK2 is connected to the second node Q. The auxiliary pull-down modules in the shift register circuit all have a structure of parallel resistors, so the output waveform at the Q point can reach a high level faster, thereby making the signal response faster, improving the response speed and making the final output waveform more stable.

图3为本发明一实施例中移位寄存器工作过程中的信号时序图。结合图2和图3，第一辅助下拉晶体管M5的作用主要是释放掉第二节点Q的高电压，使得第二下拉晶体管M8能够工作在50％的周期中，加上第一下拉晶体管M6在主时钟脉冲信号CK1输出高脉冲时主输出端OUT的电平下拉，从而使所述移位寄存电路达到100％的下拉周期，从而没有浮空周期，避免了浮空状态，进而使电路稳定。FIG. 3 is a timing diagram of signals during the working process of the shift register in an embodiment of the present invention. 2 and 3, the function of the first auxiliary pull-down transistor M5 is mainly to release the high voltage of the second node Q, so that the second pull-down transistor M8 can work in 50% of the cycle, plus the first pull-down transistor M6 When the main clock pulse signal CK1 outputs a high pulse, the level of the main output terminal OUT is pulled down, so that the shift register circuit reaches a 100% pull-down period, so that there is no floating period, and the floating state is avoided, thereby making the circuit stable. .

在较佳的实施例中，所述第三辅助下拉晶体管M4的宽长比大于所述第二辅助下拉晶体管M7的宽长比。在较佳的实施例中，所述第三辅助下拉晶体管M4的宽长比大于所述第二辅助下拉晶体管M7的宽长比的十倍。所述移位寄存电路通过主输出端OUT提供输出信号，该输出信号反馈第二辅助下拉晶体管M7，由于第二辅助下拉晶体管M7的宽长比远大于第三辅助下拉管M4的宽长比，所以第二辅助下拉晶体管M7的电流比第三辅助下拉管M4的电流更大，使得第二节点Q的电流更接近第二辅助下拉晶体管M7导通的低电平VGL的电压，形成如图3所示的波形，从而使得过滤掉了从时钟信号CK2的一个高脉冲信号。In a preferred embodiment, the width-to-length ratio of the third auxiliary pull-down transistor M4 is greater than the width-to-length ratio of the second auxiliary pull-down transistor M7. In a preferred embodiment, the width-to-length ratio of the third auxiliary pull-down transistor M4 is greater than ten times the width-to-length ratio of the second auxiliary pull-down transistor M7. The shift register circuit provides an output signal through the main output terminal OUT, and the output signal is fed back to the second auxiliary pull-down transistor M7. Since the width-to-length ratio of the second auxiliary pull-down transistor M7 is much greater than that of the third auxiliary pull-down transistor M4, Therefore, the current of the second auxiliary pull-down transistor M7 is larger than the current of the third auxiliary pull-down transistor M4, so that the current of the second node Q is closer to the voltage of the low-level VGL turned on by the second auxiliary pull-down transistor M7, forming as shown in FIG. 3 As shown in the waveform, a high pulse signal from the clock signal CK2 is filtered out.

进一步的，所述第一电容C1接所述第一节点P和主输出端OUT之间。Further, the first capacitor C1 is connected between the first node P and the main output terminal OUT.

进一步的，所述第一下拉晶体管M6和第二下拉晶体管M8的工作时间分别为下拉周期的一半。由于第一下拉晶体管M6和第二下拉晶体管M8各自在半个下拉周期工作，也抑制了因晶体管宽长比过大的阈值电压的漂移，进而保证了电路的稳定性。通过设置辅助下拉模块200，能够使第二节点的输出波形更加稳定。Further, the working time of the first pull-down transistor M6 and the second pull-down transistor M8 is half of the pull-down period respectively. Since the first pull-down transistor M6 and the second pull-down transistor M8 each work in half a pull-down period, the drift of the threshold voltage due to the excessively large width-to-length ratio of the transistors is also suppressed, thereby ensuring the stability of the circuit. By setting the auxiliary pull-down module 200, the output waveform of the second node can be made more stable.

图4为本发明一实施例中移位寄存器与现有技术一移位寄存电路的工作过程中P点信号时序图。图4中曲折线200表示采用图2所示的移位寄存电路的工作过程中第一节点P的信号时序图，而曲折线100表示一种现有技术的未设置第三下拉晶体管的移位寄存电路的在工作过程中第一节点的信号时序图，由图4可知，在第一节点P充电进入高电位前，由A点可以看到，本发明所述移位寄存电路的第一节点P维持在-10V的低电压，由B点可以看到，而现有技术的移位寄存电路的第一节点P的电压为-8.264V，由C点可以看到，增加第三下拉晶体管后，第一节点P点在进入高电位之前的电位能进一步下拉2.1107V，从而优化下拉电压及保持能力得到很大提升。由此可知，增加第三下拉晶体管能够保持第一节点P的下拉能力，从而优化移位寄存电路的驱动能力，进而优化移位寄存器的整体驱动能力。FIG. 4 is a time sequence diagram of signals at point P during the working process of the shift register in an embodiment of the present invention and a shift register circuit in the prior art. The zigzagging line 200 in Fig. 4 represents the signal timing diagram of the first node P in the working process of the shift register circuit shown in Fig. The signal timing diagram of the first node in the working process of the register circuit, as can be seen from Figure 4, before the first node P is charged into a high potential, it can be seen from point A that the first node of the shift register circuit according to the present invention P is maintained at a low voltage of -10V, which can be seen from point B, while the voltage of the first node P of the shift register circuit in the prior art is -8.264V, which can be seen from point C, after adding the third pull-down transistor , the potential of the first node P before entering the high potential can be further pulled down to 2.1107V, thereby optimizing the pull-down voltage and greatly improving the holding capacity. It can be seen that adding the third pull-down transistor can maintain the pull-down capability of the first node P, thereby optimizing the driving capability of the shift register circuit, and further optimizing the overall driving capability of the shift register.

综上所述，本发明所述的移位寄存器的移位寄存电路利用输出信号作为反馈进一步控制信号稳定输出，从而达到电流稳定控制下拉电压的目的，同时采用双下拉晶体管对输出端进行下拉，且能够利用100％的下拉周期进行充分下拉，避免了浮空状态，进而时电路稳定。In summary, the shift register circuit of the shift register of the present invention uses the output signal as feedback to further control the stable output of the signal, thereby achieving the purpose of stabilizing the current and controlling the pull-down voltage, and at the same time using a double pull-down transistor to pull down the output terminal. Moreover, the 100% pull-down period can be used to perform full pull-down, avoiding the floating state, and then the circuit is stable.

进一步的，本发明所述移位寄存器增加设置所述第三下拉晶体管，所述第三下拉晶体管能够根据所在移位寄存电路的前一移位寄存电路的第二节点的电压控制当前移位寄存电路的第一节点的电平的下拉，从而保持第一节点的下拉电位，进而优化移位寄存器的整体驱动能力。Further, the shift register of the present invention is additionally provided with the third pull-down transistor, and the third pull-down transistor can control the voltage of the second node of the previous shift register circuit where the shift register circuit is located. The level of the first node of the circuit is pulled down to maintain the pull-down potential of the first node, thereby optimizing the overall driving capability of the shift register.

本发明还提供一种由前述的移位寄存器组成的薄膜晶体管液晶显示器，所述薄膜晶体管液晶显示器包括显示阵列和栅极驱动电路，所述移位寄存器用以产生多个栅极信号来控制所述显示阵列，所述栅极驱动电路包括采用前述的移位寄存器。采用本发明所述的移位寄存器组成的薄膜晶体管液晶显示器的显示更加稳定，反应速度更快，且减小了面板尺寸，实现高端轻薄产品的顺利量产，进一步降低生产成本。The present invention also provides a thin film transistor liquid crystal display composed of the aforementioned shift register, the thin film transistor liquid crystal display includes a display array and a gate drive circuit, the shift register is used to generate a plurality of gate signals to control the In the above display array, the gate drive circuit includes the aforementioned shift register. The thin film transistor liquid crystal display composed of the shift register of the present invention has more stable display, faster response speed, reduced panel size, smooth mass production of high-end light and thin products, and further reduces production cost.

虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视权利要求书所界定者为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the scope of protection of the present invention should be defined by the claims.

Claims (10)

1. shift register comprises the shift register circuit of multi-stage cascade, and each shift register circuit comprises:

Primary input end and main output terminal;

Signal output module, comprise and be respectively coupled to the pulling up transistor of described main output terminal, first pull-down transistor, second pull-down transistor, the described input termination first node that pulls up transistor, described pulling up transistor in order to when opening, to produce the described main output terminal that outputs signal to of high level, described first pull-down transistor and second pull-down transistor are in order to alternately to produce the low level described main output terminal that outputs signal to, the input termination Section Point of described second pull-down transistor when opening;

Switching transistor is coupled between described primary input end and the described first node, in order to the described unlatching that pulls up transistor of input signal control according to master clock signal and primary input end;

First electric capacity is coupled between described first node and the described main output terminal, provides burning voltage in order to utilize the electric capacity bootstrap effect for described pulling up transistor;

Reset transistor is coupled to described first node, in order to control the described replacement of closing the output signal of exporting with described main output terminal that pulls up transistor; And

Drop-down supplementary module is coupled to described main output terminal and described Section Point, alternately produces low level output signal in order to realize described first pull-down transistor and second pull-down transistor, and described drop-down supplementary module comprises:

The first auxiliary pull-down transistor is in order to discharge the high level of described Section Point fast according to master clock signal;

The second auxiliary pull-down transistor is the level of the described Section Point of FEEDBACK CONTROL in order to the output signal according to described main output terminal, and then stablizes the level of described main output terminal; And

The 3rd auxiliary pull-down transistor, in order to according to the level of drawing high described Section Point from clock signal, described anti-phase from clock signal and described master clock signal;

Described signal output module also comprises the 3rd pull-down transistor, and the input termination first node of described the 3rd pull-down transistor is used for the level according to the drop-down first node of Section Point of the last shift register circuit of place shift register circuit.

2. shift register as claimed in claim 1, it is characterized in that, in described shift register, the switching transistor of first order shift register circuit receives initialize signal, and the switching transistor of every grade of shift register circuit is coupled to the main output terminal of its prime shift register circuit thereafter; The switching transistor of afterbody shift register circuit receives final reset signal, and the reset transistor of other every grade shift register circuit is coupled to the main output terminal of level shift register circuit thereafter.

3. shift register as claimed in claim 2, it is characterized in that, describedly pull up transistor, first pull-down transistor, second pull-down transistor, the 3rd pull-down transistor, switching transistor, reset transistor, the first auxiliary pull-down transistor, the second auxiliary pull-down transistor and the 3rd auxiliary pull-down transistor be Thin Film Transistor (TFT).

4. shift register as claimed in claim 3 is characterized in that, in each shift register circuit:

In described signal output module: the described grid that pulls up transistor connects first node, source electrode and connects and describedly connect described main output terminal from clock signal, drain electrode; The grid of described first pull-down transistor connects described master clock signal, source electrode and connects described main output terminal, misses and connect low level end; The grid of described second pull-down transistor connects that Section Point, source electrode connect described main output terminal, drain electrode connects low level end; The source electrode of described the 3rd pull-down transistor connects the drop-down Section Point of Section Point, the drain electrode that first node, grid connect the last shift register circuit of its place shift register circuit and connects low level end;

The grid of described switching transistor connects that described master clock signal, source electrode connect described primary input end, drain electrode connects described first node;

Main output terminal, the source electrode that the grid of described reset transistor connects back one shift register circuit connects described first node, drain electrode connects low level end; And in described drop-down supplementary module:

The grid of the described first auxiliary pull-down transistor connects that described master clock signal, source electrode connect described Section Point, drain electrode connects described low level end;

The grid of the described second auxiliary pull-down transistor connects that described main output terminal, source electrode connect described Section Point, drain electrode connects described low level end;

The grid of the described the 3rd auxiliary pull-down transistor and drain electrode connect and describedly connect described Section Point from clock signal, source electrode.

5. shift register as claimed in claim 4 is characterized in that, the breadth length ratio of the described the 3rd auxiliary pull-down transistor is greater than the breadth length ratio of the described second auxiliary pull-down transistor.

6. shift register as claimed in claim 5 is characterized in that, the breadth length ratio of the described the 3rd auxiliary pull-down transistor is greater than ten times of the breadth length ratio of the described second auxiliary pull-down transistor.

7. shift register as claimed in claim 3 is characterized in that, described first electric capacity connects between described first node and the main output terminal.

8. as any described shift register in the claim 1 to 7, it is characterized in that the working time of described first pull-down transistor and second pull-down transistor is respectively half of drop-down cycle.

9. as any described shift register in the claim 1 to 7, it is characterized in that, shift register circuit is divided into odd level shift register circuit and even level shift register circuit in the described shift register, and the master clock signal that the master clock signal that described odd level shift register circuit receives and described even level shift register circuit receive is anti-phase.

10. Thin Film Transistor-LCD, it is characterized in that, comprise array of display and gate driver circuit, described gate driver circuit is controlled described array of display in order to produce a plurality of signals, and described gate driver circuit comprises as any described shift register in the claim 1 to 9.

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