技术领域technical field
本发明涉及显示技术领域，特别是涉及一种阵列基板、显示装置及阵列基板的制造方法。The present invention relates to the field of display technology, in particular to an array substrate, a display device and a manufacturing method of the array substrate.
背景技术Background technique
在平板显示装置中，薄膜晶体管液晶显示器（ThinFilmTransistorLiquidCrystalDisplay，简称TFT-LCD）具有体积小、功耗低、制造成本相对较低和无辐射等特点，在当前的平板显示器市场占据了主导地位。Among flat panel display devices, Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, relatively low manufacturing cost and no radiation, and occupies a dominant position in the current flat panel display market.
目前，TFT-LCD的显示模式主要有TN（TwistedNematic，扭曲向列）模式、VA（VerticalAlignment，垂直取向）模式、IPS（In-Plane-Switching，平面方向转换）模式和AD-SDS（ADvancedSuperDimensionSwitch，高级超维场转换技术，简称ADS）模式等。At present, the display modes of TFT-LCD mainly include TN (TwistedNematic, twisted nematic) mode, VA (VerticalAlignment, vertical orientation) mode, IPS (In-Plane-Switching, plane direction conversion) mode and AD-SDS (ADvancedSuperDimensionSwitch, advanced Ultra-dimensional field conversion technology, referred to as ADS) mode, etc.
其中，基于ADS模式的显示器通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹（pushMura）等优点。Among them, the display based on the ADS mode forms a multi-dimensional electric field through the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that everything between the slit electrodes in the liquid crystal cell and directly above the electrodes All aligned liquid crystal molecules can be rotated, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency. Advanced ultra-dimensional field conversion technology can improve the picture quality of TFT-LCD products, and has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, and no pushMura. .
如图1所示，现有技术的ADS模式的TFT-LCD阵列基板结构示意图，图1为俯视图；图2为图1的A-A面的断面结构示意图，可以更好地看到阵列基板内部结构，如图1和图2所示，其结构包括：衬底基板1，形成于衬底基板1之上的公共电极3（即板状电极）、公共电极线2以及扫描线12（包括栅极4），其中，公共电极线2与公共电极3电连接，还包括栅极绝缘层5，有源层7，数据线11（包括源极8、漏极9），钝化层6，多个像素电极10（即狭缝电极）。每一个阵列基板包括多条平行的扫描线12和与扫描线12垂直的多条平行的数据线11，由数据线11和扫描线12交叉形成的矩形区称为像素区，每一个像素区内有一个薄膜晶体管，一行薄膜晶体管设置有一条与这行的薄膜晶体管的栅极连接的扫描线。As shown in Figure 1, a schematic diagram of the structure of the TFT-LCD array substrate in the ADS mode of the prior art, Figure 1 is a top view; Figure 2 is a schematic diagram of the cross-sectional structure of the A-A surface of Figure 1, and the internal structure of the array substrate can be better seen, As shown in Figures 1 and 2, its structure includes: a base substrate 1, a common electrode 3 (that is, a plate electrode) formed on the base substrate 1, a common electrode line 2, and a scanning line 12 (including a gate 4 ), wherein the common electrode line 2 is electrically connected to the common electrode 3, and also includes a gate insulating layer 5, an active layer 7, a data line 11 (including a source electrode 8 and a drain electrode 9), a passivation layer 6, and a plurality of pixels Electrode 10 (ie slit electrode). Each array substrate includes a plurality of parallel scanning lines 12 and a plurality of parallel data lines 11 perpendicular to the scanning lines 12. The rectangular area formed by the intersection of the data lines 11 and the scanning lines 12 is called a pixel area. There is one thin film transistor, and a row of thin film transistors is provided with a scan line connected to the gates of the row of thin film transistors.
如图3所示，现有技术ADS模式的TFT-LCD液晶盒的结构示意图，即彩膜基板和阵列基板对盒的结构示意图，彩膜基板内的彩色滤光层21以彩色光阻作为滤光膜层覆盖于像素区，每个彩色滤光层可以透过红绿蓝三原色其中一种原色的光，而黑矩阵22需要覆盖在薄膜晶体管、扫描线12、数据线11及公共电极线2上以防各像素间漏光，并且能增加三原色的对比度。As shown in Figure 3, the structural diagram of the TFT-LCD liquid crystal cell in the ADS mode in the prior art, that is, the structural diagram of the color filter substrate and the array substrate paired box, the color filter layer 21 in the color filter substrate uses color photoresist as a filter The light film layer covers the pixel area, each color filter layer can transmit light of one of the three primary colors of red, green and blue, and the black matrix 22 needs to cover the thin film transistor, scanning line 12, data line 11 and common electrode line 2 To prevent light leakage between pixels, and increase the contrast of the three primary colors.
现有技术存在的缺陷在于，由于阵列基板上公共电极线的存在，彩膜基板上黑矩阵就要覆盖在公共电极线上方，导致面板的开口率和透过率较低。The disadvantage of the prior art is that due to the existence of the common electrode lines on the array substrate, the black matrix on the color filter substrate will cover the common electrode lines, resulting in low aperture ratio and transmittance of the panel.
发明内容Contents of the invention
本发明的目的是提供一种阵列基板、显示装置及阵列基板的制造方法，用以提高面板的开口率和透过率，进而提高面板的亮度。The object of the present invention is to provide an array substrate, a display device and a manufacturing method of the array substrate, which are used to increase the aperture ratio and transmittance of the panel, and further improve the brightness of the panel.
本发明阵列基板，包括衬底基板和阵列排布的多个薄膜晶体管，还包括：The array substrate of the present invention includes a base substrate and a plurality of thin film transistors arranged in an array, and further includes:
位于所述衬底基板上的公共电极线；a common electrode line located on the base substrate;
位于所述衬底基板上与所述公共电极线电连接的公共电极；A common electrode located on the base substrate and electrically connected to the common electrode line;
覆盖所述公共电极线、公共电极和衬底基板的绝缘层；an insulating layer covering the common electrode lines, the common electrodes and the base substrate;
所述多个薄膜晶体管位于所述绝缘层上，并且与每一行所述薄膜晶体管的栅极连接的扫描线位于所述公共电极线的上方。The plurality of thin film transistors are located on the insulating layer, and the scanning lines connected to the gates of each row of the thin film transistors are located above the common electrode lines.
优选的，所述公共电极位于所述公共电极线的两侧并与所述公共电极线电连接。Preferably, the common electrodes are located on both sides of the common electrode lines and are electrically connected to the common electrode lines.
优选的，所述绝缘层的材质为氮化硅。Preferably, the insulating layer is made of silicon nitride.
优选的，所述的阵列基板，还包括：Preferably, the array substrate further includes:
覆盖所述薄膜晶体管的钝化层；a passivation layer covering the thin film transistor;
位于所述钝化层上的多个像素电极，所述像素电极位于所述公共电极的上方。A plurality of pixel electrodes located on the passivation layer, the pixel electrodes located above the common electrode.
优选的，所述像素电极与所述公共电极的材质一致。Preferably, the material of the pixel electrode is the same as that of the common electrode.
优选的，所述公共电极的材质为氧化铟锡。Preferably, the common electrode is made of indium tin oxide.
本发明还涉及一种显示装置，包括上述任一种所述的阵列基板。The present invention also relates to a display device, comprising any one of the above-mentioned array substrates.
本发明还涉及一种阵列基板的制造方法，包括：The present invention also relates to a method for manufacturing an array substrate, comprising:
形成位于衬底基板之上的公共电极层，并通过掩膜构图工艺形成公共电极；forming a common electrode layer on the base substrate, and forming the common electrode through a mask patterning process;
在设定的扫描线位置形成位于所述衬底基板上的公共电极线；forming a common electrode line on the base substrate at a set scanning line position;
形成覆盖所述公共电极、公共电极线和衬底基板的绝缘层；forming an insulating layer covering the common electrode, the common electrode line and the base substrate;
在所述绝缘层上形成薄膜晶体管。A thin film transistor is formed on the insulating layer.
优选的，所述的阵列基板的制造方法，在所述绝缘层上形成薄膜晶体管之后，还包括：Preferably, the manufacturing method of the array substrate, after forming the thin film transistor on the insulating layer, further includes:
形成位于所述薄膜晶体管上的钝化层；forming a passivation layer on the thin film transistor;
形成位于所述钝化层之上，位于所述公共电极上方的多个像素电极。A plurality of pixel electrodes are formed on the passivation layer and on the common electrode.
优选的，在所述的阵列基板的制造方法中，所述绝缘层的材质为氮化硅。Preferably, in the manufacturing method of the array substrate, the insulating layer is made of silicon nitride.
在本发明阵列基板中，由于所述公共电极线位于扫描线的下方，并且扫描线与公共电极线间采用绝缘层进行绝缘，因此，彩膜基板的黑矩阵只覆盖至扫描线上方即可，因此黑矩阵的线宽可以相应减小，进而提高了面板开口率和透过率。此外，由于公共电极上方增加了一层绝缘层，因此，可以有效降低存储电容，从而减小像素的充电时间，也利于制作高解像度的产品。In the array substrate of the present invention, since the common electrode lines are located below the scanning lines, and an insulating layer is used to insulate the scanning lines from the common electrode lines, the black matrix of the color filter substrate only needs to cover the scanning lines. Therefore, the line width of the black matrix can be correspondingly reduced, thereby improving the panel aperture ratio and transmittance. In addition, since an insulating layer is added above the common electrode, the storage capacitance can be effectively reduced, thereby reducing the charging time of the pixel, and it is also beneficial to manufacture high-resolution products.
附图说明Description of drawings
图1为现有技术ADS模式的TFT-LCD阵列基板结构示意图；FIG. 1 is a schematic structural diagram of a TFT-LCD array substrate in an ADS mode in the prior art;
图2为图1的A-A面的断面结构示意图；Fig. 2 is the cross-sectional structure schematic diagram of A-A plane of Fig. 1;
图3为现有技术ADS模式的TFT-LCD液晶盒的结构示意图；Fig. 3 is the structural representation of the TFT-LCD liquid crystal box of prior art ADS mode;
图4为本发明阵列基板一实施例结构示意图；4 is a schematic structural diagram of an embodiment of an array substrate of the present invention;
图5为图4的B-B面的断面结构示意图；Fig. 5 is the cross-sectional structure schematic diagram of the B-B face of Fig. 4;
图6为本发明液晶盒的结构示意图；Fig. 6 is the structural representation of liquid crystal cell of the present invention;
图7为本发明阵列基板另一实施例结构示意图；7 is a schematic structural diagram of another embodiment of the array substrate of the present invention;
图8为本发明阵列基板的制造方法流程示意图。FIG. 8 is a schematic flowchart of a method for manufacturing an array substrate of the present invention.
附图标记：Reference signs:
1-衬底基板2-公共电极线3-公共电极4-栅极5-栅极绝缘层1-substrate substrate 2-common electrode line 3-common electrode 4-gate 5-gate insulating layer
6-钝化层7-有源层8-源极9-漏极10-像素电极11-数据线6-passivation layer 7-active layer 8-source 9-drain 10-pixel electrode 11-data line
12-扫描线13-绝缘层21-彩色滤光层22-黑矩阵12-scanning line 13-insulating layer 21-color filter layer 22-black matrix
具体实施方式detailed description
为了提高面板开口率，本发明提供了一种阵列基板、显示装置及阵列基板的制造方法。在该技术方案中，由于公共电极线位于扫描线的下方，因此，彩膜基板上的黑矩阵的线宽可以相应减小，进而提高了面板开口率和透过率，并且在扫描线和公共电极线之间采用绝缘层隔离，有效降低了存储电容，进而缩短了像素的充电时间。为使本发明的目的、技术方案和优点更加清楚，以下举具体实施例对本发明作进一步详细说明。In order to increase the panel aperture ratio, the present invention provides an array substrate, a display device and a manufacturing method of the array substrate. In this technical solution, since the common electrode lines are located below the scanning lines, the line width of the black matrix on the color filter substrate can be reduced correspondingly, thereby improving the panel aperture ratio and transmittance, and between the scanning lines and the common electrode lines. The electrode lines are separated by an insulating layer, which effectively reduces the storage capacitance, thereby shortening the charging time of the pixel. In order to make the purpose, technical solution and advantages of the present invention clearer, the following specific examples are given to further describe the present invention in detail.
如图4所示，本发明阵列基板一实施例结构示意图，图5为图4的B-B面的断面结构示意图，结合图4和图5所示，本发明阵列基板，包括衬底基板1和阵列排布的多个薄膜晶体管，还包括：As shown in Figure 4, the structure schematic diagram of an embodiment of the array substrate of the present invention, and Figure 5 is a schematic cross-sectional structure diagram of the B-B surface of Figure 4, combined with Figure 4 and Figure 5, the array substrate of the present invention includes the base substrate 1 and the array substrate A plurality of thin film transistors arranged also include:
位于衬底基板1上的公共电极线2；A common electrode line 2 located on the base substrate 1;
位于衬底基板1上与公共电极线2电连接的至少一个公共电极3；At least one common electrode 3 located on the base substrate 1 and electrically connected to the common electrode line 2;
覆盖公共电极线2、公共电极3和衬底基板1的绝缘层13；An insulating layer 13 covering the common electrode line 2, the common electrode 3 and the base substrate 1;
所述多个薄膜晶体管位于绝缘层13上，并且与每一行薄膜晶体管的栅极4连接的扫描线12位于公共电极线2的上方。The plurality of thin film transistors are located on the insulating layer 13 , and the scan line 12 connected to the gate 4 of each row of thin film transistors is located above the common electrode line 2 .
在本发明实施例中，由于公共电极线2位于扫描线12的下方，因此，如图6所示，本发明液晶盒结构示意图，对应的彩膜基板的黑矩阵22只需覆盖在扫描线12的上方，而现有技术中，如图1所示，扫描线12和公共电极线2平行排列，黑矩阵22需要覆盖在扫描线12和公共电极线2的上方，因此，采用本发明的技术方案，可以有效减小黑矩阵在扫描线方向的线宽（图6中的虚线部分为现有技术的黑矩阵的宽度，可见本发明的黑矩阵的线宽相应减少），提高了面板开口率和透过率，进而提高了面板的亮度。此外，公共电极3上增加了一层绝缘层13，因此，可以有效降低存储电容，进而减少像素的充电时间，利于高解像度面板的制造。In the embodiment of the present invention, since the common electrode line 2 is located below the scanning line 12, as shown in FIG. , while in the prior art, as shown in Figure 1, the scan lines 12 and the common electrode lines 2 are arranged in parallel, and the black matrix 22 needs to cover the scan lines 12 and the common electrode lines 2, therefore, the technology of the present invention is adopted solution, can effectively reduce the line width of the black matrix in the scanning line direction (the dotted line in Figure 6 is the width of the black matrix in the prior art, it can be seen that the line width of the black matrix of the present invention is correspondingly reduced), and the panel aperture ratio is improved. and transmittance, thereby improving the brightness of the panel. In addition, an insulating layer 13 is added on the common electrode 3 , so the storage capacitance can be effectively reduced, thereby reducing the charging time of the pixels, which is beneficial to the manufacture of high-resolution panels.
优选的，如图7所示，本发明阵列基板另一实施例的结构示意图，公共电极3位于公共电极线2的两侧并与公共电极线2电连接。Preferably, as shown in FIG. 7 , which is a schematic structural diagram of another embodiment of the array substrate of the present invention, the common electrodes 3 are located on both sides of the common electrode lines 2 and are electrically connected to the common electrode lines 2 .
在本发明实施例中，每一条公共电极线2可以与它两侧的公共电极3电连接，可以提高公共电极线2的利用率，并可以减少公共电极线2的制作个数。In the embodiment of the present invention, each common electrode line 2 can be electrically connected to the common electrodes 3 on both sides thereof, which can improve the utilization rate of the common electrode lines 2 and reduce the number of common electrode lines 2 produced.
优选的，如图5所示，绝缘层13的材质为氮化硅。Preferably, as shown in FIG. 5 , the insulating layer 13 is made of silicon nitride.
在本发明实施例中，绝缘层13的材质可以有多种选择，只要防止公共电极线2和扫描线绝缘即可，所以可以选用多种绝缘材料，优选氮化硅作为绝缘层13，具体可以采用化学气相沉积的方法形成绝缘层。In the embodiment of the present invention, the material of the insulating layer 13 can have multiple choices, as long as the common electrode line 2 and the scanning line are prevented from being insulated, so a variety of insulating materials can be selected, preferably silicon nitride is used as the insulating layer 13, specifically, it can be The insulating layer is formed by chemical vapor deposition.
优选的，如图5所示，本发明实施例的阵列基板，还包括：Preferably, as shown in FIG. 5, the array substrate of the embodiment of the present invention further includes:
覆盖薄膜晶体管的钝化层6；a passivation layer 6 covering the thin film transistor;
位于钝化层6上的多个像素电极10，像素电极10位于公共电极3的上方。A plurality of pixel electrodes 10 are located on the passivation layer 6 , and the pixel electrodes 10 are located above the common electrode 3 .
在本发明实施例中，像素电极10和公共电极3作为存储电容两个极板，两者之间的绝缘层13、栅极绝缘层5及钝化层6作为绝缘介质形成存储电容。如图5所示，所述阵列基板包括衬底基板1，在衬底基板1上的绝缘层13之上，可进一步包括：栅极4（扫描线的一部分）、栅极绝缘层5、有源层7等。所述薄膜晶体管可以为顶栅型，也可以为底栅型，如图5所示的底栅型薄膜晶体管形成的阵列基板，其结构具体为：扫描线层（扫描线层的扫描线在每一个像素区内包括栅极4）形成于绝缘层13之上，栅极绝缘层5形成于扫描线层之上，有源层7形成于栅极绝缘层5之上，数据线层形成于有源层7之上，钝化层6覆盖整个基板，像素电极形成于钝化层6之上，位于公共电极3的上方，并与公共电极3形成存储电容。In the embodiment of the present invention, the pixel electrode 10 and the common electrode 3 serve as two plates of the storage capacitor, and the insulating layer 13 , the gate insulating layer 5 and the passivation layer 6 between them serve as the insulating medium to form the storage capacitor. As shown in FIG. 5, the array substrate includes a base substrate 1, and on the insulating layer 13 on the base substrate 1, it may further include: a gate 4 (a part of the scanning line), a gate insulating layer 5, a source layer 7 etc. The thin-film transistor can be a top-gate type or a bottom-gate type. The array substrate formed by the bottom-gate type thin film transistor shown in FIG. A pixel area including gate 4) is formed on the insulating layer 13, the gate insulating layer 5 is formed on the scanning line layer, the active layer 7 is formed on the gate insulating layer 5, and the data line layer is formed on the active layer On the source layer 7 , the passivation layer 6 covers the entire substrate. The pixel electrode is formed on the passivation layer 6 , located above the common electrode 3 , and forms a storage capacitor with the common electrode 3 .
优选的，如图6所示，像素电极10与公共电极3的材质一致。Preferably, as shown in FIG. 6 , the pixel electrode 10 is made of the same material as the common electrode 3 .
在本发明实施例中，像素电极10和公共电极3作为存储电容的极板，可以选用同一材质的材料制成，优选为透明导电膜，由于公共电极3及其上方的像素电极10对应像素区，需要较高的光透过率，因此可以选用透明的导电膜作为其材质。In the embodiment of the present invention, the pixel electrode 10 and the common electrode 3 are used as the plates of the storage capacitor, and can be made of the same material, preferably a transparent conductive film. Since the common electrode 3 and the pixel electrode 10 above it correspond to the pixel area , requires a high light transmittance, so a transparent conductive film can be selected as its material.
优选的，公共电极3的材质为氧化铟锡。Preferably, the material of the common electrode 3 is indium tin oxide.
在本发明实施例中，像素电极10和公共电极3的材质都可以选用透明导电材料，优选氧化铟锡，因为氧化铟锡具有良好的透过率和导电性能，In the embodiment of the present invention, the material of the pixel electrode 10 and the common electrode 3 can be a transparent conductive material, preferably indium tin oxide, because indium tin oxide has good transmittance and conductivity,
本发明实施例还提供了一种显示装置，其包括上述任意一种阵列基板，所述显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。本发明的显示装置可以为TN模式、VA模式、IPS模式或ADS模式等。本发明的阵列基板形成的显示装置尤其适用于IPS模式和ADS模式。The embodiment of the present invention also provides a display device, which includes any of the above-mentioned array substrates, and the display device can be: liquid crystal panel, electronic paper, OLED panel, liquid crystal TV, liquid crystal display, digital photo frame, mobile phone, tablet computer and other products or parts with any display function. The display device of the present invention can be in TN mode, VA mode, IPS mode or ADS mode, etc. The display device formed by the array substrate of the present invention is especially suitable for IPS mode and ADS mode.
如图8所示，本发明还涉及一种阵列基板的制造方法，包括：As shown in FIG. 8, the present invention also relates to a method for manufacturing an array substrate, including:
步骤101、形成位于衬底基板之上的公共电极层，并通过掩膜构图工艺形成公共电极；Step 101, forming a common electrode layer on the base substrate, and forming the common electrode through a mask patterning process;
步骤102、在设定的扫描线位置形成位于所述衬底基板上的公共电极线；Step 102, forming a common electrode line on the base substrate at the set scanning line position;
步骤103、形成覆盖所述公共电极、公共电极线和衬底基板的绝缘层；Step 103, forming an insulating layer covering the common electrode, the common electrode line and the base substrate;
步骤104、在所述绝缘层上形成薄膜晶体管。Step 104, forming thin film transistors on the insulating layer.
在本发明实施例中，首先在阵列基板上形成公共电极，并在设定的扫描线的位置形成公共电极线，公共电极与公共电极线电连接，公共电极线可以提供给公共电极一个公共电压，在公共电极线的上方形成扫描线，这样就使得扫描线和公共电极线处于上下平行的状态，彩膜基板黑矩阵本应对应的公共电极线的宽度可以减少，因此，可以提高面板的开口率和透过率，进而提高面板的亮度。此外，公共电极线和扫描线之间需采用绝缘层将两者绝缘，因此，公共电极和像素电极间的绝缘介质的厚度增加，降低了存储电容，进而缩短了像素的充电时间，有利于高解像度产品的设计和制作。In the embodiment of the present invention, the common electrode is first formed on the array substrate, and the common electrode line is formed at the position of the set scanning line, the common electrode is electrically connected to the common electrode line, and the common electrode line can provide a common voltage to the common electrode , forming the scanning line above the common electrode line, so that the scanning line and the common electrode line are in a parallel state up and down, and the width of the common electrode line corresponding to the black matrix of the color filter substrate can be reduced, so the opening of the panel can be improved rate and transmittance, thereby improving the brightness of the panel. In addition, an insulating layer is used between the common electrode line and the scanning line to insulate the two. Therefore, the thickness of the insulating medium between the common electrode and the pixel electrode is increased, which reduces the storage capacitance, thereby shortening the charging time of the pixel, which is beneficial to high Design and production of resolution products.
优选的，所述的阵列基板的制造方法，在所述绝缘层上形成薄膜晶体管之后，还包括：Preferably, the manufacturing method of the array substrate, after forming the thin film transistor on the insulating layer, further includes:
形成位于所述薄膜晶体管上的钝化层；forming a passivation layer on the thin film transistor;
形成位于所述钝化层之上，位于所述公共电极上方的多个像素电极。A plurality of pixel electrodes are formed on the passivation layer and on the common electrode.
在本发明实施例中，薄膜晶体管的制作方法与现有技术一致，薄膜晶体管可以为底栅型，也可以为顶栅型的，只要将公共电极线设计在扫描线的下方即可，公共电极及其上方的多个像素电极形成存储电容，由于存储电容的绝缘介质的厚度增加，因此，存储电容有效降低，进而减少了像素的充电时间；钝化层的材质可以选为透明树脂材料，用于进一步提高透过率。In the embodiment of the present invention, the manufacturing method of the thin film transistor is consistent with the prior art, and the thin film transistor can be bottom gate type or top gate type, as long as the common electrode line is designed under the scanning line, the common electrode line and the multiple pixel electrodes above it form a storage capacitor. Since the thickness of the insulating medium of the storage capacitor increases, the storage capacitor is effectively reduced, thereby reducing the charging time of the pixel; the material of the passivation layer can be selected as a transparent resin material. to further increase the transmittance.
优选的，在所述的阵列基板的制造方法中，所述绝缘层的材质为氮化硅。Preferably, in the manufacturing method of the array substrate, the insulating layer is made of silicon nitride.
图5中所示实施例的阵列基板，其主要制作工艺流程如下：The main manufacturing process of the array substrate of the embodiment shown in FIG. 5 is as follows:
在衬底基板上形成一层公共电极层，可以优选采用溅射沉积的方法形成，公共电极层优选的材质为氧化铟锡，衬底基板选为玻璃基板，具体为通过溅射沉积在玻璃基板上沉积一层公共电极层，并通过第一次掩模构图工艺（掩模构图工艺通常包括清洗、成膜、涂布、曝光、显影、干刻或湿刻、光刻胶剥离等工序）形成公共电极；A common electrode layer is formed on the base substrate, which can preferably be formed by sputtering deposition. The preferred material of the common electrode layer is indium tin oxide, and the base substrate is selected as a glass substrate. Specifically, it is deposited on the glass substrate by sputtering. A common electrode layer is deposited on it, and formed by the first mask patterning process (the mask patterning process usually includes cleaning, film formation, coating, exposure, development, dry etching or wet etching, photoresist stripping, etc.) common electrode;
在衬底基板上设定的扫描线的位置形成公共电极线，具体为通过溅射沉积一层公共电极线层，并通过第二次掩膜构图工艺在扫描线对应的位置形成公共电极线阵列网格；Form the common electrode line at the position of the scanning line set on the base substrate, specifically, deposit a common electrode line layer by sputtering, and form a common electrode line array at the position corresponding to the scanning line through the second mask patterning process grid;
形成覆盖公共电极、公共电极线及衬底基板的绝缘层，优选的绝缘层的材质为氮化硅（SiNx），具体为通过化学气相沉积、曝光、刻蚀、剥离工艺，形成一层氮化硅绝缘层；Form an insulating layer covering the common electrodes, common electrode lines, and the base substrate. The preferred material of the insulating layer is silicon nitride (SiNx). Specifically, a layer of nitride is formed through chemical vapor deposition, exposure, etching, and stripping processes Silicon insulating layer;
按传统工艺，在绝缘层上形成扫描线（包括栅极），并按传统工艺依次形成覆盖扫描线的栅绝缘层、有源层、源漏电极层、钝化层及像素电极完成后续工艺从而完成整个阵列基板制作，其中，像素电极的材质可以优选为氧化铟锡，钝化层的材质可以优选为氮化硅。According to the traditional process, the scanning line (including the gate) is formed on the insulating layer, and the gate insulating layer, active layer, source-drain electrode layer, passivation layer and pixel electrode covering the scanning line are sequentially formed according to the traditional process to complete the subsequent process. The fabrication of the entire array substrate is completed, wherein the material of the pixel electrode may preferably be indium tin oxide, and the material of the passivation layer may preferably be silicon nitride.
可见，扫描线和公共电极线上下平行排列，使得黑矩阵的线宽减小，提高了面板的开口率和透过率，并且由于制作了一层绝缘层，因此增加了公共电极和像素电极间的绝缘介质的厚度，有效降低了存储电容，进而缩短了像素的充电时间。It can be seen that the scanning lines and the common electrode lines are arranged in parallel up and down, so that the line width of the black matrix is reduced, the aperture ratio and transmittance of the panel are improved, and because an insulating layer is made, the distance between the common electrode and the pixel electrode is increased. The thickness of the insulating medium effectively reduces the storage capacitance, thereby shortening the charging time of the pixel.
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.
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| CN201310110333.5ACN103278986B (en) | 2013-04-01 | 2013-04-01 | The manufacture method of a kind of array base palte, display device and array base palte |
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| CN201310110333.5ACN103278986B (en) | 2013-04-01 | 2013-04-01 | The manufacture method of a kind of array base palte, display device and array base palte |
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| CN201310110333.5AActiveCN103278986B (en) | 2013-04-01 | 2013-04-01 | The manufacture method of a kind of array base palte, display device and array base palte |
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