CN103258824A - Memory cell of flash memory and forming method - Google Patents

Abstract

The invention discloses a memory cell of a flash memory and a forming method. The memory cell of the flash memory comprises a semiconductor substrate, an isolating layer, a base layer selecting grid, a base layer dielectric layer, control grid layers, a memory plugging array and a plurality of polycrystalline silicon layers. The semiconductor substrate comprises an array area and step areas and the step areas are arranged at two sides of the array area. The isolating layer, the base layer selecting grid and the base layer dielectric layer are sequentially arranged on the surface of the semiconductor substrate. The control grid layers are arranged on the surface of the base layer dielectric layer. The control grid layers further comprises a plurality of polycrystalline silicon layers and a plurality of interlayer dielectric layers arranged on the surfaces of the polycrystalline silicon layers. The memory plugging array penetrates through the control grid layers of the array area in a thickness direction. The polycrystalline silicon layers are arranged in the control grid layers of the step areas and form a ladder layer by layer from the lowermost layer to the topmost layer in a decreasing mode. Projections of steps of all levels of the ladder on the semiconductor substrate are arranged in the shape of a line, and the line is parallel to the boundaries of the array area and the step areas. According to the memory cell of the flash memory, bit density of the flash memory is improved, and cost is reduced.

Description

The memory cell of flash memory and formation method

Technical field

The present invention relates to semiconductor device and forming method thereof, particularly a kind of memory cell of flash memory and formation method.

Background technology

In recent years, the development of flash memory (flash memory) is particularly rapid.The main feature of flash memory is can keep canned data for a long time under situation about not powering up; And have integrated level height, access speed fast, be easy to wipe and advantage such as rewriting, thereby obtained using widely in multinomial fields such as microcomputer, automation controls.

In order further to improve flash memory bit density (bit density), reduce position cost (bit cost) simultaneously, a kind of low-cost three-dimensional multilayer structure (Bit-Cost Scalable of flash memory, abbreviation BiCS) technology has obtained further development, please refer to Fig. 1, cross-sectional view for the memory cell of existing flash memory BiCS structure comprises:

Semiconductor substrate 100, describedSemiconductor substrate 100 comprisesarray area 101 and steppedregion 102, describedstepped region 102 is inarray area 101 both sides; Be positioned at theseparator 103 on describedSemiconductor substrate 100 surfaces; The bottom that is positioned atseparator 103 surfaces is selected grid 104; Be positioned at bottom and select the bottom dielectric layer 105 on grid 104 surfaces, run through theseparator 103 of describedarray area 101, the bottom selectiongrid connector array 106 that bottom is selected grid 104 and bottom dielectric layer 105 thickness;

Be positioned at described bottom dielectric layer 105 and bottom and select thecontrol grid layer 107 ongrid connector array 106 surfaces, described control grid layer also comprises: some layers ofpolysilicon layer 121, and the interlayer dielectric layer 122 of eachlayer polysilicon layer 121 surface coverage; Thememory connector array 108 that runs throughcontrol grid layer 107 thickness of describedarray area 101 selectsconnector array 106 corresponding one by one with bottom;

The top layer that is positioned atcontrol grid layer 107 surfaces of describedarray area 101 is selected grid 109, be positioned at described top layer and select the top layerdielectric layer 110 on grid 109 surfaces, be positioned at the bit line 111 on described top layerdielectric layer 110 surfaces, run through described top layerdielectric layer 110 and top layer and select the top layer of grid 109 thickness to selectconnector array 112, and corresponding one by one withmemory connector array 108;

Be positioned at the insulating barrier 114 oncontrol grid layer 107 surfaces of describedstepped region 102, be positioned at some connecting lines 113 on described insulating barrier 114 surfaces; The someattachment plugs 115 that run through described insulating barrier 114 thickness, described someattachment plugs 115 are connected the some layers ofpolysilicon layer 121 in some connecting lines 113 and thecontrol grid layer 107 respectively.

Please refer to Fig. 2, Fig. 2 is that Fig. 1 is along AA ' direction, the vertical view of ignoring insulating barrier 114 and interlayer dielectric layer 122 (please refer to Fig. 1),polysilicon layer 121 in thecontrol grid layer 107 of described stepped region, position by next-door neighbour's array area successively increases progressively same size to the outside away fromarray area 101 by the superiors' polysilicon layer to orlop polysilicon layer, forms stepped; The projection of described attachment plug 115 onSemiconductor substrate 100, the boundary oblique that joins with respect toarray area 101 and steppedregion 102.

In being the U.S. patent documents of US 2011/0073935A1, publication number can also find memory cell of more flash memory and forming method thereof.

Yet, there is the space waste in the BiCS structure of existing flash memory, caused the bit density of flash memory to reduce, it is big that the volume of flush memory device becomes, the also corresponding reduction of position cost, institute's rheme cost is the needed manufacturing cost of every manufacturing a data position memory space in the manufacturing process of memory device, is the feature that embodies the memory device cost.

Summary of the invention

The problem that the present invention solves is the area that reduces the flash memory control grid layer, thereby improves the bit density of flash memory, reduces the position cost of flash memory.

For addressing the above problem, the embodiment of the invention provides a kind of memory cell of flash memory, comprising:

Semiconductor substrate, described Semiconductor substrate comprises array area and stepped region, described stepped region is in the array area both sides; Be positioned at the separator of semiconductor substrate surface; The bottom that is positioned at insulation surface is selected grid; Be positioned at bottom and select the bottom dielectric layer on grid surface;

Run through the separator of described array area, the bottom selection grid connector array that bottom is selected grid and bottom thickness of dielectric layers;

Be positioned at described bottom dielectric layer and bottom and select the control grid layer of grid connector array surface, described control grid layer also comprises: some layers of polysilicon layer and be positioned at the interlayer dielectric layer on each layer polysilicon layer surface, wherein, the memory connector array that runs through the control grid layer thickness of described array area, and described memory connector array selects the connector array corresponding one by one with bottom;

Be positioned at the size of some layers of polysilicon layer of the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region;

Be positioned at the insulating barrier on the control grid layer surface of described stepped region, be positioned at some connecting lines of described surface of insulating layer, described some connecting lines some attachment plugs by running through described thickness of insulating layer respectively are connected respectively with some layers of polysilicon layer in the control grid layer, the projection of described some attachment plugs on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region.

Optionally, also comprise: the some top layers that are positioned at the control grid layer surface of described array area are selected grid; Be positioned at some top layers and select the top layer dielectric layer on grid surface; Be positioned at some bit lines on top layer dielectric layer surface; Run through described top layer dielectric layer and top layer and select the top layer of grid thickness to select the connector array, described top layer selects the connector array corresponding one by one with memory connector array, and is connected with bit line.

Optionally, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.

Optionally, the described insulation material layer multiple-level stack that is silicon oxide layer, silicon nitride layer or silica and silicon nitride.

Optionally, the size of some layers of polysilicon layer in the control grid layer of described stepped region, the polysilicon layer from the polysilicon layer of the bottom to top layer successively successively decreases, and each layer polysilicon layer measure-alike with following one deck polysilicon layer minimizing relatively.

Optionally, described separator comprises oxide layer, catches charge layer and barrier oxide layer, and the described charge layer of catching is positioned at described oxide layer surface, and described barrier oxide layer is positioned at the described charge layer surface of catching.

Optionally, the material of described oxide layer is silica, and described material of catching charge layer is silicon nitride, material oxidation silicon or the aluminium oxide of described barrier oxide layer.

The embodiment of the invention also provides a kind of formation method of memory cell of flash memory, comprising:

Semiconductor substrate is provided, and semiconductor substrate surface has separator successively, bottom is selected grid, bottom dielectric layer and control grid layer, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is positioned at the array area both sides; Run through the separator of described array area, the bottom selection grid connector array that bottom is selected grid and bottom thickness of dielectric layers; Described control grid layer comprises: some layers of polysilicon layer and be positioned at the interlayer dielectric layer on each layer polysilicon layer surface, wherein, run through the memory connector array of the control grid layer thickness of described array area, and described memory connector array is corresponding one by one with bottom selection connector array;

Form hard mask layer on the control grid layer surface;

Forming first photoresist layer on described hard mask layer surface, is that mask is removed array area and stepped region control grid layer and hard mask layer in addition with first photoresist layer;

Remove first photoresist layer of stepped region and hard mask layer till exposing first interlayer dielectric layer, described first interlayer dielectric layer is the interlayer dielectric layer of top layer in the control grid layer, removes first photoresist layer of array area;

Form second photoresist layer at hard mask layer and first interlayer dielectric layer surface;

Etching interlayer dielectric layer and polysilicon layer and the attenuate second photoresist layer several times repeatedly, make the size of some layers of polysilicon layer in the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases from the bottom to top, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region;

Control grid layer surface in stepped region forms insulating barrier, forms the some attachment plugs that run through described thickness of insulating layer, is connected with some layers of polysilicon layer respectively;

Form some connecting lines at insulating barrier and attachment plug surface, described some connecting lines are connected with some polysilicon layers by some attachment plugs respectively.

Optionally, also comprise step: form some top layers on the control grid layer surface of array area and select grid, select the grid surface to form the top layer dielectric layer at some top layers; Formation runs through described top selects the top layer of grid and top layer thickness of dielectric layers to select the connector array, and described top layer selects the connector array corresponding one by one with memory connector array; Form some bit lines on described top layer dielectric layer surface, described bit line selects the connector array to be connected with top layer.

Optionally, described at hard mask layer and first interlayer dielectric layer surface formation, second photoresist layer, and the method for etching interlayer dielectric layer and polysilicon layer and the attenuate second photoresist layer several times repeatedly, also comprise step: form second photoresist layer at hard mask layer and first interlayer dielectric layer surface, and exposing the interior first step district of stepped region, described first step district is bottom step The corresponding area in the stepped region; Be mask with second photoresist layer and hard mask layer, etching first interlayer dielectric layer and first polysilicon layer, and expose second interlayer dielectric layer, described first polysilicon layer is the polysilicon layer of top layer in the control grid layer, and described second interlayer dielectric layer is the interlayer dielectric layer of one deck under first interlayer dielectric layer; Attenuate second photoresist layer also exposes the second step district of first interlayer dielectric layer in the stepped region, and described second step district is corresponding zone on upper level step place first interlayer dielectric layer of bottom step; Be mask with second photoresist layer and hard mask layer, at second step district etching first interlayer dielectric layer and first polysilicon layer, at first step district etching second interlayer dielectric layer and second polysilicon layer, described second polysilicon layer is the polysilicon layer of one deck under first polysilicon layer; Attenuate second photoresist layer also exposes the 3rd stepped region of first interlayer dielectric layer, and described the 3rd stepped region is zone corresponding on first interlayer dielectric layer of upper level step place, second step district.

Optionally, the technology of described attenuate photoresist is dry etching.

Optionally, the technology of described etching interlayer dielectric layer and polysilicon layer is the reactive ion etching method.

Optionally, described interlayer dielectric layer is 1～50 for the etching selection ratio of hard mask layer, and described polysilicon layer is 5～200 for the etching selection ratio of hard mask layer.

Optionally, described hard mask layer is that in insulation material layer, metal level or the amorphous carbon layer one or more overlap.

Optionally, the described insulation material layer multiple-level stack that is silicon oxide layer, silicon nitride layer or silica and silicon nitride.

Optionally, the material of described metal level is one or more the alloy in copper, tungsten, the aluminium.

Optionally, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.

Optionally, the described insulation material layer multiple-level stack that is silicon oxide layer, silicon nitride layer or silica and silicon nitride.

Optionally, the material of described hard mask layer and interlayer dielectric layer is inequality.

Optionally, the size of some layers of polysilicon layer in the control grid layer of described stepped region, the polysilicon layer from the polysilicon layer of the bottom to top layer successively successively decreases, and each layer polysilicon layer measure-alike with following one deck polysilicon layer minimizing relatively.

Optionally, described separator successively by oxide layer, catch charge layer and barrier oxide layer and pile up and constitute;

Optionally, the material of described oxide layer is silica, and described material of catching charge layer is silicon nitride, material oxidation silicon or the aluminium oxide of described barrier oxide layer.

Compared with prior art, the embodiment of the invention has the following advantages:

The memory cell of the flash memory that embodiments of the invention provide, in the stacked structure that does not change some layers of polysilicon layer in the control grid layer in the prior art, some layers of polysilicon layer in the control grid layer on stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and it is described linear parallel with the contacted sideline of array area and stepped region, can solve in the BiCS structure of existing control grid layer the space waste problem of control grid layer on the stepped region of Semiconductor substrate.Make in the polysilicon layer multiple-level stack structure in keeping control grid layer, reduced the area of control grid layer, thereby improved the bit density of flash memory, and reduced the position cost of flash memory.

The memory cell formation method of the flash memory that embodiments of the invention provide, by attenuate second photoresist layer and etching interlayer dielectric layer and polysilicon layer repeatedly, make the polysilicon layer in the control grid layer form step-like in stepped region, described formation method can be with less processing step, accurate formation is step-like, it is easy to have technology, the advantage that the moulding accuracy is high.

Description of drawings

Fig. 1 is the cross-sectional view of the memory cell of existing flash memory BiCS structure;

Fig. 2 is the vertical view of ignoring insulating barrier and interlayer dielectric layer for Fig. 1 along AA ' direction;

Fig. 3 is the process chart of formation method of memory cell of the flash memory of the embodiment of the invention;

Fig. 4 to Figure 18 is the structural representation of formation method of memory cell of the flash memory of the embodiment of the invention;

Figure 19 be Figure 17 along CC ' direction, ignore the vertical view of some interlayer dielectric layers in insulating barrier, memory connector array and the control grid layer;

Figure 20 is the equivalent circuit diagram of memory cell of the flash memory of the embodiment of the invention.

Embodiment

The inventor finds, in the BiCS structure of existing flash memory, some layers of polysilicon layer in the control grid layer of flash memory are on the Semiconductor substrate stepped region, by next-door neighbour array area the position from top to bottom successively increase progressively to the outside away from array area form stepped, and caused the space of the memory cell of flash memory to waste, and then increased the area of memory cell, thus reduced the bit density of flash memory, increased the position cost of flash memory.

For the area of the memory cell that reduces flash memory, thereby improve the bit density of flash memory, reduce the position cost of flash memory, the inventor provides a kind of memory cell of flash memory, comprising:

Semiconductor substrate, described Semiconductor substrate comprises array area and stepped region, described stepped region is in the array area both sides; Be positioned at the separator of semiconductor substrate surface; The bottom that is positioned at insulation surface is selected grid; Be positioned at bottom and select the bottom dielectric layer on grid surface; Run through the separator of described array area, the bottom selection grid connector array that bottom is selected grid and bottom thickness of dielectric layers; Be positioned at described bottom dielectric layer and bottom and select the control grid layer of grid connector array surface, described control grid layer also comprises: some layers of polysilicon layer and be positioned at some interlayer dielectric layers on each layer polysilicon layer surface; Wherein, run through the memory connector array of the control grid layer thickness of described array area, and described memory connector array selects the connector array corresponding one by one with bottom; Be positioned at some layers of polysilicon layer of the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region; Be positioned at the insulating barrier on the control grid layer surface of described stepped region, be positioned at some connecting lines of described surface of insulating layer, described some connecting lines some attachment plugs by running through described thickness of insulating layer respectively are connected respectively with some layers of polysilicon layer in the control grid layer, the projection of described some attachment plugs on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted sideline of array area and stepped region;

The some top layers that are positioned at the control grid layer surface of described array area are selected grid; Be positioned at some top layers and select the top layer dielectric layer on grid surface; Be positioned at some bit lines on top layer dielectric layer surface; Run through described top layer dielectric layer and top layer and select the top layer of grid thickness to select the connector array, described top layer selects the connector array corresponding one by one with memory connector array, and is connected with bit line.

The memory cell of the flash memory that the inventor provides, in the stacked structure that does not change some layers of polysilicon layer of the control grid layer of flash memory in the prior art, by making some layers of polysilicon layer in the control grid layer on the Semiconductor substrate stepped region, on the direction of the same row that are close to the Semiconductor substrate array area, successively successively decreased by orlop to the superiors, form stair-stepping method, in the BiCS structure that solves existing control grid layer, some layers of polysilicon layer in the control grid layer successively increase progressively same size by the position of next-door neighbour's array area from top to bottom to the outside away from array area, form stepped and waste problem in space that cause, make in the polysilicon layer multiple-level stack structure in keeping control grid layer, reduced the area of the memory cell of flash memory, thereby improved the bit density of flash memory, and reduced the position cost of flash memory.

In order to form the memory cell of described flash memory, the inventor also provides a kind of formation method of memory cell of flash memory, is elaborated below with reference to specific embodiment, please refer to Fig. 3, and the formation method of the memory cell of flash memory comprises step:

Step S101 provides Semiconductor substrate, and semiconductor substrate surface has separator successively, bottom is selected grid, bottom dielectric layer and control grid layer, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is positioned at the array area both sides; Run through the separator of described array area, the bottom selection grid connector array that bottom is selected grid and bottom thickness of dielectric layers; Described control grid layer comprises: some layers of polysilicon layer and be positioned at the interlayer dielectric layer on each layer polysilicon layer surface, wherein, run through the memory connector array of the control grid layer thickness of described array area, and described memory connector array is corresponding one by one with bottom selection connector array.

Step S102 forms hard mask layer on the control grid layer surface.

Step S103 forms first photoresist layer on described hard mask layer surface, is that mask is removed array area and stepped region control grid layer and hard mask layer in addition with first photoresist layer.

Step S104 removes first photoresist layer of stepped region and hard mask layer till exposing first interlayer dielectric layer, and described first interlayer dielectric layer is the interlayer dielectric layer of top layer in the control grid layer, removes first photoresist layer of array area.

Step S105 forms second photoresist layer at hard mask layer and first interlayer dielectric layer surface.

Step S106, etching interlayer dielectric layer and polysilicon layer repeatedly, and the attenuate second photoresist layer several times, make the size of some layers of polysilicon layer in the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases from the bottom to top, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region.

Step S107 forms insulating barrier on the control grid layer surface of stepped region, forms the attachment plug that runs through described thickness of insulating layer, is connected respectively with some layers of polysilicon layer respectively.

Step S108 forms some connecting lines at insulating barrier and attachment plug surface, and described some connecting lines are connected with some polysilicon layers by some attachment plugs respectively.

The memory cell formation method of the flash memory that embodiments of the invention provide, by attenuate second photoresist layer and etching interlayer dielectric layer and polysilicon layer repeatedly, make the polysilicon layer in the control grid layer form step-like in stepped region, described formation method can be with less processing step, accurate formation is step-like, it is easy to have technology, the advantage that the moulding accuracy is high.

Fig. 4 to Figure 18 is the structural representation of formation method of the memory cell of embodiment of the invention flash memory.

Please refer to Fig. 4,Semiconductor substrate 200 is provided, describedSemiconductor substrate 200 comprisesarray area 201 and steppedregion 202, described steppedregion 202 is inarray area 201 both sides,Semiconductor substrate 200 surfaces haveseparator 210,separator 210 surfaces have bottom andselect grid 220, bottom selectsgrid 220 surfaces to have bottomdielectric layer 221,bottom dielectric layer 221 surfaces havecontrol grid layer 230, theseparator 210 that runs through describedarray area 201, bottom selects the bottom of the thickness ofgrid 220 andbottom dielectric layer 221 to selectconnector array 222, describedcontrol grid layer 230 also comprises: the interlayer dielectric layer (not shown) of some layers of polysilicon layer (not shown) and each polysilicon layer surface coverage, wherein, thememory connector array 231 of thickness that runs through thecontrol grid layer 230 of describedarray area 201, describedmemory connector array 231 selectsconnector array 222 corresponding one by one with bottom.

The material of describedSemiconductor substrate 200 is silicon or silicon-on-insulator, and effect is to provide workbench for subsequent technique.

Describedseparator 210 successively byoxide layer 211,catch charge layer 212 andbarrier oxide layer 213 and pile up and constitute, the material of describedoxide layer 211 is silica, described material of catchingcharge layer 212 is silicon nitride, material oxidation silicon or the aluminium oxide of describedbarrier oxide layer 213.

Wherein, described effect of catchingcharge layer 212 is store electrons, has replaced the effect of the floating boom in the existing technology, can further reduce the size of memory cell.

It is polysilicon that described bottom is selected the material ofgrid 220, the material of described bottomdielectric layer 221 is silicon nitride, the material of the interlayer dielectric layer in the describedcontrol grid layer 230 is insulating material or amorphous carbon, and described insulating material is the multiple-level stack of silica, silicon nitride or silica and silicon nitride.

It is sedimentation that describedseparator 210, bottom are selected the formation technology ofgrid 220 andbottom dielectric layer 221, and preferably chemical vapour deposition technique formsseparator 210,bottom selection grid 220 andbottom dielectric layer 221 atSemiconductor substrate 200 surface depositions successively.

Bottom selects the formation technology ofgrid connector array 222 to be: atbottom dielectric layer 221 surface-coated photoresists and graphical, be mask etchingbottom dielectric layer 221 with the photoresist, bottom selectsgrid 220 andseparator 210 to form some openings until exposingSemiconductor substrate 200, dry etching preferably, sidewall at described opening forms silicon oxide layer and exposesSemiconductor substrate 200, the technology that forms described silicon oxide layer can be chemical vapour deposition technique, fill on theSemiconductor substrate 200 of open bottom and silicon oxide layer surface polysilicon until withbottom dielectric layer 221 flush, form bottom and selectgrid connector array 222.

Select the surface ofgrid connector array 222 to formcontrol grid layer 230 at described bottomdielectric layer 221 and bottom, the formation technology of describedcontrol grid layer 230 is: at the surface deposition polysilicon layer ofbottom dielectric layer 221 and bottom selectiongrid connector array 222, form interlayer dielectric layer at described polysilicon layer surface deposition, the material of described interlayer dielectric layer is insulating material or amorphous carbon, described insulating material is silica, silicon nitride, silicon oxynitride, continue deposit spathic silicon layer and interlayer dielectric layer several times successively at described inter-level dielectric laminar surface, formcontrol grid layer 230.

The formation technology of describedmemory connector array 231 is: atcontrol grid layer 230 surface-coated photoresists and graphical, be that some polysilicon layers and interlayer dielectric layers in the mask etchingcontrol grid layer 230 form the opening that runs throughcontrol grid layer 230 thickness with the photoresist, sidewall at described opening forms silicon nitride layer and exposes bottom selectiongrid connector array 222 surfaces, bottom in opening select to fill ingrid connector array 222 and the silicon nitride layer surface polysilicon until withcontrol grid layer 230 flush, formmemory connector array 231.

Please refer to Fig. 5, formhard mask layer 240 oncontrol grid layer 230 surfaces, formfirst photoresist layer 241 on describedhard mask layer 240 surfaces, be that mask is removedcontrol grid layer 230 and thehard mask layer 240 beyondarray area 201 and the steppedregion 202 withfirst photoresist layer 241, andseparator 210, bottom are selectedgrid 220 andbottom dielectric layer 221.

Describedhard mask layer 240 is by insulating material, in metal or the amorphous carbon one or more overlap, described insulating material is silica, the multiple-level stack of silicon nitride or silica and silicon nitride, metal is copper, tungsten, the alloy of one or more in the aluminium, the material of the interlayer dielectric layer in the material ofhard mask layer 240 and thecontrol grid layer 230 is different, formation technology is sedimentation, chemical vapour deposition technique preferably, describedhard mask layer 240 is different with the material of interlayer dielectric layer, can be used for the mask as subsequent etching interlayer dielectric layer and polysilicon layer, do not react with etching gas.

Apply photoresist and image conversion, formfirst photoresist layer 241, describedfirst photoresist layer 241 coversarray area 201 and steppedregion 202 correspondence positions ofhard mask layer 240, be mask withfirst photoresist layer 241,select grid 220 andbottom dielectric layer 221 byhard mask layer 240,control grid layer 230,separator 210, bottoms that etching is removed outsidearray area 201 and the steppedregion 202, described etching technics is dry etching or wet etching.

Please refer to Fig. 6, removefirst photoresist layer 241 of steppedregion 202 andhard mask layer 240 till exposing firstinterlayer dielectric layer 232, described firstinterlayer dielectric layer 232 is the interlayer dielectric layer of top layer in thecontrol grid layer 230.

Removefirst photoresist layer 241 of steppedregion 202 by dry etching, described etching gas is one or more in nitrogen, oxygen, fluorocarbon gases and the hydrocarbon gas, be mask withfirst photoresist layer 241, dry etching or wet etching are removed thehard mask layer 240 of steppedregion 202, until exposinginterlayer dielectric layer 232.

Please refer to Fig. 7 and Fig. 8, Fig. 8 is the end view of Fig. 7 on BB ' direction, remove first photoresist layer 241 (please refer to Fig. 6) ofarray area 201, formsecond photoresist layer 242 athard mask layer 240 and first interlayer dielectric layer, 232 surfaces, and exposingfirst step district 203 in the steppedregion 202, describedfirst step district 203 is the bottom step The corresponding area of formed ladder in the steppedregion 202 inherent subsequent techniques.

The technology of removingfirst photoresist layer 241 is dry etching or wet etching, athard mask layer 240 and first interlayer dielectric layer, 232 surface-coated photoresists and graphical, expose thehard mask layer 240 of the foldedarray area 201 infirst step district 203 andfirst step district 203.

Please refer to Fig. 9 and Figure 10, Figure 10 is the end view of Fig. 9 on BB ' direction, be mask withsecond photoresist layer 242 withhard mask layer 240, etching firstinterlayer dielectric layer 232 andfirst polysilicon layer 233, and expose secondinterlayer dielectric layer 234, describedfirst polysilicon layer 233 is the polysilicon layer of top layer in thecontrol grid layer 230, and described secondinterlayer dielectric layer 234 is the interlayer dielectric layer of 232 times one decks of first interlayer dielectric layer.

Described etching technics is the reactive ion etching method, the advantage that reactive ion is sent out is that anisotropy and selectivity are good, can form smooth step, not damagehard mask layer 240 andsecond photoresist layer 242 simultaneously, the etching gas of etchingfirst polysilicon layer 233 is Cl₂, HBr or Cl₂Mist with HBr, because firstinterlayer dielectric layer 232 is different with the material ofhard mask layer 240, therefore firstinterlayer dielectric layer 232 andfirst polysilicon layer 233 have selectivity respectively forhard mask layer 240, polysilicon layer is 5～200 for the etching selection ratio ofhard mask layer 240, interlayer dielectric layer is 1～50 for the etching selection ratio ofhard mask layer 240, when so then can thoroughly remove firstinterlayer dielectric layer 232 andfirst polysilicon layer 233,hard mask layer 240 there is not influence.

Please refer to Fig. 9 and Figure 11, Figure 11 is the end view of Fig. 9 on BB ' direction, attenuatesecond photoresist layer 242 also exposes thesecond step district 204 of first interlayerdielectric layers 232 in the steppedregion 202, and describedsecond step district 204 be the zone of correspondence on firstinterlayer dielectric layer 232 of 203 upper level step places, first step district.

Described attenuatesecond photoresist layer 242 technologies are dry etching, dry etching can makesecond photoresist layer 242 accurately be thinned to exposesecond step district 204, and the gas of described dry etching is one or more mixing in inert gas, nitrogen, oxygen, fluorocarbon gases and the hydrocarbon gas.

Please refer to Figure 12 and Figure 13, Figure 13 is the end view of Figure 12 on BB ' direction, be mask withsecond photoresist layer 242 with hard mask layer 240,204 etchings, firstinterlayer dielectric layer 232 andfirst polysilicon layer 233 in the second step district, 203 etchings, secondinterlayer dielectric layer 234 andsecond polysilicon layer 235 in the first step district, describedsecond polysilicon layer 235 is the polysilicon layer of 233 times one decks of first polysilicon layer.

Described etching technics is the reactive ion etching method, and the technology of concrete reactive ion etching method is consistent with present embodiment Fig. 9 and Figure 10, and is well known to those skilled in the art, and does not give unnecessary details at this.

Please refer to Figure 12 and Figure 14, Figure 14 is the end view of Figure 12 on BB ' direction, attenuatesecond photoresist layer 242 also exposes the 3rd steppedregion 205 of firstinterlayer dielectric layer 234, and described the 3rd steppedregion 205 is zone corresponding on firstinterlayer dielectric layer 232 of 204 upper level step places, second step district.

The technology of described attenuatesecond photoresist layer 242 is described consistent with present embodiment Fig. 9 and Figure 11, and is well known to those skilled in the art, and does not give unnecessary details at this.

Please refer to Figure 15 and Figure 16, Figure 16 is the end view of Figure 15 on BB ' direction, state etching interlayer dielectric layer and polysilicon layer repeatedly, and attenuate second photoresist layer 242 (the please refer to Figure 14) several times, make the size of some layers of polysilicon layer in thecontrol grid layer 230 of steppedregion 202, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases from the bottom to top, the projection of the steps at different levels of described ladder onSemiconductor substrate 200 arranged and is linear, and described linear parallel with steppedregion 202 contacted borders witharray area 201.

The technology of etching interlayer dielectric layer and polysilicon layer is the reactive ion etching method, every removal one deck interlayer dielectric layer and one deck polysilicon layer, then withsecond photoresist layer 242 of dry etching attenuate certain size, several times are removed fully untilsecond photoresist layer 242 repeatedly, and the polysilicon layer formed ladder in steppedregion 202 in thecontrol grid layer 230, each layer step is measure-alike with respect to following one deck step minimizing.

Please refer to Figure 17 and Figure 18, Figure 18 is the end view of Figure 17 on BB ' direction, remove hard mask layer 240 (please refer to Figure 15),control grid layer 230 surfaces in steppedregion 202form insulating barrier 250, forming the some attachment plugs 251 that run through its thickness in described insulatingbarrier 250 is connected respectively with some layers of polysilicon layer, form some connectinglines 252 at insulatingbarrier 250 and attachment plug 251 surfaces, described someconnecting lines 252select grid 220 to be connected respectively byattachment plug 251 with some polysilicon layers and bottom.

The technology of described removalhard mask layer 240 is dry etching or wet etching.

The material of described insulatingbarrier 250 is silica or silicon nitride, and the material of describedarticulamentum 252 is polysilicon, and the formation technology of insulatingbarrier 250 andarticulamentum 252 is sedimentation, preferably chemical vapour deposition technique.

The formation technology of describedattachment plug 251 is: at described insulatingbarrier 250 surface-coated photoresists, and exposure imaging is graphical, be mask etching insulatingbarrier 250 with the photoresist, form the opening of some attachment plugs 251, and expose the surface of the polysilicon layer that eachattachment plug 251 connects, in described opening, fill polysilicon,form attachment plug 251.

Further, please refer to Figure 17, the formation method in the memory cell of flash memory also comprises step: form some top layers oncontrol grid layer 230 surfaces ofarray area 201 andselect grid 260,select grid 260 surfaces to form top layerdielectric layers 261 at described top layer; Formation runs through top layer selects the top layer ofgrid 260 and toplayer dielectric layer 261 thickness to selectconnector array 262, and described top layer selectsconnector array 262 corresponding one by one withmemory connector array 231; Form somebit lines 263 on described toplayer dielectric layer 261 surfaces, describedbit line 263 selectsconnector array 262 to be connected with top layer.

Described some top layers are selectedgrid 260, connect the connector in the same row's top layerselection connector array 262 on the first direction, material is polysilicon, forming technology is to form top layer atcontrol grid layer 230 surface depositions to select grid layer (not shown), select the grid laminar surface to apply photoresist at described top layer, and exposure imaging is graphical, selects the grid layer with photoresist as the mask etching top layer, forms top layer and selectsgrid 260.

Select grid 260 surface deposition top layerdielectric layers 261 at top layer, the material of described toplayer dielectric layer 261 is silica or silicon nitride, described toplayer dielectric layer 261 surfaces and insulatingbarrier 250 flush.

Described top layer selects the formation technology ofconnector array 262 to select the formation technology ofconnector array 222 consistent with the described bottom of Fig. 4, and is well known to those skilled in the art, and does not give unnecessary details at this.

Same row's top layer on described somebit lines 263 connection second directions is selected the connector in theconnector array 262, described second direction and first direction are perpendicular, the flush ofbit line 263 surfaces andarticulamentum 252, it is identical with the technology that forms toplayer selection grid 260 to form technology, and be well known to those skilled in the art, do not give unnecessary details at this.

The formation method of the flash memory control grid layer of the embodiment of the invention, by etching interlayer dielectric layer and polysilicon layer repeatedly, and attenuatesecond photoresist layer 242, make the some polysilicon layers in thecontrol grid layer 230, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases from the bottom to top, the projection of the steps at different levels of described ladder onSemiconductor substrate 200 arranged and is linear, and it is described linear parallel with steppedregion 202 contacted borders witharray area 201, described formation method can be with less processing step, accurate formation is step-like, it is easy to have technology, the advantage that the moulding accuracy is high.

The memory cell of the formed flash memory of formation method of the memory cell of present embodiment flash memory please refer to Figure 17 and Figure 18, and Figure 18 is the end view of Figure 17 on BB ' direction, comprising:

Semiconductor substrate 200, describedSemiconductor substrate 200 comprisesarray area 201 and steppedregion 202, described steppedregion 202 is inarray area 201 both sides;

Be positioned at theseparator 210 onSemiconductor substrate 200 surfaces; The bottom that is positioned atseparator 210 surfaces is selectedgrid 220; Be positioned at bottom and select thebottom dielectric layer 221 ongrid 220 surfaces; Run through theseparator 210 of describedarray area 201, the bottom selectiongrid connector array 222 that bottom is selectedgrid 220 andbottom dielectric layer 221;

Be positioned at described bottomdielectric layer 221 and bottom and select thecontrol grid layer 230 ongrid connector array 222 surfaces, describedcontrol grid layer 230 also comprises: some layers of polysilicon layer and be positioned at the interlayer dielectric layer on each layer polysilicon layer surface, wherein, thememory connector array 231 that runs throughcontrol grid layer 230 thickness of describedarray area 201, describedmemory connector array 231 selectsconnector array 222 corresponding one by one with bottom;

Be positioned at the size of some layers of polysilicon layer of thecontrol grid layer 230 of steppedregion 202, the formation ladder that successively successively decreases of the polysilicon layer from the polysilicon layer of the bottom to top layer;

Be positioned at the insulatingbarrier 250 oncontrol grid layer 230 surfaces of steppedregion 202, be positioned at some connectinglines 252 on described insulatingbarrier 250 surfaces, described someconnecting lines 252 some attachment plugs 251 by running through described insulatingbarrier 250 thickness respectively are connected respectively with some layers of polysilicon layer in thecontrol grid layer 230;

The memory cell of described flash memory also comprises: the some top layers that are positioned atcontrol grid layer 230 surfaces of describedarray area 201 are selectedgrid 260, be positioned at somebit lines 263 that described top layer is selected the toplayer dielectric layer 261 ongrid 260 surfaces and is positioned at described toplayer dielectric layer 261 surfaces; The top layer that runs through described toplayer dielectric layer 261 thickness is selectedconnector array 262, and described top layer selectsconnector array 262 corresponding one by one withmemory connector 231 arrays.

Same row's top layer that described some top layers selectgrid 260 to connect respectively on the first direction is selectedconnector array 262, described somebit lines 263 connect same row's top layer on the second directions and select connector in theconnector array 262, and described second direction and first direction are perpendicular.

Please refer to Figure 19, Figure 19 is that the memory cell of flash memory shown in Figure 17 is along CC ' direction, the vertical view of ignoring some interlayer dielectric layers in insulatingbarrier 250,memory connector array 231 and thecontrol grid layer 230, the projection of the steps at different levels of described ladder onSemiconductor substrate 200 arranged and is linear, and described linear parallel with steppedregion 202 contacted borders witharray area 201.

Need to prove, the size of some layers of polysilicon layer in thecontrol grid layer 230 of described steppedregion 202, polysilicon layer from the polysilicon layer of the bottom to top layer successively successively decreases, and each layer polysilicon layer measure-alike with following one deck polysilicon layer minimizing relatively.

The projection of described some attachment plugs 251 on Semiconductor substrate arranged and is linear, and described linear parallel with steppedregion 202 contacted borders witharray area 201.

Please refer to Figure 20, equivalent circuit diagram for the memory cell of embodiment of the invention flash memory, because somebit lines 263select grid 260 vertical mutually with some top layers, when giving abit line 263 and toplayer selection grid 260 certain bias voltages, then thisbit line 263 and this top layerselect grid 260 to choose connector in the connector array, and this connector from top to bottom comprises: top layer is selected connector, memory connector and bottom selection connector;Select grid 220 to add another bias voltage at bottom, then form bias current in this connector; Then can by polysilicon layer thiscontrol grid layer 230 in for the connector chosen control when the certain bias voltage of a certain polysilicon layer that gives in thecontrol grid layer 230 this moment, achieves the function that reads, writes and wipe.

The memory cell of the flash memory that embodiments of the invention provide, do not changing in the prior art in the control grid layer in the stacked structure of some layers of polysilicon layer, by some layers of polysilicon layer in thecontrol grid layer 230 on the steppedregion 202 that makesSemiconductor substrate 200, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases, the projection of the steps at different levels of described ladder onSemiconductor substrate 200 arranged and is linear, and it is described linear parallel with steppedregion 202 contacted sidelines witharray area 201, solved in the BiCS structure of existing control grid layer the space waste problem of control grid layer on the stepped region of Semiconductor substrate.Make in the polysilicon layer multiple-level stack structure in keepingcontrol grid layer 230, reduced the area ofcontrol grid layer 230, thereby improved the bit density of flash memory, and reduced a cost of flash memory.

In sum, the memory cell of the flash memory that embodiments of the invention provide, in the stacked structure that does not change some layers of polysilicon layer in the control grid layer in the prior art, some layers of polysilicon layer in the control grid layer on stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and it is described linear parallel with the contacted sideline of array area and stepped region, can solve in the BiCS structure of existing control grid layer the space waste problem of control grid layer on the stepped region of Semiconductor substrate.Make in the polysilicon layer multiple-level stack structure in keeping control grid layer, reduced the area of control grid layer, thereby improved the bit density of flash memory, and reduced the position cost of flash memory.

The memory cell formation method of the flash memory that embodiments of the invention provide, by attenuate second photoresist layer and etching interlayer dielectric layer and polysilicon layer repeatedly, make the polysilicon layer in the control grid layer form step-like in stepped region, described formation method can be with less processing step, accurate formation is step-like, it is easy to have technology, the advantage that the moulding accuracy is high.

Further, the formation method of the flash memory control grid layer of embodiments of the invention is passed through attenuate second photoresist layer and etching interlayer dielectric layer and polysilicon layer repeatedly, make the polysilicon layer in the control grid layer form step-like in stepped region, described formation method can be with less processing step, accurate formation is step-like, it is easy to have technology, the advantage that the moulding accuracy is high.

Though the embodiment of the invention as mentioned above, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims (22)

1. the memory cell of a flash memory is characterized in that, comprising:

Semiconductor substrate, described Semiconductor substrate comprises array area and stepped region, described stepped region is in the array area both sides; Be positioned at the separator of semiconductor substrate surface; The bottom that is positioned at insulation surface is selected grid; Be positioned at bottom and select the bottom dielectric layer on grid surface;

Run through the separator of described array area, the bottom selection grid connector array that bottom is selected grid and bottom thickness of dielectric layers;

Be positioned at described bottom dielectric layer and bottom and select the control grid layer of grid connector array surface, described control grid layer also comprises: some layers of polysilicon layer and be positioned at the interlayer dielectric layer on each layer polysilicon layer surface, wherein, the memory connector array that runs through the control grid layer thickness of described array area, and described memory connector array selects the connector array corresponding one by one with bottom;

Be positioned at the size of some layers of polysilicon layer of the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region;

Be positioned at the insulating barrier on the control grid layer surface of described stepped region, be positioned at some connecting lines of described surface of insulating layer, described some connecting lines some attachment plugs by running through described thickness of insulating layer respectively are connected respectively with some layers of polysilicon layer in the control grid layer, the projection of described some attachment plugs on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region.

2. according to the memory cell of the described flash memory of claim 1, it is characterized in that, also comprise: the some top layers that are positioned at the control grid layer surface of described array area are selected grid; Be positioned at some top layers and select the top layer dielectric layer on grid surface; Be positioned at some bit lines on top layer dielectric layer surface; Run through described top layer dielectric layer and top layer and select the top layer of grid thickness to select the connector array, described top layer selects the connector array corresponding one by one with memory connector array, and is connected with bit line.

3. according to the memory cell of the described flash memory of claim 1, it is characterized in that described interlayer dielectric layer is insulation material layer or amorphous carbon layer.

4. according to the memory cell of the described flash memory of claim 3, it is characterized in that described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.

5. according to the memory cell of the described flash memory of claim 1, it is characterized in that, the size of some layers of polysilicon layer in the control grid layer of described stepped region, polysilicon layer from the polysilicon layer of the bottom to top layer successively successively decreases, and each layer polysilicon layer measure-alike with following one deck polysilicon layer minimizing relatively.

6. according to the memory cell of the described flash memory of claim 1, it is characterized in that, described separator comprises oxide layer, catches charge layer and barrier oxide layer, and the described charge layer of catching is positioned at described oxide layer surface, and described barrier oxide layer is positioned at the described charge layer surface of catching.

7. according to the memory cell of the described flash memory of claim 6, it is characterized in that the material of described oxide layer is silica, described material of catching charge layer is silicon nitride, material oxidation silicon or the aluminium oxide of described barrier oxide layer.

8. the formation method of the memory cell of a flash memory is characterized in that, comprising:

Semiconductor substrate is provided, and semiconductor substrate surface has separator successively, bottom is selected grid, bottom dielectric layer and control grid layer, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is positioned at the array area both sides; Run through the separator of described array area, the bottom selection grid connector array that bottom is selected grid and bottom thickness of dielectric layers; Described control grid layer comprises: some layers of polysilicon layer and be positioned at the interlayer dielectric layer on each layer polysilicon layer surface, wherein, run through the memory connector array of the control grid layer thickness of described array area, and described memory connector array is corresponding one by one with bottom selection connector array;

Form hard mask layer on the control grid layer surface;

Forming first photoresist layer on described hard mask layer surface, is that mask is removed array area and stepped region control grid layer and hard mask layer in addition with first photoresist layer;

Remove first photoresist layer of stepped region and hard mask layer till exposing first interlayer dielectric layer, described first interlayer dielectric layer is the interlayer dielectric layer of top layer in the control grid layer, removes first photoresist layer of array area;

Form second photoresist layer at hard mask layer and first interlayer dielectric layer surface;

Etching interlayer dielectric layer and polysilicon layer and the attenuate second photoresist layer several times repeatedly, make the size of some layers of polysilicon layer in the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to the top layer formation ladder that successively successively decreases from the bottom to top, the projection of the steps at different levels of described ladder on Semiconductor substrate arranged and is linear, and described linear parallel with the contacted border of array area and stepped region;

Control grid layer surface in stepped region forms insulating barrier, forms the some attachment plugs that run through described thickness of insulating layer, is connected with some layers of polysilicon layer respectively;

Form some connecting lines at insulating barrier and attachment plug surface, described some connecting lines are connected with some polysilicon layers by some attachment plugs respectively.

9. the formation method of the memory cell of described flash memory according to Claim 8 is characterized in that, also comprises step: form some top layers on the control grid layer surface of array area and select grid, select the grid surface to form the top layer dielectric layers at some top layers; Formation runs through described top selects the top layer of grid and top layer thickness of dielectric layers to select the connector array, and described top layer selects the connector array corresponding one by one with memory connector array; Form some bit lines on described top layer dielectric layer surface, described bit line selects the connector array to be connected with top layer.

10. the formation method of the memory cell of described flash memory according to Claim 8, it is characterized in that, described at hard mask layer and first interlayer dielectric layer surface formation, second photoresist layer, and the method for etching interlayer dielectric layer and polysilicon layer and the attenuate second photoresist layer several times repeatedly, also comprise step:

Form second photoresist layer at hard mask layer and first interlayer dielectric layer surface, and expose the first step district in the stepped region, described first step district is bottom step The corresponding area in the stepped region;

Be mask with second photoresist layer and hard mask layer, etching first interlayer dielectric layer and first polysilicon layer, and expose second interlayer dielectric layer, described first polysilicon layer is the polysilicon layer of top layer in the control grid layer, and described second interlayer dielectric layer is the interlayer dielectric layer of one deck under first interlayer dielectric layer;

Attenuate second photoresist layer also exposes the second step district of first interlayer dielectric layer in the stepped region, and described second step district is corresponding zone on upper level step place first interlayer dielectric layer of bottom step;

Be mask with second photoresist layer and hard mask layer, at second step district etching first interlayer dielectric layer and first polysilicon layer, at first step district etching second interlayer dielectric layer and second polysilicon layer, described second polysilicon layer is the polysilicon layer of one deck under first polysilicon layer;

Attenuate second photoresist layer also exposes the 3rd stepped region of first interlayer dielectric layer, and described the 3rd stepped region is zone corresponding on first interlayer dielectric layer of upper level step place, second step district.

11. the formation method of the memory cell of described flash memory is characterized in that according to Claim 8, the technology of described attenuate photoresist is dry etching.

12. the formation method of the memory cell of described flash memory is characterized in that according to Claim 8, the technology of described etching interlayer dielectric layer and polysilicon layer is the reactive ion etching method.

13. the formation method according to the memory cell of the described flash memory of claim 12 is characterized in that described interlayer dielectric layer is 1～50 for the etching selection ratio of hard mask layer, described polysilicon layer is 5～200 for the etching selection ratio of hard mask layer.

14. the formation method of the memory cell of described flash memory is characterized in that according to Claim 8, described hard mask layer is that in insulation material layer, metal level or the amorphous carbon layer one or more overlap.

15. the formation method according to the memory cell of the described flash memory of claim 14 is characterized in that described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.

16. the formation method according to the memory cell of the described flash memory of claim 14 is characterized in that, the material of described metal level is one or more the alloy in copper, tungsten, the aluminium.

17. the formation method of the memory cell of described flash memory is characterized in that according to Claim 8, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.

18. the formation method according to the memory cell of the described flash memory of claim 17 is characterized in that described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.

19. the formation method of the memory cell of described flash memory is characterized in that according to Claim 8, the material of described hard mask layer and interlayer dielectric layer is inequality.

20. the formation method of the memory cell of described flash memory according to Claim 8, it is characterized in that, the size of some layers of polysilicon layer in the control grid layer of described stepped region, polysilicon layer from the polysilicon layer of the bottom to top layer successively successively decreases, and each layer polysilicon layer measure-alike with following one deck polysilicon layer minimizing relatively.

21. the formation method of the memory cell of described flash memory is characterized in that according to Claim 8, described separator successively by oxide layer, catch charge layer and barrier oxide layer and pile up and constitute.

22. the formation method according to the memory cell of the described flash memory of claim 21 is characterized in that the material of described oxide layer is silica, described material of catching charge layer is silicon nitride, material oxidation silicon or the aluminium oxide of described barrier oxide layer.

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