CN103248207A - Constant-current and constant-voltage fly-back converter based on primary side feedback - Google Patents

Abstract

The invention discloses a constant-current and constant-voltage fly-back converter based on primary side feedback. The constant-current and constant-voltage fly-back converter comprises a rectifying bridge, an inverted U-shaped filter, a transformer, an auxiliary power supply circuit, a constant-current and constant-voltage controller and a switch tube, wherein the transformer consists of a primary winding, a secondary winding and an auxiliary winding; the constant-current and constant-voltage controller comprises a constant-voltage module, a frequency generator, a constant-current module, a joint gate, an RS trigger and a driving module; the output end of the constant-voltage module and the first and second output ends of the constant-current module are connected with three input ends of the joint gate; the input end of the constant-current module is connected with the emitting electrode of the switch tube, and is used for sampling a current signal of the primary winding; the output end of the joint gate is connected with the R end of the RS trigger, and is used for transmitting a switch-off signal generated by the joint gate to the R end of the RS trigger; the switch-on signal of the frequency generator is output to the S end of the RS trigger; the RS trigger is used for receiving the switch-on signal and the switch-off signal to generate a modulating signal; and the Q end of the RS trigger is connected with the input end of the driving module.

Description

A kind of constant current constant voltage formula inverse excitation type converter based on former limit feedback

Technical field

Designing integrated circuit of the present invention field.More particularly, the present invention relates to a kind of constant current constant voltage formula inverse excitation type converter based on former limit feedback.

Background technology

Hand-hold type personal telecommunication terminal (such as mobile phone) product develops rapidly in recent years.Its relevant charger market is developed thereupon.Inverse excitation type converter is because himself cost, performance advantage are widely used in this field.And the constant-current constant-voltage controller of the former limit of various employings feedback is with low cost because its peripheral structure is simple, is widely accepted and uses.

The constant-current constant-voltage controller of existing former limit feedback, the inverse excitation type converter of building, as shown in Figure 1.Comprise,rectifier bridge 170, ∏ mode filter 171,absorb circuit 172, theelementary winding 180 of transformer 173(,secondary winding 181, auxiliary winding 182), the constant-current constant-voltage controller 187 of former limit feedback,secondary commutation diode 174,output capacitance 175,output dummy load 176, auxiliarypower supply circuit 177,switching tube 178, primarycurrent sampling resistor 179.

The constant-current constant-voltage controller 187 of former limit feedback, comprise that degaussing detection module 120, sampling keepmodule 110,time delay module 130, operational amplifier 112,comparator 140, rest-set flip-flop 150,driver module 152, lead-edge-blanking module 160, transmitting switch 162 etc.

The constant-current constant-voltage controller 187 of former limit feedback needs the extraction information relevant with output voltage and output loading, and the conducting by exporting the modulation signal control switch and ending comes regulated output voltage.In system shown in Figure 1, such information can be extracted bysignal 100 and signal 101.Wherein,signal 100 equal proportions reflection output voltage values; Andsignal 101 is the electric current of theelementary winding 180 of flowing through, at the voltage signal of primarycurrent sampling resistor 179 formation.

Suppose that output voltage is Vout,secondary winding 181 numbers of turn are that Ns,auxiliary winding 182 numbers of turn are Naux, andsignal 100 is V at the magnitude of voltage of direct current section_Fb

$V_{\mathrm{fb}}=\frac{N_{\mathrm{aux}}}{N_s}*V_o*\frac{R3}{R2+R3}$(formula 1)

Formula 1 as can be seen, output voltage V o and V_FbVoltage is linear, can pass through constant V_FbThe way of voltage voltage is come constant output voltage.

If switch 178 conductings, the electric current of theelementary winding 180 of then flowing through, the linear increase,signal 101 is linear the increase also.Signal 101 generatessignal 102 through behind the transmitting switch 162, and enterscomparator 140 withthreshold voltage signal 113, generates signal 141.Whensignal 102 surpassed threshold voltage signal 116, thencomparator signal 141 was high level.

Whenswitch 178 ended, the energy that is stored in the transformer was released to output, and demagnetization process begins.In demagnetization process, sampling keeps the maintenance of sampling of 110 pairs ofsignals 100 of module, output signal 111.Signal 111 is poor withreference voltage Vref 1, is amplified to generate amplifyingsignal 113 by error amplifier 112.The detection module of degaussing simultaneously detects degaussing time T demag, generates signal 121.Signal 113 andsignal 121 entertime delay module 130 together, and Tdis is after the time for process,output signal 131.

Rest-set flip-flop 150 receivessignal 131 and 141, and generatessignal 151 in response.Be logic low ifsignal 131 is logic high andsignal 141, thensignal 151 is logic high.Be logic high ifsignal 131 is logic low andsignal 141, thensignal 151 is logic low.

If shown in 1,signal 151 drivenmodules 152 receive, andoutput signal 153 is given switch 178.Ifsignal 151 is high level, drivermodule output signal 153 makesdriving switch 178 conductings.Otherwise ifsignal 151 is low level, drivermodule output signal 153 is endeddriving switch 178.

Reference supply convertor shown in Figure 1 system, output loading is more big, and theoutput signal 113 of error amplifier 112 becomes more big so.Theoutput signal 131 oftime delay module 130, the Tdis time of decision is more little.Whole supply convertor system frequency is more high.Otherwise output loading is more little, and theoutput signal 113 of error amplifier 112 becomes more little so.Theoutput signal 131 oftime delay module 130, the Tdis time of decision is more little big.Whole supply convertor system frequency is more low.

When if output loading is dynamically switched, load switches to fully loaded suddenly from underloading, because the feedback information of former limit feedback needs could sample in the next cycle.At one-period in the time, because the controller of former limit feedback can't detect output voltage information, output voltage can continue to fall so.

Up-to-date USB3.0 standard has proposed higher dynamic response capability to the charger of the specified 5V1A of being output as, and output voltage range is 4.75～5.25V.The charger output capacitance of 5V1A is generally 1000uF.

Drop-off voltage value according to 0.5V.

$C=\frac{Q}{U}=\frac{I*T}{U}$(formula 2)

$T=\frac{C*U}{I}=500\mathrm{uS}$

$\mathrm{Fsw}=\frac{1}{T}=2\mathrm{KHz}$

The lowermost switch frequency Fsw of the controller of former limit feedback is greater than and equals 2K.

When unloaded, the constant current constant voltage control of former limit feedback needs to guarantee the requirement of the lowermost switch frequency of 2K, and the size of the service time of this moment has determined the size of the idling consumption of whole supply convertor.

$P=V_{\mathrm{DC}}*\frac{1}{2}*I_p*\frac{\mathrm{Ton}}{T}$(formula 3)

Inverse excitation type converter is being opened moment, has immediate current to pass through transformer turn-to-turn capacitance, diode equivalent electric capacity, byswitch 178, forms spike at primary current sampling resistor 179.In order to hide the interference of peak voltage.Need lead-edge-blanking module 160, receivesignal 151, postpone just to make transmittingswitch 161 conductings behind a period of time Tleb.(seeing Fig. 2, Fig. 3)

Tleb is typically designed to 500nS in the practical application.

So, system shown in Figure 1, minimum ON time Ton also is 500nS.

So according to calculating, the specified charger that is output as 5V1A, the inductance value of the elementary winding 110 of transformer is about 1.5mH, so when 230V exchanges input, whole charger stand-by power consumption is at least, and determines that by minimum duty cycle and lowermost switch frequency limitation loss is at least

Formula$P=V_{\mathrm{DC}}*\frac{1}{2}*I_p*\frac{T_{\mathrm{LEB}}}{T}=V_{\mathrm{DC}}*\frac{1}{2}*\left(\frac{V_{\mathrm{DC}}*T_{\mathrm{LEB}}}{L_P}\right)*\frac{T_{\mathrm{LEB}}}{T}\≈17\mathrm{mW}$

If design a kind of constant-current constant-voltage controller of former limit feedback newly, if its minimum service time is not subjected to the restriction of lead-edge-blanking time.So, use its supply convertor of building, under the similarity condition, the constant-current constant-voltage controller of general relatively former limit feedback will have lower stand-by power consumption.

Summary of the invention

The invention provides the constant current constant voltage formula inverse excitation type converter based on former limit feedback that a kind of dynamic response is better and stand-by power consumption is lower.

The technical scheme of technical solution problem of the present invention is:

A kind of constant current constant voltage formula inverse excitation type converter based on former limit feedback, comprise: rectifier bridge, the ∏ mode filter, absorb circuit, by elementary winding, the transformer that secondary winding and auxiliary winding constitute, constant-current constant-voltage controller and switching tube, described secondary winding also is connected with secondary circuit, described auxiliary winding also is connected with the auxiliary power supply circuit, the base stage of described switching tube is connected with the output of constant-current constant-voltage controller, the collector electrode of switching tube is connected with elementary winding, the emitter of switching tube is by primary current sampling resistor ground connection, described constant-current constant-voltage controller comprises the constant voltage module, frequency generator, constant flow module, or door, rest-set flip-flop and driver module, the input of described constant voltage module is used for the voltage voltage division signal of the auxiliary winding of sampling, first of the output of constant voltage module and constant flow module, second output respectively with or three inputs of door are connected and for first cut-off signals, second cut-off signals and the 3rd cut-off signals be sent to respectively or the door three inputs, the input of constant flow module is connected the current signal that is used for the elementary winding of sampling with the emitter of described switching tube, the R end of output and the rest-set flip-flop of described or door is connected and be used for will or the cut-off signals of the pupil's one-tenth R that is sent to rest-set flip-flop hold, the input of described frequency generator is used for sampling and receives the voltage voltage division signal of auxiliary winding, frequency generator produces opens signal and exports the S end of rest-set flip-flop to, described rest-set flip-flop is used for receiving opens signal and cut-off signals, generate modulation signal, the Q end of rest-set flip-flop is connected with the input of driver module, described driver module is used for receiving modulation signal, and to described switching tube output drive signal.

Compare with the constant-current constant-voltage controller of the former limit of tradition feedback, the present invention has many benefits.When unloaded, the triangular wave of first threshold signal and inside enters first comparator and compares.By modulation module, the output modulation signal.By experiments more of the present invention, show the inverse excitation type converter that the present invention builds, can not be subjected to the restriction of lead-edge-blanking time, the lowermost switch frequency (seeing Fig. 3, Fig. 6 contrast) that can have littler service time and Geng Gao when unloaded, thereby, can satisfy the requirement of dynamic response and stand-by power consumption simultaneously.

Description of drawings

Fig. 1 is the inverse excitation type converter system simplification diagram of the constant-current constant-voltage controller of existing former limit feedback.

Fig. 2 is the simplified timing diagram of system among Fig. 1.

Simplified timing diagram when Fig. 3 is system among Fig. 1 unloaded.

Fig. 4 is the constant current constant voltage formula inverse excitation type converter system simplification diagram of former according to an embodiment of the invention limit feedback.

Fig. 5 is the simplified timing diagram of constant current constant voltage formula inverse excitation type converter system of the former limit feedback of Fig. 4 embodiments of the invention.

Simplified timing diagram when Fig. 6 is constant current constant voltage formula inverse excitation type converter system unloaded of former limit feedback of Fig. 4 embodiments of the invention.

Fig. 7 is in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention, the simplification diagram of degaussing detection module 420.

Fig. 8 is the simplified timing diagram of Fig. 7 degaussing detection module 420.

Fig. 9 is that sampling keeps the simplification diagram ofmodule 410 in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention.

Figure 10 is that Fig. 9 samples and keeps the simplified timing diagram ofmodule 410.

Figure 11 is in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention, the simplification diagram oftime delay module 430.

Figure 12 is the simplified timing diagram of Figure 11time delay module 430.

Figure 13 is in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention, the simplification diagram of triangular-wave generator 433.

Figure 14 is the simplified timing diagram of Figure 13 triangular-wave generator 433.

Figure 15 is that the simplification diagram of currentsample computing module 440 is fed back in the constant current constant voltage formula inverse excitation type converter system of building on the former limit of Fig. 4 embodiments of the invention.

Figure 16 is the simplified timing diagram of Figure 15 currentsample computing module 440.

Embodiment

A kind of constant current constant voltage formula inverse excitation type converter based on former limit feedback, comprise:rectifier bridge 470, ∏mode filter 471,absorb circuit 472, byelementary winding 480, thetransformer 473 thatsecondary winding 481 andauxiliary winding 482 constitute, constant-current constant-voltage controller 479 andswitching tube 487, describedsecondary winding 481 also is connected withsecondary circuit 494, describedauxiliary winding 482 also is connected with auxiliarypower supply circuit 474, the base stage of describedswitching tube 487 is connected with the output of constant-current constant-voltage controller 479, the collector electrode ofswitching tube 487 is connected withelementary winding 480, the emitter ofswitching tube 487 is by primarycurrent sampling resistor 488 ground connection, described constant-current constant-voltage controller 479 comprisesconstant voltage module 490,frequency generator 491,constant flow module 492, ordoor 462, rest-set flip-flop 464 anddriver module 466, the input of describedconstant voltage module 490 is used for the voltagevoltage division signal 400 of theauxiliary winding 482 of sampling, first of the output ofconstant voltage module 490 andconstant flow module 492, second output respectively with or door three inputs of 462 are connected and for first cut-offsignals 415, second cut-offsignals 453 and the 3rd cut-offsignals 461 are sent to respectively or door three inputs of 462, the input ofconstant flow module 492 is connected thecurrent signal 401 that is used for theelementary winding 480 of sampling with the emitter of describedswitching tube 487, described ordoor 462 output is connected with the R end of rest-set flip-flop 463 and be used for will or the cut-offsignals 463 of thedoor 462 generations R that is sent to rest-set flip-flop 464 hold, the input of describedfrequency generator 491 is used for sampling and receives the voltagevoltage division signal 400 ofauxiliary winding 482,frequency generator 491 produces openssignal 432 and exports the S end of rest-set flip-flop 464 to, described rest-set flip-flop 464 is used for receivingopens signal 432 and cut-offsignals 463, generatemodulation signal 465, the Q end of rest-set flip-flop 464 is connected with the input ofdriver module 466, describeddriver module 466 is used for receivingmodulation signal 465, and to describedswitching tube 487output drive signals 467.

In the present embodiment,

Describedfrequency generator 491 comprises degaussing detection module 420,time delay module 430 and triangular-wave generator 433, the input of degaussing detection module 420 is as the input offrequency generator 491, the outputdegaussing time signal 421 of degaussing detection module 420,degaussing time signal 421 enterstime delay module 430,open signal 432 and second through time-delay back generation first andopen signal 431, first openssignal 432 is delivered to S end with rest-set flip-flop 464 as the output signal offrequency generator 491 output by describedfrequency generator 491, triangular-wave generator 433 receives second and openssignal 431, generatestriangular signal 434;

Describedconstant voltage module 490 comprises that sampling keepsmodule 410,first error amplifier 412, first comparator 414, the input that sampling keepsmodule 410 asconstant voltage module 490 input, sampling keeps theoutput signal 411 ofmodule 410 to enterfirst error amplifier 412, and generationfirst threshold signal 413,first threshold signal 413 and thetriangular signal 434 that is generated by described triangular-wave generator 433 enter first comparator 414, generate first cut-offsignals 415 and asconstant voltage module 490 output signals;

Describedconstant flow module 492 comprises currentsample computing module 440,second error amplifier 450,second comparator 452 and the3rd comparator 460, currentsample computing module 440 also is used for thecurrent signal 401 of theelementary winding 480 of sampling as the input ofconstant flow module 492, entersecond error amplifier 450 through the output signal after calculating, generatesecond threshold signal 451,second threshold signal 451 and thetriangular signal 434 that is generated by described triangular-wave generator 433 entersecond comparator 452, and generate second cut-off signals 453, simultaneously, primary windingcurrent signal 401 enters the3rd comparator 460, generates the 3rd cut-off signals 461.

With reference to following the detailed description and the accompanying drawings, can comprehensive purpose of the present invention, characteristics and advantage.

Fig. 4 is the constant current constant voltage formula inverse excitation type converter system simplification diagram of former according to an embodiment of the invention limit feedback.This diagram only is example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, substitutions and modifications.

Fig. 5 is the simplified timing diagram of constant current constant voltage formula inverse excitation type converter system of the former limit feedback of Fig. 4 embodiments of the invention.

Simplified timing diagram when Fig. 6 is constant current constant voltage formula inverse excitation type converter system unloaded of former limit feedback of Fig. 4 embodiments of the invention.

Power converting system shown in Figure 4, in an example,signal 465 output high level bydriver module 466, generate anddrive signal 467, makeswitching tube 487 conductings, and electric current is linear in theelementary winding 480 increases storage power.Meanwhile,triangular signal 434 linear risings increase.In another example,threshold signal 413 andtriangular signal 434 enter comparator 414 together.Signal 434 surpassesthreshold signal 413, and thencomparison signal 415 is logic high.Enter multichannel ordoor 462.

In another example,signal 465 output low levels bydriver module 466, generate and drivesignal 467, and switchingtube 487 is ended, and be stored in elementary winding 480 energy and be released tosecondary winding 481 andauxiliary winding 482 this moment, and transformer is finished degaussing.In demagnetization process, sampling keeps thevoltage division signal 400 of 410 pairs ofauxiliary windings 482 of module to sample, and output voltage signal 411.Signal 411 enterserror amplifier 412 withreference voltage Vref 1, carries out error and amplifiesoutput signal 413.

According to an example, primary windingcurrent sampling resistor 488 is for detection of the current signal of elementary winding 480, formation voltage signal 401.Signal 401, signal 421, signal 432 entercurrent sample module 440 together, generate signal 441.In another example, signal 441 enterserror amplifier 450 withreference voltage Vref 2, carries out error and amplifies, output threshold signal 451.In another example,threshold signal 451 andtriangular signal 434enter comparator 452 together.Triangular signal 434 linear risings increase, and surpassthreshold signal 451, and thencomparison signal 453 is logic high.

In another example; signal 401 is compareddevice 460 and receives, and comparator also is used for receiving the threshold signal Vref3 of overcurrent protection, and threshold signal Vref3 is compared withsignal 401; when signal 401 surpassed threshold signal Vref3,comparator 460output signals 461 became high level.

In an example, multichannel ordoor 462 receivesignal 415, signal 453, signal 461, and output signal 463.For example, signal 415 is high level, and signal 453 is low level, and signal 461 is low level, and signal 463 is high level so.Signal 415 is low level, and signal 453 is high level, and signal 461 is low level, and signal 463 is high level so.Signal 415 is low level, and signal 453 is low level, and signal 461 is high level, and signal 363 is high level so.Signal 315 is low level, and signal 353 is low level, and signal 361 is low level, and signal 463 is low level so.

According to an example,time delay module 430 receives degaussingtime signal 421, signal 411, and signal 441, through behind certain delay time Tdis,output signal 432 becomes high level, enters rest-set flip-flop 464.In another example,time delay module 430output signals 431 enter triangular-wave generator 433.

In an example, triangular-wave generator 433 receives triggeringsignal 431, and generatestriangular signal 434.

In an example, rest-set flip-flop 464 receivessignal 432 and signals 463, andoutput signal 465 in response.For example, be logic low ifsignal 432 is logic high and 463, then signal 465 is logic high.Be logic high ifsignal 432 is logic high and 463, then signal 465 is logic low.

Fig. 7 is in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention, the simplification diagram of degaussing detection module 420.This diagram only is example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, replacement and change.

For example, degaussing detection module 420 comprisescomparator 701, notgate 710 and 720, and withdoor 730 and 750, rest-set flip-flop 740.

Fig. 8 is the simplified timing diagram of Fig. 7 degaussing detection module 420.With reference to figure 4, Fig. 7 and Fig. 8, thevoltage division signal 400 of auxiliary winding enterscomparator 701, compares with threshold voltage (being 0.1V among Fig. 7),output signal 702, behind notgate 710, output signal 711.In another example, signal 465 behind notgate 720, output signal 721.According to another example, receivesignal 711 and signal 721 withdoor 730,output signal 731.

In an example, rest-set flip-flop 740 receivessignal 465 and signal 731, andoutput signal 741 in response.For example, be logic low ifsignal 731 is logic high and 465, then signal 741 is logic high.Be logic high ifsignal 731 is logic low and 465, then signal 741 is logic low.

In an example, receivesignal 741 and 702,output signal 421 withdoor 750.

Fig. 9 is that sampling keeps the simplification diagram ofmodule 410 in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention.This diagram only is example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that many variants, replacement and change.

Figure 10 is that Fig. 9 samples and keeps the simplified timing diagram ofmodule 410.

Sampling keepsmodule 410 to comprise: d type flip flop 901, withdoor 903, withdoor 904, withdoor 951, withdoor 952 and 971,current source 910, current source 911,current source 913 and 924,switch 921,switch 922,switch 923,switch 914,switch 991,electric capacity 931,electric capacity 932 and 981,comparator 941 and 942, monostable 955 and 956 ordoor 961.

With reference to figure 9 and Figure 10, degaussing time signal 421 and d type flip flop CLK end is connected, the D input of d type flip flop 901 withOutput is connected and forms 2 frequency dividing circuits, and degaussing time signal 421 is carried out 2 frequency divisions, and the Q output of d type flip flop 901 and degaussing time signal 421 enter and door 903, and output signal 905, d type flip flop 901

Output and degaussing time signal 421 enter and door 904, and output signal 906.Degaussing time signal 421 is divided into first cycle degaussing time signal 905 and second period degaussing time signal 906.Current source 910 upper ends are connected with constant voltage VDD, and the lower end is connected with switch 921 upper ends, and switch 921 lower ends are connected with switch 922 upper ends, switch 922 lower ends and another current source 911 upper ends, current source 911 lower end ground connection.Current source 913 upper ends are connected with constant voltage VDD, and the lower end is connected with switch 923 upper ends, and switch 923 lower ends are connected with switch 914 upper ends, switch 914 lower ends and another current source 924 upper ends, current source 924 lower end ground connection.Signal 905 control switchs 921 and 914.Signal 906 control switchs 922 and 923.The tie point of switch 921 and switch 922 is connected with electric capacity 931 1 ends, and is connected electric capacity 931 other end ground connection with comparator 941 negative terminals simultaneously.The tie point of switch 923 and switch 914 is connected with electric capacity 932 1 ends, and is connected electric capacity 932 other end ground connection with comparator 942 negative terminals simultaneously.Comparator 941 and 942 positive input termination reference voltage 0.1V.The output of comparator 941 and signal 906 enter and door 951, output signal 953.The output of comparator 942 and signal 905 enter and door 952, output signal 954.Monostable 955 receives signal 953, and output pulse signal 957.Monostable 956 receives signal 954, and output pulse signal 958.Pulse signal 957 and 958 enters or door 961 together, and output signal 962.Signal 962 and degaussing signal 421 enter and door 971, output signal 972.Switch 991 1 ends are connected with the voltage division signal 400 of auxiliary winding, and switch 991 other ends are connected with electric capacity 981 1 ends, generate signal 411, electric capacity 981 other end ground connection.Signal 972 control switchs 991.First cycle degaussing time signal 905 with constant current I charging, in the mode of integration, to first cycle degaussing time signal 905, is carried out stored record by 921 pairs of capacitors 931 of switch.Second period degaussing time signal 906 is carried out constant current 2I discharge by 922 pairs of capacitors of switch 931.When the voltage signal 925 of capacitor 931 was lower than 0.1V, trigger comparator 941 was exported high level, and enters and door 951 with signal 906, and output signal 953, and signal 953 enters monostable 955 production burst signals 957.Second period degaussing time signal 906 with constant current I charging, in the mode of integration, to second period degaussing time signal 906, is carried out stored record by 923 pairs of capacitors 932 of switch.First cycle degaussing time signal 905 is carried out constant current 2I discharge by 914 pairs of capacitors of switch 932.When the voltage signal 926 of capacitor 932 was lower than 0.1V, trigger comparator 942 was exported high level, and enters and door 952 with signal 905, and output signal 954, and signal 954 enters monostable 956 production burst signals 958.Signal 957 and 958 warps or door 961 generate signals 962, and signal 962 warps and door 971 generate signals 972, and control switch 991 is sampled to the voltage division signal 400 of assisting winding.

Figure 11 is in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention, the simplification diagram of time delay module 430.This diagram only is example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that more changeable body, replacement and change.

Figure 12 is the simplified timing diagram of Figure 11time delay module 430.

Time delay module 430 comprises:switch 1110,electric capacity 1120,resistance 1140,comparator 1150, multiplier 1130.With reference to Figure 11 and Figure 12.Degaussing time signal 421 control switchs 1110.Switch 1,110 one ends are connected with voltage VDD, and the other end is connected withresistance 1140 withelectric capacity 1120, and the tie point signal is 1101.Electric capacity 1120 links to each other with ground withresistance 1140other ends.Signal 411 and 441 entersmultiplier 1130,multiplier 1130 output signals 1102.Signal 1101 is connected with negative input end with the positive input terminal ofcomparator 1150 respectively with signal 1102.Comparator 1150output signals 431 and signal 432.

For example, whenswitch 1110 is opened in 421 controls of degaussing time signal, toelectric capacity 1120 chargings; During shutoff, utilize 1140 pairs of electric capacity ofresistance 1120 to carry out the RC discharge.In another example, reflect thesignal 411 and 441 of output voltage, output current information respectively, entermultiplier 1130,output signal 1102, signal 1102 reflection output power information.

According to another example,signal 1101 and signal 1102enter comparator 1150,output signal 431 and 432.The control switch frequency.Make that power is more big,signal 1102 is more big, and the Tdis time is more short, and switching frequency is more high; Otherwise power is more low, andsignal 1102 is more little, and Tdis is more long, and switching frequency is more low.

Figure 13 is in the constant current constant voltage formula inverse excitation type converter system of former limit feedback of Fig. 4 embodiments of the invention, the simplification diagram of triangular-wave generator 433.This diagram only is example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that more changeable body, replacement and change.

Figure 14 is the simplified timing diagram of Figure 13 triangular-wave generator 433.

Triangular-wave generator 433 comprises: dtype flip flop 1310, notgate 1320 and 1380,switch 1330 and 1340,electric capacity 1360,current source 1150, comparator 1370.With reference to Figure 13 and Figure 14, the D input of dtype flip flop 1310 links to each other with voltage VDD, and signal 431 is connected with the CLK of d type flip flop 1310.The Qoutput control switch 1330 of d type flip flop 1310.The Q output of dtype flip flop 1310 is controlled anotherswitch 1340 through behind the not gate 1320.Current source 1,150 one ends link to each other with VDD, and the other end links to each other with switch 1,330 one ends, and 1330 other ends link to eachother switch 1340 other end ground connection with another switch 1,340 one ends.The tie point ofswitch 1330 and switch 1340 links to each other withelectric capacity 1360 simultaneously, and links to each other with the negative input end of comparator 1370.Electric capacity 1360 other end ground connection.Fixed voltage 2V links to each other with the positive input terminal ofcomparator 1370, andcomparator 1370output signals 1371 behind notgate 1380, generatesignal 1381, and signal 1381 links to each other with the CLR input of dtype flip flop 1310.

For example,signal 1311 and signal 1321 becontrol switch 1330 and 1340 respectively, andelectric capacity 1360 is carried out charging and discharging.Generate triangular signal 434.In another example,triangular signal 434 enterscomparator 1370 with the 2V threshold value, and when signal 434 surpassed 2V,output comparison signal 1371 was low level.According to another example, aftersignal 1371 enters not gate 1180, output signal 1381.According to another example, signal 431 andsignal 1381 enter dtype flip flop 1310, generate signal 1311.Dtype flip flop 1310, D input termination high level.Ifsignal 431 is that high level and CLR input are low level, d type flip flop Q output is exported high level so; If the CLR input is high level, d type flip flop Q output so, output low level.

Figure 15 is that the simplification diagram of currentsample computing module 440 is fed back in the constant current constant voltage formula inverse excitation type converter system of building on the former limit of Fig. 4 embodiments of the invention.。This diagram only is example, and it should not limit the scope of claim undeservedly.Those skilled in the art will recognize that more changeable body, replacement and change.

Figure 16 is the simplified timing diagram of Figure 15 currentsample computing module 440.

Currentsample computing module 440 comprises:switch 1510, switch 1530,switch 1531,switch 1532,electric capacity 1520, electric capacity 1560,resistance 1540, notgate 1553,XOR gate 1550.

With reference to Figure 15 and Figure 16, switch 1,510 one ends link to each other withsignal 401, and the other end links to each other withelectric capacity 1520, and the tie point signal is 1511.Electric capacity 1520 other end ground connection.Switch 1,530 one ends link to each other withsignal 1511, and the other end links to each other with 1532 withswitch 1531, link to each other withresistance 1540simultaneously.Switch 1531 other endground connection.Switch 1532 other endground connection.Resistance 1540 other ends link to each other with electric capacity 1560, and the tie point signal is 441.Electric capacity 1560 other endground connection.Signal 421 generatessignal 1552 behind not gate 1553.Signal 432 andsignal 1552enter XOR gate 1550, and output signal 1551.Signal 432 control switchs 1510.Signal 421 control switchs 1530.Signal 432 control switchs 1531.Signal 1551control switchs 1532.

1510 pairs of signals ofsignal 432 control switchs 401 carry out peak value sampling, and the voltage max ofsignal 401 is remained on electric capacity 1520.In another example, signal 421, signal 432 andsignal 1551, control switch 1530,switch 1531 andswitch 1532 discharge and recharge by 1540 pairs of electric capacity 1560 of resistance respectively.

According to another example, signal 421 is through the non-signal 1552 that generates behind the door, andsignal 1552 and signal 432enter XOR gate 1550 together, and generates signal 1551.Whensignal 1552 is logic high and signal 432 during for logic low,signal 1551 is high level; Whensignal 1552 is logic low and signal 432 during for logic high,signal 1551 is high level; Whensignal 1552 is logic high and signal 432 during for logic high,signal 1551 is low level; Whensignal 1552 is logic low and signal 432 during for logic low,signal 1551 is low level.

See Figure 16, the service time Ton of the timerepresentation switch pipe 487 ofsignal 432 high level, signal 421 represent transformer degaussing time T demag the time of high level, andsignal 1551 represents delay time Tdis.

Electric capacity 1560 capacity are relatively large, and signal 441 magnitudes of voltage are basicly stable, can obviously not fluctuate because of discharging and recharging.In a switch periods, the charging charge of electric capacity 1560 equals discharge charge substantially so.The crest voltage of supposingsignal 401 is Vcs, and the magnitude of voltage of supposingsignal 441 is Vavg.

So$\frac{V_{\mathrm{cs}}-V_{\mathrm{avg}}}{R8}*T_{\mathrm{demag}}=\frac{V_{\mathrm{avg}}}{R8}*(T_{\mathrm{on}}+T_{\mathrm{dis}})$(formula 4)

Draw,$\frac{T_{\mathrm{demag}}}{T_{\mathrm{on}}+T_{\mathrm{demag}}+T_{\mathrm{dis}}}*V_{\mathrm{cs}}=V_{\mathrm{avg}}$(formula 5)

Suppose that peak primary currents is Ip, elementary umber of turn Np, secondary winding number of turn Ns, output current are Iout

Output current

$I_{\mathrm{out}}=\frac{1}{2}*I_P*\frac{N_P}{N_S}*\frac{T_{\mathrm{demag}}}{T_{\mathrm{on}}+T_{\mathrm{demag}}+T_{\mathrm{dis}}}$

$=\frac{1}{2}*\frac{V_{\mathrm{CS}}}{R8}*\frac{N_P}{N_S}*\frac{T_{\mathrm{demag}}}{T_{\mathrm{on}}+T_{\mathrm{demag}}+T_{\mathrm{dis}}}$

$=\frac{1}{2}*\frac{V_{\mathrm{avg}}}{R8}*\frac{N_P}{N_S}$

(formula 6)

By formula 6 as can be seen, in fact the magnitude of voltage Vavg ofsignal 441 is directly proportional with output current.

According to an example in shown in Figure 4, signal 441 and Vref2enter error amplifier 450 together, output error amplifying signal 451.In another example,error amplification signal 451 enterscomparator 452 withtriangular signal 434, and output comparison signal 453.Whentriangular signal 434 magnitudes of voltage surpassederror amplification signal 451, comparison signal 453 became high level.In another example, signal 453 becomes high level, pass through so or thedoor 462 after,output signal 463 becomes high level.According to another example, signal 463 high level trigger rest-set flip-flop 464, andoutput signal 465 becomes low level.In another example, signal 465 levelenter driver module 466, and output signal 367 on-offswitching tubes 487.

With reference to system shown in Figure 4, when output current strengthens gradually, the magnitude of voltage Vavg of theoutput signal 441 of currentsample computing module 440 strengthens gradually, when Vavg equals Vref2, form feedback control loop, by turning on and off ofcontrol switch pipe 487, make Vavg no longer increase, thereby the restriction output current plays the effect of constant output electric current.

At last, it is also noted that what more than give an example only is certain specific embodiment of the present invention.Obviously, the invention is not restricted to above embodiment, many distortion can also be arranged.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention all should be thought protection scope of the present invention.

Claims (2)

1. constant current constant voltage formula inverse excitation type converter based on former limit feedback, comprise: rectifier bridge (470), ∏ mode filter (471), absorb circuit (472), by elementary winding (480), the transformer (473) that secondary winding (481) and auxiliary winding (482) constitute, constant-current constant-voltage controller (479) and switching tube (487), described secondary winding (481) also is connected with secondary circuit (494), described auxiliary winding (482) also is connected with auxiliary power supply circuit (474), the base stage of described switching tube (487) is connected with the output of constant-current constant-voltage controller (479), the collector electrode of switching tube (487) is connected with elementary winding (480), the emitter of switching tube (487) is by primary current sampling resistor (488) ground connection, it is characterized in that, described constant-current constant-voltage controller (479) comprises constant voltage module (490), frequency generator (491), constant flow module (492), or door (462), rest-set flip-flop (464) and driver module (466), the input of described constant voltage module (490) is used for the voltage voltage division signal (400) of the auxiliary winding (482) of sampling, first of the output of constant voltage module (490) and constant flow module (492), second output respectively with or three inputs of door (462) are connected and for first cut-off signals (415), second cut-off signals (453) and the 3rd cut-off signals (461) be sent to respectively or the door (462) three inputs, the input of constant flow module (492) is connected the current signal (401) that is used for the elementary winding of sampling (480) with the emitter of described switching tube (487), the R end of outputs and the rest-set flip-flop (464) of described or door (462) is connected and be used for will or the cut-off signals (463) of door (462) generation R that is sent to rest-set flip-flop (464) hold, the input of described frequency generator (491) is used for sampling and receives the voltage voltage division signal (400) of auxiliary winding (482), frequency generator (491) produces opens signal (432) and exports the S end of rest-set flip-flop (464) to, described rest-set flip-flop (464) is used for receiving opens signal (432) and cut-off signals (463), generate modulation signal (465), the Q end of rest-set flip-flop (464) is connected with the input of driver module (466), described driver module (466) is used for receiving modulation signal (465), and to described switching tube (487) output drive signal (467).

2. the constant current constant voltage formula inverse excitation type converter based on former limit feedback according to claim 1, it is characterized in that, described frequency generator (491) comprises degaussing detection module (420), time delay module (430) and triangular-wave generator (433), the input of degaussing detection module (420) is as the input of frequency generator (491), the output degaussing time signal (421) of degaussing detection module (420), degaussing time signal (421) enters time delay module (430), open signal (432) and second through time-delay back generation first and open signal (431), first opens signal (432) is delivered to S end with rest-set flip-flop (464) as the output signal of frequency generator (491) output by described frequency generator (491), triangular-wave generator (433) receives second and opens signal (431), generates triangular signal (434);

Described constant voltage module (490) comprises that sampling keeps module (410), first error amplifier (412), first comparator (414), sampling keeps the input of module (410) as the input of constant voltage module (490), sampling keeps the output signal (411) of module (410) to enter first error amplifier (412), and generation first threshold signal (413), first threshold signal (413) and enter first comparator (414) by the triangular signal (434) that described triangular-wave generator (433) generates generates first cut-off signals (415) and as constant voltage module (490) output signal;

Described constant flow module (492) comprises current sample computing module (440), second error amplifier (450), second comparator (452) and the 3rd comparator (460), current sample computing module (440) also is used for the current signal (401) of the elementary winding of sampling (480) as the input of constant flow module (492), enter second error amplifier (450) through the output signal after calculating, generate second threshold signal (451), second threshold signal (451) and the triangular signal (434) that is generated by described triangular-wave generator (433) enter second comparator (452), and generate second cut-off signals (453), simultaneously, primary winding current signal (401) enters the 3rd comparator (460), generates the 3rd cut-off signals (461).

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