CN103187489A

Movatterモバイル変換

Info

Publication number: CN103187489A
Application number: CN2011104505529A
Authority: CN
Inventors: 林厚德; 张超雄
Original assignee: Rongchuang Energy Technology Co ltd; Zhanjing Technology Shenzhen Co Ltd
Current assignee: Rongchuang Energy Technology Co ltd; Zhanjing Technology Shenzhen Co Ltd
Priority date: 2011-12-29
Filing date: 2011-12-29
Publication date: 2013-07-03
Also published as: TWI467809B; TW201327930A

Abstract

本发明提供一种半导体封装制程及其封装结构，其包括以下的步骤；首先，提供一个基板，在所述基板上设置一个凹槽以及至少二个穿孔，接着，设置一个电路结构在所述凹槽内，所述电路结构包括一个第一电极以及一个第二电极，并通过所述穿孔在所述基板底面形成一个第一外部电极以及一个第二外部电极，然后，形成一个第一透明层在所述凹槽内，通过可移除的一个阻挡层在所述第一透明层形成一个凹部，并使所述凹部位于所述第一、二电极之间，然后，设置一个LED芯片在所述凹部，使所述LED芯片与所述电路结构达成电性连接，最后，形成一个封装层，所述封装层包括一个荧光层以及一个第二透明层，所述荧光层覆盖所述LED芯片，所述第二透明层覆盖所述荧光层。本发明并提供所述半导体封装结构。

The present invention provides a semiconductor packaging process and its packaging structure, which includes the following steps: firstly, a substrate is provided, and a groove and at least two through holes are arranged on the substrate, and then, a circuit structure is arranged in the concave In the groove, the circuit structure includes a first electrode and a second electrode, and a first external electrode and a second external electrode are formed on the bottom surface of the substrate through the through hole, and then a first transparent layer is formed on the bottom surface of the substrate In the groove, a recess is formed on the first transparent layer through a removable barrier layer, and the recess is located between the first and second electrodes, and then, an LED chip is arranged on the The concave part makes the LED chip and the circuit structure electrically connected, and finally, forms an encapsulation layer, the encapsulation layer includes a fluorescent layer and a second transparent layer, and the fluorescent layer covers the LED chip, so The second transparent layer covers the fluorescent layer. The invention also provides the semiconductor packaging structure.

Description

Semiconductor packing process and encapsulating structure thereof

Technical field

The present invention relates to a kind of semiconductor packing process and encapsulating structure thereof, relate in particular to semiconductor packing process and encapsulating structure thereof that a kind of mode with conformal coating (Conformal coating) forms fluorescence coating.

Background technology

The LED industry is one of industry that attracted most attention in recent years, development so far, that the LED product has had is energy-conservation, power saving, high efficiency, the reaction time is fast, the life cycle time is long and not mercurous, have advantage such as environmental benefit.Yet because the encapsulation procedure of LED structure can directly have influence on its serviceability and life-span, for example aspect optics control, can improve light extraction efficiency and optimize beam distribution by encapsulation procedure.At present on led chip, in a glue mode sealing that blending has fluorescent material is set, though described colloid and described fluorescent material are to have the effect of the LED of raising luminous efficiency, but because shape and the thickness of described the described sealing of the difficult control of glue mode, will cause the color of LED bright dipping inconsistent, inclined to one side blue light or inclined to one side gold-tinted occur.The unmanageable problem of the shape of relevant described sealing and thickness can solve by the mode with model, but can increase processing procedure and cost like this.In addition, described fluorescent material sealing is directly coated on the led chip, can make light extraction efficiency lower owing to have the problem of light scattering.So how from semi-conductive encapsulation procedure, to make the color of bright dipping more even, need continue to study improvement.

Summary of the invention

In view of this, be necessary to provide a kind of semiconductor packing process and encapsulating structure thereof of conformal coating.

A kind of semiconductor packing process, it comprises the steps;

A substrate is provided, at described substrate a groove and at least two perforation is set,

A circuit structure is set in described groove, described circuit structure comprises first electrode and second electrode, and forms first outer electrode and second outer electrode by described perforation in described substrate bottom surface,

Form first hyaline layer in described groove, form a recess by a removable barrier layer at described first hyaline layer, and make described recess between described first and second electrode,

A led chip is set at described recess, makes described led chip and described circuit structure reach electric connection, and

Form an encapsulated layer, described encapsulated layer comprises a fluorescence coating and second hyaline layer, and described fluorescence coating covers described led chip, and described second hyaline layer covers described fluorescence coating.

In the above-mentioned semiconductor packing process, because the described recess of described first hyaline layer is formed between first and second interior electrode of described substrate recess, described led chip can be reached electric connection at described recess and described circuit structure, and the described fluorescence coating that covers described led chip arranges in described recess, make described fluorescence coating have the structure of conformal coating, it is more even to make described semiconductor encapsulated element go out light color by the described fluorescence layer structure of conformal coating.

Description of drawings

Fig. 1 is the flow chart of steps of semiconductor packing process of the present invention.

Fig. 2 is the cutaway view that corresponding diagram 1 provides a substrate step.

Fig. 3 is the cutaway view that corresponding diagram 1 arranges a circuit structure step.

Fig. 4 is the cutaway view that corresponding diagram 1 forms first a hyaline layer step.

Fig. 5 is the cutaway view that corresponding diagram 1 arranges a led chip step.

Fig. 6 is the cutaway view that corresponding diagram 1 forms the semiconductor package of an encapsulated layer step.

The main element symbol description

Semiconductor package	10
		Substrate	12
End face	120a
		Thebottomsurface	120b
Groove
		122
Perforation			124
	Circuit structure	14
First electrode			142
	Second electrode	144
Firstouter electrode			146
	Secondouter electrode	148
Firsthyaline layer			15
	Thebarrier layer	152
Recess			154
	Ledchip	16
Encapsulatedlayer			18
	Fluorescence coating	182
Secondhyaline layer			184

Following embodiment will further specify the present invention in conjunction with above-mentioned accompanying drawing.

Embodiment

Below in conjunction with accompanying drawing the present invention being done one specifically introduces.

See also Fig. 1, be depicted as the flow chart of steps of semiconductor packing process of the present invention, it comprises the steps;

S11 provides a substrate, at described substrate a groove and at least two perforation is set,

S12 arranges a circuit structure in described groove, and described circuit structure comprises first electrode and second electrode, and forms first outer electrode and second outer electrode by described perforation in described substrate bottom surface,

S13 forms first hyaline layer in described groove, and form a recess by a removable barrier layer at described first hyaline layer, and make described recess between described first and second electrode,

S14 arranges a led chip at described recess, makes described led chip and described circuit structure reach electric connection, and

S15 forms an encapsulated layer, and described encapsulated layer comprises a fluorescence coating and second hyaline layer, and described fluorescence coating covers described led chip, and described second hyaline layer covers described fluorescence coating.

Described step S11 provides asubstrate 12, at describedsubstrate 12groove 122 and at least twoperforation 124 are set, describedsubstrate 12 comprises anend face 120a and abottom surface 120b, describedgroove 122 is arranged on theend face 120a of describedsubstrate 12, and describedperforation 124 runs through describedsubstrate 12 to describedbottom surface 120b (as shown in Figure 2) in described groove 122.Describedsubstrate 12 materials can be pottery (Ceramic) material or silicon (Si) material, and wherein silicon (Si)material substrate 12 is convenient to the follow-up manufacturing of carrying out micro electronmechanical processing procedure, helps the raising of precision.

Described step S12 arranges acircuit structure 14 in describedgroove 122, describedcircuit structure 14 comprisesfirst electrode 142 andsecond electrode 144, and form firstouter electrode 146 and secondouter electrode 148 by describedperforation 124 at describedsubstrate bottom surface 120b, described first and second electrode 142,144 is oppositely arranged (as shown in Figure 3) in the bottom of describedgroove 122, and extend to thebottom surface 120b of describedsubstrate 12 respectively by describedperforation 124, form described first and second outer electrode 146,148.

Described step S13 formsfirst hyaline layer 15 in describedgroove 122, form arecess 154 by aremovable barrier layer 152 at describedfirst hyaline layer 15, and make describedrecess 154 be positioned at described first, between two electrodes 142,144, describedbarrier layer 152 is as described in a mould or a photoresist layer (shown in the dotted line position of Fig. 4) are arranged on first, between two electrodes 142,144, describedfirst hyaline layer 15 is centered around around the describedbarrier layer 152 and is positioned at the bottom of describedgroove 122, the height of describedfirst hyaline layer 15 less than or equal describedbarrier layer 152 height.After describedfirst hyaline layer 15 solidifies, can carry out the running that removes on describedbarrier layer 152, will be between described first and second electrode at 152 places, described barrier layer after describedbarrier layer 152 removes 142,144 form described recess 154.If describedbarrier layer 152 moulds can directly remove, if describedbarrier layer 152 photoresist layers then can use etched mode to remove.In addition, form on the mode of arecess 154 at describedfirst hyaline layer 15, except above-mentioned removable describedbarrier layer 152 modes, can directly utilize the mode of pressurising to form described recess 154.That is, directly form describedfirst hyaline layer 15 earlier on the describedcircuit structure 14 of describedgroove 122 bottoms, 142,144 modes with pressurising form describedrecess 154 between described first and second electrode of describedcircuit structure 14 then.

Described step S14 arranges aled chip 16 at describedrecess 154, make described ledchip 16 reach electric connection with describedcircuit structure 14, describedrecess 154 is owing to be formed between described first and second electrode of describedcircuit structure 14 142,144, therefore, described ledchip 16 can directly be arranged on described first and second electrode 142,144 by describedrecess 154, see also shown in Figure 5, thereby described ledchip 16 is reached electric connection with described circuit structure 14.Described ledchip 16 and described first and second electrode 142,144 electric connection can routing (Wire Bonding) be covered crystalline substance (Flip Chip) or eutectic (Eutectic) mode is reached.

At last, described step S15 forms anencapsulated layer 18, described encapsulatedlayer 18 comprises afluorescence coating 182 and secondhyaline layer 184, describedfluorescence coating 182 covers described ledchip 16, describedsecond hyaline layer 184 covers describedfluorescence coating 182, describedfluorescence coating 182 covers described ledchip 16 at describedrecess 154, and makes cover height identical with described first hyaline layer 15.Describedfluorescence coating 182 in describedrecess 154 to the covering fully of described ledchip 16 outsides, thereby form the mode of conformal coating (Conformal coating), it is more even to make semiconductor element go out light color.Describedsecond hyaline layer 184 covers describedfluorescence coating 182 and comprises described ledchip 16 and described first hyaline layer 15 (as shown in Figure 6).A fluorescence coating (not indicating among the figure) can be set in addition again, in order to promote the light output of semiconductor element in described second hyaline layer 184.The refractive index of described secondhyaline layer 184 is less than the refractive index of describedfluorescence coating 18 and describedfirst hyaline layer 15.

The semiconductor package 10 that above-mentioned semiconductor packing process is made comprises asubstrate 12, acircuit structure 14,first hyaline layer 15, aled chip 16 and an encapsulated layer 18.Have agroove 122 and at least twoperforation 124 on the describedsubstrate 12, describedcircuit structure 14 is arranged in the describedgroove 122, describedcircuit structure 14 comprisesfirst electrode 142 andsecond electrode 144, and described first and second electrode 142,144 forms firstouter electrode 146 and secondouter electrode 148 by describedperforation 124 at described substrate bottom surface 120b.Describedfirst hyaline layer 15 is arranged on the bottom of describedgroove 122, and between described first and second electrode 142,144, has arecess 154, described ledchip 16 is set in the describedrecess 154, described ledchip 16 electrically connects with described first and second electrode 142,144, describedencapsulated layer 18 comprises afluorescence coating 182 and secondhyaline layer 184, describedfluorescence coating 182 covers described ledchip 16, and describedsecond hyaline layer 184 covers described fluorescence coating 182.Make describedfluorescence coating 182 cover the outside of described ledchip 16 by describedrecess 154, it is more even to make described semiconductor package 10 go out light color.

To sum up, semiconductor packing process of the present invention, describedcircuit structure 14 is set in the describedgroove 122 of describedsubstrate 12, form describedfirst hyaline layer 15 and have describedrecess 154 settings at describedcircuit structure 14, can make described ledchip 16 electrically connect describedcircuit structure 14 by describedrecess 154, make describedfluorescence coating 182 be covered in the outside of described ledchip 16 simultaneously, have that processing procedure is simple, cost is low, can effectively promote semiconductor package goes out the uniform usefulness of light color.

In addition, those skilled in the art also can do other variation in spirit of the present invention, and certainly, the variation that these are done according to spirit of the present invention all should be included within the present invention's scope required for protection.