技术领域technical field
本发明涉及射频技术领域，尤其涉及一种提供时钟信号的方法、装置及频谱分析仪。The invention relates to the field of radio frequency technology, in particular to a method, device and spectrum analyzer for providing a clock signal.
背景技术Background technique
在射频通讯领域，数字电路与射频模拟电路共存一个系统的时代在继续而且仍将继续，这种情况下，数字电路干扰模拟电路也仍将继续。尤其是在射频接收电路中，射频前端灵敏度高，而接收的有用信号很微弱，很容易被数字电路的开关高次谐波所干扰，而数字部分电路的干扰是不可预知的，即干扰是非相关的，所以通常在电路设计过程中，将数字电路和射频模拟电路在物理上相互隔开，如将整个射频系统分为数字电路板和射频电路板，因为物理隔离的原因，两块板也各自用了各自的时钟，市场上现有的DSA1030系列频谱仪就使用了此结构。In the field of radio frequency communication, the era in which digital circuits and radio frequency analog circuits coexist in one system continues and will continue. In this case, digital circuits will continue to interfere with analog circuits. Especially in the radio frequency receiving circuit, the radio frequency front-end sensitivity is high, but the useful signal received is very weak, and it is easy to be interfered by the switching high-order harmonics of the digital circuit, and the interference of the digital part circuit is unpredictable, that is, the interference is non-correlated Therefore, usually in the circuit design process, the digital circuit and the RF analog circuit are physically separated from each other. For example, the entire RF system is divided into a digital circuit board and an RF circuit board. Because of physical isolation, the two boards are also separate. With their own clocks, the existing DSA1030 series spectrum analyzers on the market use this structure.
如图1所示，为现有的DSA1030频谱分析仪系统时钟框图，分为射频电路板1和数字电路板2，射频电路板1射频电路同步于一个时钟11，而数字电路板2的器件由于数据处理或传输速率的不同分别使用不同的时钟，如数据处理单元122使用时钟12，而外设132使用时钟13，外设142使用时钟14，在DSA1030中像数据处理单元122就使用了DSP(Digital SignalProcessing，数字信号处理)，需要25MHz的时钟，外设132为USB(Universal Serial BUS，通用串行总线)接口芯片需要12MHz的时钟信号，外设142为以太网接口芯片需要25MHz的时钟信号，他们均使用了频率稳定度较差的无源晶振。物理的隔离使射频电路板1与数字电路板2彼此隔离，时钟也彼此独立，这样的好处是各个时钟与其作用器件的物理间距减小，时钟PCB(Printed Circuit Board，印刷电路板)连线缩短。As shown in Figure 1, it is a clock block diagram of the existing DSA1030 spectrum analyzer system, which is divided into a radio frequency circuit board 1 and a digital circuit board 2. The radio frequency circuit of the radio frequency circuit board 1 is synchronized with a clock 11, and the devices of the digital circuit board 2 are due to The difference of data processing or transmission rate uses different clocks respectively, as data processing unit 122 uses clock 12, and peripheral hardware 132 uses clock 13, and peripheral hardware 142 uses clock 14, in DSA1030 just used DSP like data processing unit 122 ( Digital SignalProcessing, digital signal processing), need the clock of 25MHz, peripheral hardware 132 needs the clock signal of 12MHz for the USB (Universal Serial BUS, universal serial bus) interface chip, peripheral hardware 142 needs the clock signal of 25MHz for the Ethernet interface chip, They all use passive crystal oscillators with poor frequency stability. Physical isolation isolates the RF circuit board 1 and the digital circuit board 2 from each other, and the clocks are also independent from each other. The advantage of this is that the physical distance between each clock and its active device is reduced, and the clock PCB (Printed Circuit Board, printed circuit board) connection is shortened. .
当然物理上的隔离能够很好的阻止数字电路干扰模拟电路，但是对于体积较小的射频设备来说，这种物理上的隔离所带来的成本和体积的增加是难以容忍的，还增加了装配难度。当射频电路与数字电路相互通讯时还会出现由于电路两边时钟不同步而出现通讯信号的不同步问题。Of course, physical isolation can prevent digital circuits from interfering with analog circuits, but for small radio frequency equipment, the increase in cost and volume caused by this physical isolation is intolerable, and it also increases Assembly difficulty. When the radio frequency circuit and the digital circuit communicate with each other, there will be a problem of asynchronous communication signals due to the asynchronous clocks on both sides of the circuit.
数字信号的时钟干扰信号混入模拟电路后，由于数字时钟相位噪声劣于模拟时钟，所以两者相互叠加致使最终信号相位噪声变差。After the clock interference signal of the digital signal is mixed into the analog circuit, since the phase noise of the digital clock is worse than that of the analog clock, the two superimpose on each other to make the phase noise of the final signal worse.
综上，对于数字电路与射频电路之间的干扰问题和同步问题，目前亟需解决方案。To sum up, there is an urgent need for solutions to the interference and synchronization problems between digital circuits and radio frequency circuits.
发明内容Contents of the invention
本发明实施例提供一种提供时钟信号的方法、装置及频谱分析仪，以解决数字电路与射频电路之间的干扰问题和同步问题。Embodiments of the present invention provide a method, device and spectrum analyzer for providing a clock signal, so as to solve the interference and synchronization problems between digital circuits and radio frequency circuits.
一方面，本发明实施例提供了一种提供时钟信号的方法，所述方法应用于同时存在射频电路和数字电路的装置，所述方法包括：提供一个系统时钟；获取所述系统时钟发出的时钟信号；将所述时钟信号的一路发送给所述射频电路使用，并将所述时钟信号的另一路发送给所述数字电路使用。On the one hand, an embodiment of the present invention provides a method for providing a clock signal, and the method is applied to a device with both radio frequency circuits and digital circuits, and the method includes: providing a system clock; obtaining a clock signal sent by the system clock Signal; sending one of the clock signals to the radio frequency circuit for use, and sending the other clock signal to the digital circuit for use.
可选的，在本发明的一实施例中，所述获取所述系统时钟发出的时钟信号，包括：通过多个时钟驱动电路，将所述时钟信号分出多个同频的时钟信号。Optionally, in an embodiment of the present invention, the acquiring the clock signal sent by the system clock includes: splitting the clock signal into multiple clock signals of the same frequency through multiple clock driving circuits.
可选的，在本发明的一实施例中，所述将所述时钟信号的一路发送给所述射频电路使用，包括：将分出的多个同频的时钟信号经锁相环及混频器进行频率合成，获得供所述射频电路使用的时钟信号。Optionally, in an embodiment of the present invention, the sending one of the clock signals to the radio frequency circuit includes: passing multiple separated clock signals of the same frequency through a phase-locked loop and frequency mixing The frequency synthesizer is used to obtain the clock signal used by the radio frequency circuit.
可选的，在本发明的一实施例中，所述将所述时钟信号的另一路发送给所述数字电路使用，包括：将分出的另一个时钟信号依次经过时钟整形电路、时钟传输通道、时钟接收电路后，通过频率合成转变为供所述数字电路的各个单元使用的时钟信号。Optionally, in an embodiment of the present invention, the sending another channel of the clock signal to the digital circuit includes: passing the other clock signal through a clock shaping circuit and a clock transmission channel in sequence 1. After the clock receiving circuit, it is converted into a clock signal used by each unit of the digital circuit through frequency synthesis.
可选的，在本发明的一实施例中，所述通过频率合成转变为供所述数字电路的各个单元使用的时钟信号，包括：利用所述数字电路的数据处理单元中的现场可编程门阵列FPGA自带的锁相环PLL，通过频率合成转变为供所述数字电路的各个单元使用的时钟信号。Optionally, in an embodiment of the present invention, converting the clock signal used by each unit of the digital circuit through frequency synthesis includes: using a field programmable gate in the data processing unit of the digital circuit The phase-locked loop PLL of the array FPGA is converted into a clock signal used by each unit of the digital circuit through frequency synthesis.
可选的，在本发明的一实施例中，所述时钟整形电路通过低通滤波器或带通滤波器实现。Optionally, in an embodiment of the present invention, the clock shaping circuit is implemented by a low-pass filter or a band-pass filter.
可选的，在本发明的一实施例中，当所述射频电路和所述数字电路在同一个电路板上同时存在时，所述时钟传输通道通过印刷电路板PCB微带线，或光耦传输，或磁耦传输实现；当所述射频电路和所述数字电路不在同一个电路板上同时存在时，所述时钟传输通道通过同轴线缆实现。Optionally, in an embodiment of the present invention, when the radio frequency circuit and the digital circuit coexist on the same circuit board, the clock transmission channel passes through the printed circuit board PCB microstrip line, or an optocoupler transmission, or magnetic coupling transmission; when the radio frequency circuit and the digital circuit do not exist on the same circuit board at the same time, the clock transmission channel is realized through a coaxial cable.
可选的，在本发明的一实施例中，所述时钟接收电路对经过的时钟信号进行倍频处理。Optionally, in an embodiment of the present invention, the clock receiving circuit performs frequency multiplication processing on the passed clock signal.
另一方面，本发明实施例提供了一种提供时钟信号的装置，所述装置为同时存在射频电路和数字电路的装置，所述装置只包括一个系统时钟，用于发出时钟信号，该系统时钟将所述时钟信号的一路发送给所述射频电路使用，并将所述时钟信号的另一路发送给所述数字电路使用。On the other hand, an embodiment of the present invention provides a device for providing a clock signal. The device is a device in which a radio frequency circuit and a digital circuit exist at the same time. The device only includes a system clock for sending a clock signal. The system clock One of the clock signals is sent to the radio frequency circuit for use, and the other clock signal is sent to the digital circuit for use.
可选的，在本发明的一实施例中，所述装置还包括：多个时钟驱动电路，用于将所述时钟信号分出多个同频的时钟信号。Optionally, in an embodiment of the present invention, the device further includes: multiple clock driving circuits, configured to divide the clock signal into multiple clock signals of the same frequency.
可选的，在本发明的一实施例中，所述射频电路包括：锁相环及混频器，用于将分出的多个同频的时钟信号经锁相环及混频器进行频率合成，获得供所述射频电路使用的时钟信号。Optionally, in an embodiment of the present invention, the radio frequency circuit includes: a phase-locked loop and a mixer, which are used to perform frequency conversion of multiple divided clock signals of the same frequency through the phase-locked loop and the mixer. and synthesizing to obtain a clock signal used by the radio frequency circuit.
可选的，在本发明的一实施例中，所述数字电路包括时钟整形电路、时钟传输通道、时钟接收电路、频率合成单元，用于将分出的另一个时钟信号依次经过时钟整形电路、时钟传输通道、时钟接收电路后，通过频率合成单元转变为供所述数字电路的各个单元使用的时钟信号。Optionally, in an embodiment of the present invention, the digital circuit includes a clock shaping circuit, a clock transmission channel, a clock receiving circuit, and a frequency synthesizing unit, which are used to sequentially pass another split clock signal through the clock shaping circuit, After the clock transmission channel and the clock receiving circuit, it is transformed into a clock signal used by each unit of the digital circuit through the frequency synthesis unit.
可选的，在本发明的一实施例中，所述频率合成单元，具体用于利用所述数字电路的数据处理单元中的现场可编程门阵列FPGA自带的锁相环PLL，通过频率合成转变为供所述数字电路的各个单元使用的时钟信号。Optionally, in an embodiment of the present invention, the frequency synthesis unit is specifically configured to use the phase-locked loop PLL that comes with the field programmable gate array FPGA in the data processing unit of the digital circuit to perform frequency synthesis Converted to a clock signal used by the various units of the digital circuit.
可选的，在本发明的一实施例中，所述时钟整形电路通过低通滤波器或带通滤波器实现。Optionally, in an embodiment of the present invention, the clock shaping circuit is implemented by a low-pass filter or a band-pass filter.
可选的，在本发明的一实施例中，当所述射频电路和所述数字电路在同一个电路板上同时存在时，所述时钟传输通道通过印刷电路板PCB微带线，或光耦传输，或磁耦传输实现；当所述射频电路和所述数字电路不在同一个电路板上同时存在时，所述时钟传输通道通过同轴线缆实现。Optionally, in an embodiment of the present invention, when the radio frequency circuit and the digital circuit coexist on the same circuit board, the clock transmission channel passes through the printed circuit board PCB microstrip line, or an optocoupler transmission, or magnetic coupling transmission; when the radio frequency circuit and the digital circuit do not exist on the same circuit board at the same time, the clock transmission channel is realized through a coaxial cable.
可选的，在本发明的一实施例中，所述时钟接收电路对经过的时钟信号进行倍频处理。Optionally, in an embodiment of the present invention, the clock receiving circuit performs frequency multiplication processing on the passed clock signal.
再一方面，本发明实施例提供了一种频谱分析仪，所述频谱分析仪包括上述提供时钟信号的装置。In yet another aspect, an embodiment of the present invention provides a spectrum analyzer, where the spectrum analyzer includes the above-mentioned device for providing a clock signal.
上述技术方案具有如下有益效果：因为采用了一种提供时钟信号的装置，所述装置为同时存在射频电路和数字电路的装置，所述装置只包括一个系统时钟，用于发出时钟信号；将所述时钟信号的一路发送给所述射频电路使用，并将所述时钟信号的另一路发送给所述数字电路使用的技术手段，所以可以解决数字电路与射频电路之间的干扰问题和同步问题。特别是解决了宽频带接收机领域中的数字电路与射频电路集成于同一电路板所带来的干扰问题和同步问题，而且一个时钟也使得电路设计大大简化，节省成本。同一时钟信号使得整个系统各个时钟相关，这样可以通过软件处理去除与输入信号无关的杂散信号。射频时钟信号质量一般要优于数字时钟，所以采用同一时钟同步后可以提高整个系统频率分辨率。The above technical solution has the following beneficial effects: because a device for providing a clock signal is adopted, the device is a device in which a radio frequency circuit and a digital circuit exist at the same time, and the device only includes a system clock for sending out a clock signal; One way of the clock signal is sent to the radio frequency circuit, and the other way of the clock signal is sent to the digital circuit, so the interference and synchronization problems between the digital circuit and the radio frequency circuit can be solved. In particular, it solves the interference and synchronization problems caused by the integration of digital circuits and radio frequency circuits on the same circuit board in the field of broadband receivers, and one clock also greatly simplifies circuit design and saves costs. The same clock signal makes the clocks of the whole system related, so that the spurious signals that have nothing to do with the input signal can be removed through software processing. The quality of the radio frequency clock signal is generally better than that of the digital clock, so the frequency resolution of the entire system can be improved after the same clock is used for synchronization.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1为现有的DSA1030频谱分析仪系统时钟框图；Fig. 1 is the clock block diagram of existing DSA1030 spectrum analyzer system;
图2为本发明实施例一种提供时钟信号的方法流程图；FIG. 2 is a flowchart of a method for providing a clock signal according to an embodiment of the present invention;
图3为本发明实施例一种提供时钟信号的装置结构示意图；3 is a schematic structural diagram of a device for providing a clock signal according to an embodiment of the present invention;
图4为本发明实施例一种频谱分析仪结构示意图；Fig. 4 is a schematic structural diagram of a spectrum analyzer according to an embodiment of the present invention;
图5为本发明实施例时钟驱动电路的第一设计示意图；5 is a schematic diagram of a first design of a clock drive circuit according to an embodiment of the present invention;
图6为本发明实施例时钟驱动电路的第二设计示意图；6 is a schematic diagram of a second design of a clock drive circuit according to an embodiment of the present invention;
图7为本发明实施例时钟驱动电路的第三设计示意图；7 is a schematic diagram of a third design of a clock drive circuit according to an embodiment of the present invention;
图8为本发明实施例时钟整形电路的第一设计示意图；FIG. 8 is a schematic diagram of a first design of a clock shaping circuit according to an embodiment of the present invention;
图9为本发明实施例时钟整形电路的第二设计示意图；9 is a schematic diagram of a second design of a clock shaping circuit according to an embodiment of the present invention;
图10为本发明实施例对时钟信号进行倍频处理的电路设计示意图。FIG. 10 is a schematic diagram of a circuit design for performing frequency multiplication processing on a clock signal according to an embodiment of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
如图2所示，为本发明实施例一种提供时钟信号的方法流程图，所述方法应用于同时存在射频电路和数字电路的装置，所述方法包括：As shown in FIG. 2, it is a flow chart of a method for providing a clock signal according to an embodiment of the present invention. The method is applied to a device in which a radio frequency circuit and a digital circuit exist at the same time. The method includes:
201、提供一个系统时钟；201. Provide a system clock;
202、获取所述系统时钟发出的时钟信号；202. Obtain a clock signal sent by the system clock;
203、将所述时钟信号的一路发送给所述射频电路使用，并将所述时钟信号的另一路发送给所述数字电路使用。203. Send one path of the clock signal to the radio frequency circuit for use, and send the other path of the clock signal to the digital circuit for use.
可选的，所述获取所述系统时钟发出的时钟信号，可以包括：通过多个时钟驱动电路，将所述时钟信号分出多个同频的时钟信号。Optionally, the acquiring the clock signal sent by the system clock may include: splitting the clock signal into multiple clock signals of the same frequency through multiple clock driving circuits.
可选的，所述将所述时钟信号的一路发送给所述射频电路使用，可以包括：将分出的多个同频的时钟信号经锁相环及混频器进行频率合成，获得供所述射频电路使用的时钟信号。Optionally, the sending one of the clock signals to the radio frequency circuit may include: performing frequency synthesis on a plurality of separated clock signals of the same frequency through a phase-locked loop and a mixer to obtain The clock signal used by the RF circuit described above.
可选的，所述将所述时钟信号的另一路发送给所述数字电路使用，可以包括：将分出的另一个时钟信号依次经过时钟整形电路、时钟传输通道、时钟接收电路后，通过频率合成转变为供所述数字电路的各个单元使用的时钟信号。Optionally, the sending the other channel of the clock signal to the digital circuit for use may include: passing the other clock signal through the clock shaping circuit, the clock transmission channel, and the clock receiving circuit in sequence, and passing the frequency A clock signal converted into a clock signal for use by various units of the digital circuit is synthesized.
可选的，所述通过频率合成转变为供所述数字电路的各个单元使用的时钟信号，可以包括：利用所述数字电路的数据处理单元中的现场可编程门阵列FPGA自带的锁相环PLL，通过频率合成转变为供所述数字电路的各个单元使用的时钟信号。Optionally, the conversion into a clock signal used by each unit of the digital circuit through frequency synthesis may include: using a phase-locked loop of a field programmable gate array FPGA in the data processing unit of the digital circuit The PLL is converted into a clock signal used by each unit of the digital circuit through frequency synthesis.
可选的，所述时钟整形电路可以通过低通滤波器或带通滤波器实现。Optionally, the clock shaping circuit may be implemented by a low-pass filter or a band-pass filter.
可选的，当所述射频电路和所述数字电路在同一个电路板上同时存在时，所述时钟传输通道通过印刷电路板PCB微带线，或光耦传输，或磁耦传输实现；当所述射频电路和所述数字电路不在同一个电路板上同时存在时，所述时钟传输通道通过同轴线缆实现。Optionally, when the radio frequency circuit and the digital circuit exist on the same circuit board at the same time, the clock transmission channel is implemented through a printed circuit board PCB microstrip line, or optocoupler transmission, or magnetic coupling transmission; when When the radio frequency circuit and the digital circuit do not exist on the same circuit board at the same time, the clock transmission channel is implemented through a coaxial cable.
可选的，所述时钟接收电路可以对经过的时钟信号进行倍频处理。Optionally, the clock receiving circuit may perform frequency multiplication processing on the passed clock signal.
本发明上述方法技术方案可以解决数字电路与射频电路之间的干扰问题和同步问题。特别是解决了宽频带接收机领域中的数字电路与射频电路集成于同一电路板所带来的干扰问题和同步问题，而且一个时钟也使得电路设计大大简化，节省成本。同一时钟信号使得整个系统各个时钟相关，这样可以通过软件处理去除与输入信号无关的杂散信号。射频时钟信号质量一般要优于数字时钟，所以采用同一时钟同步后可以提高整个系统频率分辨率。The technical scheme of the above method of the present invention can solve the interference problem and synchronization problem between the digital circuit and the radio frequency circuit. In particular, it solves the interference and synchronization problems caused by the integration of digital circuits and radio frequency circuits on the same circuit board in the field of broadband receivers, and one clock also greatly simplifies circuit design and saves costs. The same clock signal makes the clocks of the whole system related, so that the spurious signals that have nothing to do with the input signal can be removed through software processing. The quality of the radio frequency clock signal is generally better than that of the digital clock, so the frequency resolution of the entire system can be improved after the same clock is used for synchronization.
对应于上述方法实施例，如图3所示，为本发明实施例一种提供时钟信号的装置结构示意图，所述装置为同时存在射频电路32和数字电路33的装置，所述装置只包括一个系统时钟31，用于发出时钟信号，该系统时钟31将所述时钟信号的一路发送给所述射频电路32使用，并将所述时钟信号的另一路发送给所述数字电路33使用。Corresponding to the above-mentioned method embodiment, as shown in FIG. 3 , it is a schematic structural diagram of a device for providing a clock signal according to an embodiment of the present invention. The device is a device in which a radio frequency circuit 32 and a digital circuit 33 exist at the same time, and the device includes only one The system clock 31 is used to send a clock signal. The system clock 31 sends one of the clock signals to the radio frequency circuit 32 for use, and sends the other clock signal to the digital circuit 33 for use.
可选的，所述装置还包括：多个时钟驱动电路，用于将所述时钟信号分出多个同频的时钟信号。Optionally, the device further includes: multiple clock driving circuits, configured to split the clock signal into multiple clock signals of the same frequency.
可选的，所述射频电路包括：锁相环及混频器，用于将分出的多个同频的时钟信号经锁相环及混频器进行频率合成，获得供所述射频电路使用的时钟信号。Optionally, the radio frequency circuit includes: a phase-locked loop and a mixer, which are used to perform frequency synthesis on multiple divided clock signals of the same frequency through the phase-locked loop and the mixer to obtain a frequency for use by the radio frequency circuit. the clock signal.
可选的，所述数字电路包括时钟整形电路、时钟传输通道、时钟接收电路、频率合成单元，用于将分出的另一个时钟信号依次经过时钟整形电路、时钟传输通道、时钟接收电路后，通过频率合成单元转变为供所述数字电路的各个单元使用的时钟信号。Optionally, the digital circuit includes a clock shaping circuit, a clock transmission channel, a clock receiving circuit, and a frequency synthesis unit, which are used to sequentially pass another divided clock signal through the clock shaping circuit, the clock transmission channel, and the clock receiving circuit, The frequency synthesis unit is converted into a clock signal used by each unit of the digital circuit.
可选的，所述频率合成单元，具体用于利用所述数字电路的数据处理单元中的现场可编程门阵列FPGA自带的锁相环PLL，通过频率合成转变为供所述数字电路的各个单元使用的时钟信号。Optionally, the frequency synthesizing unit is specifically configured to use the phase-locked loop PLL carried by the field programmable gate array FPGA in the data processing unit of the digital circuit to convert frequency synthesizing into each frequency for the digital circuit. The clock signal used by the unit.
可选的，所述时钟整形电路通过低通滤波器或带通滤波器实现。Optionally, the clock shaping circuit is implemented by a low-pass filter or a band-pass filter.
可选的，当所述射频电路和所述数字电路在同一个电路板上同时存在时，所述时钟传输通道通过印刷电路板PCB微带线，或光耦传输，或磁耦传输实现；当所述射频电路和所述数字电路不在同一个电路板上同时存在时，所述时钟传输通道通过同轴线缆实现。Optionally, when the radio frequency circuit and the digital circuit exist on the same circuit board at the same time, the clock transmission channel is implemented through a printed circuit board PCB microstrip line, or optocoupler transmission, or magnetic coupling transmission; when When the radio frequency circuit and the digital circuit do not exist on the same circuit board at the same time, the clock transmission channel is implemented through a coaxial cable.
可选的，所述时钟接收电路对经过的时钟信号进行倍频处理。Optionally, the clock receiving circuit performs frequency multiplication processing on the passed clock signal.
本发明上述装置技术方案可以解决数字电路与射频电路之间的干扰问题和同步问题。特别是解决了宽频带接收机领域中的数字电路与射频电路集成于同一电路板所带来的干扰问题和同步问题，而且一个时钟也使得电路设计大大简化，节省成本。同一时钟信号使得整个系统各个时钟相关，这样可以通过软件处理去除与输入信号无关的杂散信号。射频时钟信号质量一般要优于数字时钟，所以采用同一时钟同步后可以提高整个系统频率分辨率。The above-mentioned device technical solution of the present invention can solve the interference problem and synchronization problem between the digital circuit and the radio frequency circuit. In particular, it solves the interference and synchronization problems caused by the integration of digital circuits and radio frequency circuits on the same circuit board in the field of broadband receivers, and one clock also greatly simplifies circuit design and saves costs. The same clock signal makes the clocks of the whole system related, so that the spurious signals that have nothing to do with the input signal can be removed through software processing. The quality of the radio frequency clock signal is generally better than that of the digital clock, so the frequency resolution of the entire system can be improved after the same clock is used for synchronization.
本发明实施例提供一种频谱分析仪，所述频谱分析仪包括上述提供时钟信号的装置。An embodiment of the present invention provides a spectrum analyzer, and the spectrum analyzer includes the above-mentioned device for providing a clock signal.
如图4所示，为本发明实施例一种频谱分析仪结构示意图，系统时钟41产生低相位噪声时钟信号，本实施例中使用10MHz的VCXO(Voltage Controled X′tal Oscillator，压控振荡器)作为本系统的时钟信号，此信号驱动能力较弱，所以分别加入了时钟驱动421、时钟驱动431、时钟驱动441，分别将时钟送给本振锁相环422、本振锁相环432、数字电路时钟整形电路442。锁相环422产生系统扫频信号，与射频输入信号在混频器423的作用下产生第一中频信号，此第一中频信号再与锁相环432产生的信号在混频器433的作用下产生中频输出，此中频信号频率较低，本实施例为10.7MHz，在上述射频电路中，对时钟要求最高，系统时钟41的相位噪声很大程度上决定了整个系统的相位噪声。数字时钟整形电路442在本实施例中为低通滤波器，此整形电路442将时钟驱动441输出的时钟高次谐波滤除，使进入时钟通道443的信号为纯净的正弦波时钟信号。此正弦波时钟信号在通道443中传输并不会给其他数字电路带来干扰，同样其他数字部分干扰信号也会被时钟整形电路442所滤除。10MHz正弦波信号经过通道443到达时钟接收电路444，时钟接收电路444有两个作用，第一充当匹配终端，第二将此10MHz正弦波处理为数字电路可以接受的时钟信号，本实施例中为一二倍频电路，将10MHz正弦波转变为20MHz方波时钟信号2，然后将此时钟信号2送至数据处理单元446。As shown in Figure 4, it is a schematic structural diagram of a spectrum analyzer according to an embodiment of the present invention. The system clock 41 generates a low phase noise clock signal. In this embodiment, a 10MHz VCXO (Voltage Controled X'tal Oscillator, Voltage Controlled Oscillator) is used. As the clock signal of this system, the driving ability of this signal is relatively weak, so clock driver 421, clock driver 431, and clock driver 441 are respectively added to send the clock to local oscillator phase-locked loop 422, local oscillator phase-locked loop 432, digital circuit clock shaping circuit 442 . The phase-locked loop 422 generates a system frequency sweep signal, and the RF input signal generates a first intermediate frequency signal under the action of the mixer 423, and the first intermediate frequency signal is then combined with the signal generated by the phase-locked loop 432 under the action of the mixer 433 An intermediate frequency output is generated, and the frequency of the intermediate frequency signal is relatively low, which is 10.7MHz in this embodiment. In the above-mentioned radio frequency circuit, the clock requirement is the highest, and the phase noise of the system clock 41 largely determines the phase noise of the entire system. The digital clock shaping circuit 442 is a low-pass filter in this embodiment. The shaping circuit 442 filters out the high-order harmonics of the clock output by the clock driver 441, so that the signal entering the clock channel 443 is a pure sine wave clock signal. The transmission of the sine wave clock signal in the channel 443 will not cause interference to other digital circuits, and similarly other digital interference signals will also be filtered out by the clock shaping circuit 442 . The 10MHz sine wave signal reaches the clock receiving circuit 444 through the channel 443. The clock receiving circuit 444 has two functions. The first acts as a matching terminal, and the second processes the 10MHz sine wave into a clock signal acceptable to the digital circuit. In this embodiment, it is A double frequency circuit, which converts the 10MHz sine wave into a 20MHz square wave clock signal 2, and then sends the clock signal 2 to the data processing unit 446.
此数据处理单元446是自带锁相环445的FPGA，这样只需设置软件参数即可配置不同时钟输出，如外设447，本实施例中为USB外设芯片，此USB芯片需要24MHz时钟，于是配置FPGA锁相环将时钟信号2输出为24MHz；同样外设448，本实施例中为网卡芯片，此网卡芯片需要25MHz时钟，于是配置FPGA锁相环将时钟信号3输出为25MHz，这样就完成了整个系统时钟的分配。This data processing unit 446 is an FPGA with a phase-locked loop 445, so that different clock outputs can be configured only by setting software parameters, such as the peripheral 447, which is a USB peripheral chip in this embodiment, and this USB chip needs a 24MHz clock. Then configure the FPGA phase-locked loop to output the clock signal 2 as 24MHz; the same peripheral 448, which is a network card chip in this embodiment, and this network card chip needs a 25MHz clock, so configure the FPGA phase-locked loop to output the clock signal 3 as 25MHz, so that Completed the distribution of the entire system clock.
时钟驱动421、431、441和时钟接收444的设计电路如图5、图6、图7所示。Design circuits of clock driving 421, 431, 441 and clock receiving 444 are shown in Fig. 5, Fig. 6 and Fig. 7 .
图5中的电路既可以作为时钟驱动电路，又可以作为时钟接收电路，本实施例中U31B采用器件NL27WZ04，R32与R31的比值约为4∶3，这样直流偏置约在非门U31B的翻转电平上，Vin31只需较小的幅度即可使非门U31B工作，使之Vout31输出方波。本驱动的替代方案还有图6和图7，图6中非门U41B相当于一高增益运放，工作在深度负反馈状态，其增益由R41决定；若电路对反相器的开关高次谐波敏感，还可以用替代方案图7，此放大器谐波失真小，可以满足一般电路驱动要求。The circuit in Figure 5 can be used not only as a clock driving circuit, but also as a clock receiving circuit. In this embodiment, U31B uses a device NL27WZ04, and the ratio of R32 to R31 is about 4:3, so that the DC bias is about at the flip of the NOT gate U31B. On the level, Vin31 only needs a small amplitude to make the inverter U31B work, so that Vout31 outputs a square wave. Alternatives to this drive are shown in Figure 6 and Figure 7. In Figure 6, the NOT gate U41B is equivalent to a high-gain operational amplifier, which works in a deep negative feedback state, and its gain is determined by R41; Sensitive to harmonics, you can also use the alternative scheme shown in Figure 7. This amplifier has small harmonic distortion and can meet general circuit drive requirements.
时钟整形442使驱动441输出的时钟信号便于传输而设计的，尤其是在频谱分析仪中，射频电路各个部件对时钟敏感，尤其是时钟的各次谐波，很容易进入混频器423和混频器433造成杂散信号的输出，所以需要对时钟信号进行滤波处理，本实施例中时钟整形电路如图8所示，为一10MHz带通滤波器，L61、C63、C64构成LC并联谐振回路，谐振点调整在10MHz处，这样Vout61将输出10MHz正弦波，C63和C64并联是为了增加整个谐振回路的Q值。替代方案还有10MHz低通滤波器，如图9所示。The clock shaping 442 is designed to facilitate the transmission of the clock signal output by the drive 441, especially in the spectrum analyzer, each component of the radio frequency circuit is sensitive to the clock, especially the harmonics of the clock, which are easy to enter the mixer 423 and the mixer. The frequency converter 433 causes the output of stray signals, so the clock signal needs to be filtered. In this embodiment, the clock shaping circuit is shown in Figure 8, which is a 10MHz bandpass filter, and L61, C63, and C64 form an LC parallel resonant circuit , the resonance point is adjusted at 10MHz, so that Vout61 will output a 10MHz sine wave, and C63 and C64 are connected in parallel to increase the Q value of the entire resonance circuit. An alternative is a 10MHz low-pass filter, as shown in Figure 9.
时钟传输通道443可以是PCB微带线或者是同轴线缆。为了地线的隔离时钟还可以根据系统需求选择光耦传输或者是磁耦传输。The clock transmission channel 443 may be a PCB microstrip line or a coaxial cable. In order to isolate the clock from the ground wire, optocoupler transmission or magnetic coupler transmission can also be selected according to system requirements.
本发明实施例也可以在数字电路和射频电路不在同一电路板上实现同一时钟，只需将图4中的时钟通道443修改为同轴线缆，当频率较高或线缆较长时，注意线路的匹配。In the embodiment of the present invention, the same clock can also be realized when the digital circuit and the radio frequency circuit are not on the same circuit board. Only the clock channel 443 in FIG. 4 needs to be modified to a coaxial cable. line matching.
本实施例中的数字电路和射频电路是集中于同一电路板，虽然使用了同一时钟，但是数字电路干扰仍然很大，如液晶电路上的RGB(红绿蓝)数据信号，DDR SDRAM(DoubleData Rate SDRAM，双倍速率同步动态随机存储器)数据地址信号，ADC(Analog-to-DigitalConverter，模/数转换器)数据信号等对射频电路来说都是巨大的干扰源，所以需要将数字电路和射频电路电源相互分开，地线相互分开，即割地。虽然需要割地但是又不能完全把数字地和模拟地割开，数字电路和射频电路的信号通路地还需要保证，如时钟信号通道443的地线还是要完整的保留下来。The digital circuit and the radio frequency circuit in the present embodiment are concentrated on the same circuit board. Although the same clock is used, the interference of the digital circuit is still very large, such as RGB (red, green and blue) data signals on the liquid crystal circuit, DDR SDRAM (Double Data Rate SDRAM, double-rate synchronous dynamic random access memory) data address signal, ADC (Analog-to-Digital Converter, analog/digital converter) data signal, etc. are huge sources of interference for radio frequency circuits, so it is necessary to integrate digital circuits and radio frequency The circuit power supply is separated from each other, and the ground wires are separated from each other, that is, the ground is cut. Although it is necessary to sever the ground, the digital ground and the analog ground cannot be completely separated, and the signal path ground of the digital circuit and the radio frequency circuit needs to be guaranteed. For example, the ground wire of the clock signal channel 443 must be kept intact.
当系统时钟41频率不能满足数字电路工作的情况下，还需要对此系统时钟41进行适当的处理。本实施例中10MHz时钟不能满足处理器的最低时钟要求，这是需要对其进行倍频处理，此倍频处理放在时钟接收23处，电路如图10所示，为本发明实施例对时钟信号进行倍频处理的电路设计示意图。图10中Q81、R81、R82、L81、C81、C82组成谐振放大电路，L81、C81和C82组成20MHz谐振放大电路，将Vin8上的10MHz正弦波放大后的20MHz谐波取出交给由C83、L82、C84、C85、C86、L83、C87、C88组成的20MHz带通滤波器，将谐振放大后的信号再次滤波取出纯净的20MHz信号，最后将其交给由C89、R83、U81B、R84组成的整形电路，Vout8输出20MHz方波提供给数字处理器使用，这样就完成了时钟信号的倍频接收。When the frequency of the system clock 41 cannot satisfy the operation of the digital circuit, it is also necessary to properly process the system clock 41 . In this embodiment, the 10MHz clock cannot meet the minimum clock requirement of the processor, which requires frequency multiplication processing. This frequency multiplication processing is placed at the clock receiving 23. Schematic diagram of the circuit design for signal multiplication processing. In Figure 10, Q81, R81, R82, L81, C81, and C82 form a resonant amplifying circuit, and L81, C81, and C82 form a 20MHz resonant amplifying circuit, and take out the 20MHz harmonics after the amplified 10MHz sine wave on Vin8 is handed over to C83 and L82 , C84, C85, C86, L83, C87, C88 composed of 20MHz bandpass filter, filter the resonantly amplified signal again to get a pure 20MHz signal, and finally hand it over to the shaping filter composed of C89, R83, U81B, R84 circuit, Vout8 outputs a 20MHz square wave and provides it to the digital processor, thus completing the frequency multiplication reception of the clock signal.
本发明实施例解决了宽频带接收机领域中的数字电路与射频电路集成于同一电路板所带来的干扰问题和同步问题，而且一个时钟也使得电路设计大大简化，节省成本。在整个频谱分析仪中使用同一时钟驱动，使系统各个单元时钟相关，各个单元间通讯同步；而频率合成部分用数据处理单元中的FPGA(Field-Programmable Gate Array，现场可编程门阵列)自带的PLL(Phase Locked Loop，锁相环)，充分利用资源，节省成本；数字板与射频板合于同一板，降低了装配和制板成本。同一时钟信号使得整个系统各个时钟相关，这样可以通过软件处理去除与输入信号无关的杂散信号。本发明中系统是基于同一时钟下工作，不管是射频电路本身的干扰还是来自数字电路的干扰，其效果是频谱显示中有固定的杂散存在，而且此杂散与输入无关，所以可以通过软件校准技术将这个固定杂散剔除，即使在频谱分析仪处于外同步状态下，此固定杂散仍然能有效去除。射频时钟信号质量一般要优于数字时钟，所以采用同一时钟同步后可以提高整个系统频率分辨率。The embodiment of the present invention solves the interference problem and synchronization problem caused by integrating the digital circuit and the radio frequency circuit on the same circuit board in the wideband receiver field, and one clock also greatly simplifies circuit design and saves cost. The same clock drive is used in the entire spectrum analyzer, so that the clocks of each unit of the system are related, and the communication between each unit is synchronized; and the frequency synthesis part uses the FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) in the data processing unit. Advanced PLL (Phase Locked Loop, Phase Locked Loop) makes full use of resources and saves costs; the digital board and the RF board are combined on the same board, which reduces the cost of assembly and board manufacturing. The same clock signal makes the clocks of the whole system related, so that the spurious signals that have nothing to do with the input signal can be removed through software processing. The system in the present invention works based on the same clock, whether it is the interference of the radio frequency circuit itself or the interference from the digital circuit, the effect is that there are fixed strays in the spectrum display, and this stray has nothing to do with the input, so it can be detected by software Calibration technology removes this fixed spur, even when the spectrum analyzer is in the external synchronization state, this fixed spur can still be effectively removed. The quality of the radio frequency clock signal is generally better than that of the digital clock, so the frequency resolution of the entire system can be improved after the same clock is used for synchronization.
本领域技术人员还可以了解到本发明实施例列出的各种说明性逻辑块(illustrative logical block)，单元，和步骤可以通过电子硬件、电脑软件，或两者的结合进行实现。为清楚展示硬件和软件的可替换性(interchangeability)，上述的各种说明性部件(illustrative components)，单元和步骤已经通用地描述了它们的功能。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用，可以使用各种方法实现所述的功能，但这种实现不应被理解为超出本发明实施例保护的范围。Those skilled in the art can also understand that various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of both. To clearly demonstrate the interchangeability of hardware and software, the various illustrative components, units and steps above have generally described their functions. Whether such functions are implemented by hardware or software depends on the specific application and overall system design requirements. Those skilled in the art may use various methods to implement the described functions for each specific application, but such implementation should not be understood as exceeding the protection scope of the embodiments of the present invention.
本发明实施例中所描述的各种说明性的逻辑块，或单元都可以通过通用处理器，数字信号处理器，专用集成电路(ASIC)，现场可编程门阵列(FPGA)或其它可编程逻辑装置，离散门或晶体管逻辑，离散硬件部件，或上述任何组合的设计来实现或操作所描述的功能。通用处理器可以为微处理器，可选地，该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现，例如数字信号处理器和微处理器，多个微处理器，一个或多个微处理器联合一个数字信号处理器核，或任何其它类似的配置来实现。Various illustrative logic blocks or units described in the embodiments of the present invention can be implemented by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to implement or operate the described functions. The general-purpose processor may be a microprocessor, and optionally, the general-purpose processor may also be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration to accomplish.
本发明实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的软件模块、或者这两者的结合。软件模块可以存储于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介中。示例性地，存储媒介可以与处理器连接，以使得处理器可以从存储媒介中读取信息，并可以向存储媒介存写信息。可选地，存储媒介还可以集成到处理器中。处理器和存储媒介可以设置于ASIC中，ASIC可以设置于用户终端中。可选地，处理器和存储媒介也可以设置于用户终端中的不同的部件中。The steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, a software module executed by a processor, or a combination of both. The software modules may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM or any other storage medium in the art. Exemplarily, the storage medium can be connected to the processor, so that the processor can read information from the storage medium, and can write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and the storage medium can be set in the ASIC, and the ASIC can be set in the user terminal. Optionally, the processor and the storage medium may also be set in different components in the user terminal.
在一个或多个示例性的设计中，本发明实施例所描述的上述功能可以在硬件、软件、固件或这三者的任意组合来实现。如果在软件中实现，这些功能可以存储与电脑可读的媒介上，或以一个或多个指令或代码形式传输于电脑可读的媒介上。电脑可读媒介包括电脑存储媒介和便于使得让电脑程序从一个地方转移到其它地方的通信媒介。存储媒介可以是任何通用或特殊电脑可以接入访问的可用媒体。例如，这样的电脑可读媒体可以包括但不限于RAM、ROM、EEPROM、CD-ROM或其它光盘存储、磁盘存储或其它磁性存储装置，或其它任何可以用于承载或存储以指令或数据结构和其它可被通用或特殊电脑、或通用或特殊处理器读取形式的程序代码的媒介。此外，任何连接都可以被适当地定义为电脑可读媒介，例如，如果软件是从一个网站站点、服务器或其它远程资源通过一个同轴电缆、光纤电脑、双绞线、数字用户线(DSL)或以例如红外、无线和微波等无线方式传输的也被包含在所定义的电脑可读媒介中。所述的碟片(disk)和磁盘(disc)包括压缩磁盘、镭射盘、光盘、DVD、软盘和蓝光光盘，磁盘通常以磁性复制数据，而碟片通常以激光进行光学复制数据。上述的组合也可以包含在电脑可读媒介中。In one or more exemplary designs, the above functions described in the embodiments of the present invention may be implemented in hardware, software, firmware or any combination of the three. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media and communication media that facilitate transfer of a computer program from one place to another. Storage media may be any available media that can be accessed by a general purpose or special computer. For example, such computer-readable media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other device that can be used to carry or store instructions or data structures and Other medium of program code in a form readable by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly defined as a computer-readable medium, for example, if the software is transmitted from a web site, server, or other remote source via a coaxial cable, fiber optic computer, twisted pair, digital subscriber line (DSL) Or transmitted by wireless means such as infrared, wireless and microwave are also included in the definition of computer readable media. Disks and discs include compact discs, laser discs, optical discs, DVDs, floppy discs, and Blu-ray discs. Disks usually reproduce data magnetically, while discs usually reproduce data optically with lasers. Combinations of the above can also be contained on a computer readable medium.
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431634.9ACN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431634.9ACN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
| Publication Number | Publication Date |
|---|---|
| CN103178836A CN103178836A (en) | 2013-06-26 |
| CN103178836Btrue CN103178836B (en) | 2017-08-25 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110431634.9AActiveCN103178836B (en) | 2011-12-21 | 2011-12-21 | A kind of method, device and spectrum analyzer that clock signal is provided |
| Country | Link |
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| CN (1) | CN103178836B (en) |
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