CN103178779A

Movatterモバイル変換

Info

Publication number: CN103178779A
Application number: CN2011104315204A
Authority: CN
Inventors: 丁新宇; 王悦; 王铁军; 李维森
Original assignee: Beijing Rigol Technologies Inc
Current assignee: Beijing Rigol Technologies Inc
Priority date: 2011-12-21
Filing date: 2011-12-21
Publication date: 2013-06-26
Anticipated expiration: 2031-12-21
Also published as: CN103178779B

Abstract

The invention provides a signal generator with an amplitude compensation function and a method thereof. A field programmable gate array (FPGA) module comprises a clock module, a frequency sweeping time accumulator, a frequency sweeping curve storage, an excursion multiplying device, a frequency word summator, a frequency accumulator, a carrier storage, an amplitude frequency compensation unit and a compensation multiplying device. Frequency sweeping time accumulated value is generated by the frequency sweeping time accumulator, one way of the value is processed by the frequency sweeping curve storage, the excursion multiplying device, the frequency word summator, the frequency accumulator and the carrier storage to produce output carrier, and the other way of the value is processed by the amplitude frequency compensation unit to produce output compensation. Compensated frequency sweeping signals are achieved by the compensation multiplying device. By means of the signal generator and the method, the problem of amplitude flatness in the frequency sweeping process is solved.

Description

A kind of signal generator and method thereof with Amplitude Compensation function

Technical field

The present invention relates to the thermometrically technical field, particularly a kind of signal generator and method thereof with Amplitude Compensation function.

Background technology

Signal generator, is widely used in measurement, verification and the maintenance of electronic system because it can produce different frequency, difform waveform as a kind of signal source.Signal generator is output waveform not only, for the ease of user's thermometrically, also exports simultaneously synchronizing signal.In fields such as electronics, communication, computers, synchronizing signal has various definition.In the present invention, synchronizing signal is refered in particular to a pulse signal that is synchronized with the signal generator output waveform.

Along with the development of programmable logic technology, a lot of manufacturers all adopt DDS technology and FPGA technology to realize signal generator.Direct Digital is synthesized (Direct Digital Synthesis, hereinafter to be referred as DDS) be a kind of major technique in present frequency synthesis, have low cost, high-resolution, fast change-over time, can produce random waveform and the characteristics such as the output waveform phase place is continuous when switching, be widely adopted in the signal generator design.

Fig. 1 realizes the structured flowchart of frequency sweep function for the signal generator of typical employing DDS technology.Wherein, each sweep parameters that digital signal processor (DSP) arranges the user configures the register to FPGA inside, thereby controls the mode of operation of DDS.FPGA realizes the function of DDS, and its internal structure as shown in Figure 2.Use two accumulators cumulative frequency base unit weight and frequency increment respectively, sum of the two is as the address of reading of wave memorizer.Waveform memory stores be the waveform sampling point of carrier wave, according to reading address output waveform sampling point.Digital to analog converter is converted to staircase waveform with the digital quantity of wave memorizer output.The effect of filter is the clutter that suppresses in staircase waveform, exports relatively level and smooth waveform.Analog channel is that the amplitude to output signal further processes, such as amplitude accurate adjustment, amplification, decay, skew etc.

For the amplitude-frequency characteristic of the tested network of Measurement accuracy, in the frequency change process, its amplitude should be invariable as the swept-frequency signal of test source.Yet, as relatively poor in the amplitude flatness of the swept-frequency signal of the existing signal generator of Fig. 1 structure.This is mainly that the amplitude-versus-frequency curve due to the signal system that is made of DAC, filter, analog channel in this structure is uneven, even therefore within bandwidth range, the amplitude of the waveform of the different frequency of the output of above-mentioned DDS signal generator is also inconsistent.Trace it to its cause and to analyze from these three parts respectively.

(1) DAC: what DAC realized at present is not desirable unit impact sampling, and its transfer function has the envelope trait of SINC function mostly, perhaps other nonlinear envelope shape.

(2) filter: the harmonic wave of often selecting the precipitous filter filtering sinusoidal signal of transient characteristic in the DDS signal generator; But because the element quality factor that form filter are large not, the frequency response curve in the cut-off frequency scope has recessed or becomes round and smooth, and the ripple shape is perhaps arranged;

(3) analog channel: the amplifying circuit in analog channel mainly is comprised of operational amplifier, and according to the frequency response characteristic of operational amplifier, operational amplifier has decay to the amplitude of high-frequency signal.

Above-mentioned factor has affected the amplitude flatness of output signal to a great extent.In order to address this problem, the DDS signal generator has the process of a calibration before dispatching from the factory: utilize the instruments such as universal instrument, power meter to obtain amplitude-versus-frequency curve; Calculate amplitude accurate adjustment coefficient according to the inverse of amplitude-versus-frequency curve by software.But the method that this software is proofreaied and correct can only realize proofreading and correct on a frequency, and the frequency of output signal is changing during frequency sweep, the Amplitude Compensation in the time of therefore can't realizing frequency sweep.

Summary of the invention

Main purpose of the present invention is to solve problems of the prior art, and a kind of signal generator and method thereof with Amplitude Compensation function is provided, the amplitude flatness problem when solving frequency sweep.

The objective of the invention is to be achieved by following technical proposals:

A kind of signal generator with Amplitude Compensation function comprises: FPGA module, DAC module, low pass filter and analog channel; Described FPGA module is used for generating swept-frequency signal; This swept-frequency signal is processed by DAC module, low pass filter and analog channel successively, forms the swept-frequency signal of final output; It is characterized in that: described FPGA module comprises: clock module, frequency sweep time totalizer, frequency sweep profile memory, skew multiplier, frequency word adder, frequency accumulator, carrier wave memory, amplitude-frequency compensating unit and compensation multiplier;

Described clock module is used to other modules of FPGA inside modules that master clock is provided;

Described frequency sweep time totalizer is used for generating frequency sweep time accumulated value so that frequency sweep time control word is cumulative, and this frequency sweep time accumulated value is sent to respectively frequency sweep profile memory and amplitude-frequency compensating unit;

Described frequency sweep profile memory is used for based on the frequency sweep curve that sets in advance, according to frequency sweep curve sampling point corresponding to described frequency sweep time accumulated value output;

Described skew multiplier is used for described frequency sweep curve sampling point and frequency sweep offset coefficient are multiplied each other, and obtains the increment of frequency sweep frequency word;

Described frequency word adder is used for increment and basic frequency sweep frequency word addition with described frequency sweep frequency word, obtains carrier wave frequency sweep frequency word;

Described frequency accumulator is used for described carrier wave frequency sweep frequency word is added up, and obtains the carrier wave memory and reads the address;

Described carrier wave memory is used for reading according to described carrier wave memory the corresponding sampling point that the carrier wave sampling point collection of depositing is read in the address, and exports this outgoing carrier;

Described amplitude-frequency compensating unit is used for reading the corresponding sampling point of the amplitude-frequency compensated curve of depositing according to described frequency sweep time accumulated value, and exports this output compensation;

Described compensation multiplier receives outgoing carrier and output compensation, is used for outgoing carrier and output compensation are multiplied each other, and obtains the swept-frequency signal after Amplitude Compensation.

Be provided with compensating delay and amplitude-frequency compensation memory in described amplitude-frequency compensating unit;

Described compensating delay, receiving frequency-sweeping time accumulated value is used for described frequency sweep time accumulated value is carried out delay disposal, obtains the amplitude-frequency compensation memory and reads the address;

Described amplitude-frequency compensation memory is used for reading according to described amplitude-frequency compensation memory the corresponding sampling point that the amplitude-frequency compensated curve of depositing is read in the address, and exports this output compensation.

Described amplitude-frequency compensation memory is used for reading the corresponding sampling point of the amplitude-frequency compensated curve of depositing according to described frequency sweep time accumulated value, and exports this and do not postpone output and compensate;

Described compensating delay receives this and does not postpone the output compensation, is used for described delay output compensation is carried out delay disposal, the output compensation after being postponed.

Described amplitude-frequency compensated curve is the inverse of the amplitude-versus-frequency curve of the signal system that consists of of described DAC module, low pass filter, analog channel.

A kind of signal generating method with Amplitude Compensation function, the swept-frequency signal that is generated by the FPGA module, through the DAC module carry out digital-to-analogue conversion, low pass filter carries out low-pass filtering and the analog channel amplitude of carrying out is processed, and forms the swept-frequency signal of final output; It is characterized in that: described FPGA module generates the process of swept-frequency signal, comprising:

Generate frequency sweep time accumulated value so that frequency sweep time control word is cumulative, and this frequency sweep time accumulated value is sent to respectively frequency sweep profile memory and amplitude-frequency compensating unit;

Be sent to the following processing of frequency sweep time accumulated value process of frequency sweep profile memory:

Based on the frequency sweep curve that sets in advance, according to frequency sweep curve sampling point corresponding to described frequency sweep time accumulated value output;

Described frequency sweep curve sampling point and frequency sweep offset coefficient are multiplied each other, obtain the increment of frequency sweep frequency word;

Increment and basic frequency sweep frequency word addition with described frequency sweep frequency word obtain carrier wave frequency sweep frequency word;

Described carrier wave frequency sweep frequency word is added up, obtain the carrier wave memory and read the address;

Read according to described carrier wave memory the corresponding sampling point that the carrier wave sampling point collection of depositing is read in the address, and export this outgoing carrier;

Be sent to the following processing of frequency sweep time accumulated value process of amplitude-frequency compensating unit:

Read the corresponding sampling point of the amplitude-frequency compensated curve of depositing according to described frequency sweep time accumulated value, and export this output compensation;

Outgoing carrier and output compensation are multiplied each other, obtain the swept-frequency signal after Amplitude Compensation.

The described processing procedure that is sent to the frequency sweep time accumulated value of amplitude-frequency compensating unit comprises the steps:

Described frequency sweep time accumulated value is carried out delay disposal, obtain the amplitude-frequency compensation memory and read the address;

Read according to described amplitude-frequency compensation memory the corresponding sampling point that the amplitude-frequency compensated curve of depositing is read in the address, and export this output compensation.

Read the corresponding sampling point of the amplitude-frequency compensated curve of depositing according to described frequency sweep time accumulated value, and export this and do not postpone output compensation;

Postpone to export to compensate to carry out delay disposal the output compensation after being postponed to described.

Pass through the embodiment of the present invention, before FPGA module output swept-frequency signal, according to its frequency change, first be multiplied by this amplitude-frequency compensated curve, after passing through the signal system of follow-up DAC, low pass filter, analog channel, this swept-frequency signal remains permanent envelope, the amplitude flatness problem when having solved frequency sweep.

In addition, when the initial frequency of this signal generator frequency sweep, termination frequency shift, only need the base quantity of configuration frequency sweep offset coefficient and frequency word to get final product, need not to revise the frequency sweep profile memory, greatly improved system effectiveness.

Description of drawings

Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of the application's a part, does not consist of limitation of the invention.In the accompanying drawings:

Fig. 1 realizes the structured flowchart of frequency sweep function for the signal generator of typical employing DDS technology;

Fig. 2 is FPGA inside modules structural representation in existing signal generator;

Fig. 3 is embodiment of the present invention FPGA inside modules functional module structure block diagram;

Fig. 4 is amplitude-frequency compensated curve calibration flow chart;

Fig. 5 is the signal generating method flow chart with Amplitude Compensation function.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with execution mode and accompanying drawing, the present invention is described in further details.At this, exemplary embodiment of the present invention and explanation thereof are used for explanation the present invention, but not as a limitation of the invention.

The signal generator with Amplitude Compensation function that the present invention is designed existing signal generator structure with shown in Figure 1 on hardware configuration is identical, comprising: FPGA module, DAC module, low pass filter and analog channel.Described FPGA module is used for generating swept-frequency signal.This swept-frequency signal is processed by DAC module, low pass filter and analog channel successively, forms the swept-frequency signal of final output.

Wherein, key design of the present invention be the functional module structure of FPGA inside, with the amplitude flatness of final improvement output swept-frequency signal.Fig. 3 is FPGA inside modules functional module structure block diagram.As shown in the figure, this FPGA module comprises:clock module 400, frequencysweep time totalizer 401, frequencysweep profile memory 402,skew multiplier 403,frequency word adder 404,frequency accumulator 405,carrier wave memory 406, amplitude-frequency compensating unit andcompensation multiplier 409.

Describedclock module 400 is used to other modules of FPGA inside modules thatmaster clock 420 is provided.

Described frequencysweep time totalizer 401 is used for generating frequency sweep time accumulatedvalue 421 so that frequency sweeptime control word 431 is cumulative, and this frequency sweep time accumulatedvalue 421 is sent to respectively frequencysweep profile memory 402 and amplitude-frequency compensating unit.The bit wide of supposing the frequency sweep time totalizer is the N position,

Frequency sweep cycle=master clock 420 cycle * 2^N/ frequency sweep time control word 431 (formula 1)

Described frequencysweep profile memory 402 is used for based on thefrequency sweep curve 432 that sets in advance, according to described frequency sweep time accumulatedvalue 421 frequency sweep curve sampling points 422 corresponding to output.Thisfrequency sweep curve 432 is before swept-frequency signal begins output, writes this frequencysweep profile memory 402 by the processorfrequency sweep curve 432 that sweep method is corresponding.Like this, only otherwise change sweep method, processor just need not to reconfigure the frequency sweep profile memory.

Generally, the bit wide N of frequency sweep time accumulatedvalue 421 is greater than the address bit wide M of frequency sweep profile memory, gives the latter with the former high M position, as the latter's the address of reading.

The frequency sweep time totalizer adds up a week, and all frequency sweep curve sampling points 422 of reading from the frequency sweep profile memory are exactly a frequency sweep cycle.

Describedskew multiplier 403 is used for described frequency sweepcurve sampling point 422 is multiplied each other with frequency sweep offsetcoefficient 433, obtains theincrement 423 of frequency sweep frequency word.This frequency sweep offsetcoefficient 433 writes skewmultiplier 403 in advance by processor.The multiplication formula of thisskew multiplier 403 is as follows:

Increment 423=frequency sweepcurve sampling point 422 * frequency sweep offset coefficient 433 (formula 2) of frequency sweep frequency word

Describedfrequency word adder 404 is used forincrement 423 and basic frequencysweep frequency word 434 additions with described frequency sweep frequency word, obtains carrier wave frequencysweep frequency word 424, supposes that its bit wide is the K position.This basic frequencysweep frequency word 434 is by processor writefrequency word adder 404 in advance.The addition formula of thisfrequency word adder 404 is as follows:

The increment 423 (formula 3) of the basic frequency sweep frequency word of carrier wave frequencysweep frequency word 424=434+ frequency sweep frequency word

Describedfrequency accumulator 405 is used for described carrier wave frequencysweep frequency word 424 is added up, and obtains the carrier wave memory and readsaddress 425.

Forfrequency accumulator 405, it adds up to described carrier wave frequencysweep frequency word 424, supposes the some moment M at main clock pulse, and the result (being that the carrier wave memory is read address 425) offrequency accumulator 405 outputs is P_MThe result of previous moment M-1 output is P_M-1, following relation is arranged:

P_M=P_M-1+ carrier wave frequency sweep frequency word 424 (formula 4)

Can find out clearly that by formula 2,3,4 the frequency sweep curve has determined the frequency change mode of swept-frequency signal.

On the other hand according to formula 2, take the frequency sweep profile memory of 16 bit data bit wides as example, the scope of its frequency sweep curve is 0～0xFFFF.If the user has revised initial frequency, the termination frequency of frequency sweep, only need modification frequency sweep offsetcoefficient 433 and basic frequencysweep frequency word 434 to get final product, need not to revise 2^MThe frequency sweep curve of individual sampling point can improve system effectiveness so greatly.Can calculate initial frequency and stop the corresponding frequency word of reckling between frequency according to formula 4, with KW_minExpression; Frequency word corresponding to the maximum both is with KW_maxExpression.Still take the frequency sweep profile memory of 16 bit data bit wides as example, following relational expression is arranged between them:

Basic frequencysweep frequency word 434=KW_min(formula 5)

Frequency sweep offsetcoefficient 433=(KW_max-KW_min)/65535 (formula 6)

Describedcarrier wave memory 406 is used for reading according to described carrier wave memory the corresponding sampling point that the carrier wavesampling point collection 435 of depositing is read inaddress 425, and exports this outgoing carrier 426.This carrier wavesampling point collection 435 pre-depositscarrier wave memory 406 by processor.This carrier wave sampling point integrates the 435 sampling point set as the one-period of carrier wave shape.This carrier wave shape can be sine wave, square wave, sawtooth waveforms etc.Thisoutgoing carrier 426 Digital Sweep signal that to be exactly frequency change according to sweep method.Inner at FPGA, it is permanent envelope, if directly export to DAC, passes through amplitude flatness variation after filter and analog channel.

Described amplitude-frequency compensating unit is used for reading the corresponding sampling point of the amplitude-frequency compensatedcurve 436 of depositing according to described frequency sweep time accumulatedvalue 421, and exports this output compensation 428.This amplitude-frequency compensatedcurve 436 pre-deposits the amplitude-frequency compensating unit by processor.

Describedcompensation multiplier 409 receivesoutgoing carrier 426 andoutput compensation 428, is used foroutgoing carrier 426 andoutput compensation 428 are multiplied each other, and obtains the swept-frequency signal after Amplitude Compensation.

As mentioned before, the amplitude-versus-frequency curve of the signal system that is made of DAC, filter, analog channel is uneven, but the equipment such as this curve negotiating universal instrument, power meter can be measured.The present invention namely utilizes this point to carry out the full rate compensation to swept-frequency signal.Its basic principle is to utilize A=A * (1/B) * B formula: A is the swept-frequency signal of permanent envelope herein; B is the uneven amplitude-versus-frequency curve of above-mentioned signal system; 1/B is the inverse of this amplitude-versus-frequency curve, is called the amplitude-frequency compensated curve.The present invention is namely before FPGA module output swept-frequency signal, according to its frequency change, first be multiplied by this amplitude-frequency compensated curve (being the inverse of amplitude-versus-frequency curve), after passing through the signal system of follow-up DAC, filter, analog channel, this swept-frequency signal remains permanent envelope, the amplitude flatness problem when having solved frequency sweep.

Signal generator has the process of a calibration before dispatching from the factory, in order to obtain above-mentioned amplitude-frequency compensated curve, adopt flow process shown in Figure 4.During calibration, the configuration carrier wave is shaped as sine wave, the amplitude-frequency compensated curve is required highest frequency value by the frequency range of constant, linear frequency sweep mode, frequency sweep from 1KHz to the product, FPGA output is the sine wave of linear frequency sweep like this, and due to without overcompensation, its envelope is constant amplitude.Utilize the measuring equipments such as universal instrument, power meter just can measure amplitude-versus-frequency curve; After calculating through software, just can obtain the amplitude-frequency compensated curve.

Due to,outgoing carrier 426 is obtained after through a series of resume module such as frequencysweep profile memory 402,skew multiplier 403,frequency word adder 404,frequency accumulator 405,carrier wave memories 406 by frequency sweep time accumulatedvalue 421, andoutput compensation 428 is processed through the amplitude-frequency compensating units by frequency sweep time accumulatedvalue 421 and obtained.Therefore, usually there is the time difference betweenoutgoing carrier 426 and output compensation 428.In order to makeoutgoing carrier 426 andoutput compensation 428 consistent on sequential, the compensating delay unit need to be set in described amplitude-frequency compensating unit.

As shown in Figure 3, be provided with compensatingdelay 407 and amplitude-frequency compensation memory 408 in described amplitude-frequency compensating unit.

Described compensatingdelay 407, receiving frequency-sweeping time accumulatedvalue 421 is used for described frequency sweep time accumulatedvalue 421 is carried out delay disposal, and the frequency sweep time accumulated value after being postponed is readaddress 427 as the amplitude-frequency compensation memory.

Described amplitude-frequency compensation memory 408 is used for reading according to described amplitude-frequency compensation memory the corresponding sampling point that the amplitude-frequency compensatedcurve 436 of depositing is read inaddress 427, and exports this output compensation 428.This amplitude-frequency compensatedcurve 436 pre-deposits amplitude-frequency compensation memory 408 by processor.

The present embodiment is that frequency sweep time accumulatedvalue 421 is postponed, and also can the output of amplitude-frequency compensation memory 408 be postponed, and purpose is all to allow betweenoutgoing carrier 426 andoutput compensation 428 sequential consistent, and concrete scheme is as follows:

Be provided with compensating delay and amplitude-frequency compensation memory in described amplitude-frequency compensating unit.

Described amplitude-frequency compensation memory is used for reading the corresponding sampling point of the amplitude-frequency compensated curve of depositing according to described frequency sweep time accumulated value, and exports this and do not postpone output and compensate.This amplitude-frequency compensated curve pre-deposits the amplitude-frequency compensation memory by processor.

According to Fig. 3, there are two data paths between frequencysweep time totalizer 401 andcompensation multiplier 409, starting point is frequency sweep time accumulatedvalue 421, path 1:421 → 422 → 423 → 424 → 425 → 426; Path 2:421 → 427 → 428.All in 420 times work of main clock pulse, the processing module of 1 process of path is many for inner all modules of FPGA, and the processing module of path 2 is less.If there is no compensating delay, the time delay of path 1 is greater than the time delay of path 2.Both time delay is consistent in order to allow, and need to carry out extra delay by 407 pairs of paths of compensating delay module 2.How many time delays between path 1,2 specifically differs, and are relevant with the specific implementation of FPGA.

Fig. 5 is the signal generating method flow chart with Amplitude Compensation function.As shown in the figure, the swept-frequency signal that this signal generating method is generated by the FPGA module, through the DAC module carry out digital-to-analogue conversion, low pass filter carries out low-pass filtering and the analog channel amplitude of carrying out is processed, and forms the swept-frequency signal of final output.Wherein, this FPGA module generates swept-frequency signal, comprising:

Generate frequency sweep time accumulatedvalue 421 so that frequency sweeptime control word 431 is cumulative, and this frequency sweep time accumulatedvalue 421 is sent to respectively frequencysweep profile memory 402 and amplitude-frequency compensating unit;

Be sent to the frequency sweep time accumulatedvalue 421 following processing of process of frequency sweep profile memory 402:

Based on thefrequency sweep curve 432 that sets in advance, according to described frequency sweep time accumulatedvalue 421 frequency sweep curve sampling points 422 corresponding to output;

Described frequency sweepcurve sampling point 422 is multiplied each other with frequency sweep offsetcoefficient 433, obtain theincrement 423 of frequency sweep frequency word;

Increment 423 and basic frequencysweep frequency word 434 additions with described frequency sweep frequency word obtain carrier wave frequencysweep frequency word 424;

Described carrier wave frequencysweep frequency word 424 is added up, obtain the carrier wave memory and readaddress 425;

Read according to described carrier wave memory the corresponding sampling point that the carrier wavesampling point collection 435 of depositing is read inaddress 425, and export thisoutgoing carrier 426.

Be sent to the frequency sweep time accumulatedvalue 421 following processing of process of amplitude-frequency compensating unit:

Read the corresponding sampling point of the amplitude-frequency compensatedcurve 436 of depositing according to described frequency sweep time accumulatedvalue 421, and export thisoutput compensation 428.

Outgoing carrier 426 andoutput compensation 428 are multiplied each other, obtain the swept-frequency signal after Amplitude Compensation.

As previously mentioned, the inverse of the amplitude-versus-frequency curve of the signal system that consists of for DAC, filter, analog channel of amplitude-frequency compensatedcurve 436 wherein.

The described processing procedure that is sent to the frequency sweep time accumulatedvalue 421 of amplitude-frequency compensating unit specifically comprises the steps:

Described frequency sweep time accumulatedvalue 421 is carried out delay disposal, and the frequency sweep time accumulated value after being postponed is readaddress 427 as the amplitude-frequency compensation memory;

Read according to described amplitude-frequency compensation memory the corresponding sampling point that the amplitude-frequency compensatedcurve 436 of depositing is read inaddress 427, and export thisoutput compensation 428.

Equally, this be sent to the amplitude-frequency compensating unit frequency sweep time accumulatedvalue 421 processing procedure can also as following step:

In sum, the invention provides a kind of signal generator and method thereof with Amplitude Compensation function, before FPGA module output swept-frequency signal, according to its frequency change, first be multiplied by this amplitude-frequency compensated curve, after passing through the signal system of follow-up DAC, low pass filter, analog channel, this swept-frequency signal remains permanent envelope, amplitude flatness problem when having solved frequency sweep.And, when the initial frequency of this signal generator frequency sweep, termination frequency shift, only need the base quantity of configuration frequency sweep offset coefficient and frequency word to get final product, need not to revise the frequency sweep profile memory, greatly improved system effectiveness.Persons skilled in the art any not creative transformation of doing under this design philosophy all should be considered as within protection scope of the present invention.

Claims

1. the signal generator with Amplitude Compensation function, comprising: FPGA module, DAC module, low pass filter and analog channel; Described FPGA module is used for generating swept-frequency signal; This swept-frequency signal is processed by DAC module, low pass filter and analog channel successively, forms the swept-frequency signal of final output; It is characterized in that: described FPGA module comprises: clock module, frequency sweep time totalizer, frequency sweep profile memory, skew multiplier, frequency word adder, frequency accumulator, carrier wave memory, amplitude-frequency compensating unit and compensation multiplier;

2. the signal generator with Amplitude Compensation function as claimed in claim 1, is characterized in that: be provided with compensating delay and amplitude-frequency compensation memory in described amplitude-frequency compensating unit;

3. the signal generator with Amplitude Compensation function as claimed in claim 1, is characterized in that: be provided with compensating delay and amplitude-frequency compensation memory in described amplitude-frequency compensating unit;

4. as claim 1,2 or 3 described signal generators with Amplitude Compensation function, it is characterized in that: described amplitude-frequency compensated curve is the inverse of the amplitude-versus-frequency curve of the signal system that consists of of described DAC module, low pass filter, analog channel.

5. signal generating method with Amplitude Compensation function, the swept-frequency signal that is generated by the FPGA module, through the DAC module carry out digital-to-analogue conversion, low pass filter carries out low-pass filtering and the analog channel amplitude of carrying out is processed, and forms the swept-frequency signal of final output; It is characterized in that: described FPGA module generates the process of swept-frequency signal, comprising:

6. the signal generating method with Amplitude Compensation function as claimed in claim 5, it is characterized in that: the described processing procedure that is sent to the frequency sweep time accumulated value of amplitude-frequency compensating unit comprises the steps:

7. the signal generating method with Amplitude Compensation function as claimed in claim 5, it is characterized in that: the described processing procedure that is sent to the frequency sweep time accumulated value of amplitude-frequency compensating unit comprises the steps:

8. as claim 5,6 or 7 described signal generating methods with Amplitude Compensation function, it is characterized in that: described amplitude-frequency compensated curve is the inverse of the amplitude-versus-frequency curve of the signal system that consists of of described DAC module, low pass filter, analog channel.