CN103164314A - Peripheral component interface express (PCIe) interface chip hardware verification method based on asynchronous physical layer interface - Google Patents

Abstract

Translated fromChinese

本发明公开了一种基于异步物理层接口的PCIe接口芯片硬件验证方法，其实施步骤如下：1)构建具有标准PCI Express接口的FPGA硬件平台；2)在待验证的PCI Express接口芯片ASIC代码中的PCI Express软核与物理层之间插入用于匹配频率差的异步物理层接口；3)将待验证的PCI Express接口芯片ASIC代码迁移到FPGA硬件平台综合实现，并根据PCIExpress接口芯片被综合的最高频率设置降频PIPE接口的工作频率；4)使用测试程序通过FPGA硬件平台对PCI Express接口芯片的PCI Express软核和用户逻辑进行功能测试。本发明能够实现PCI Express接口芯片的降频硬件验证，具有兼容现有测试代码、实现简单方便、通用性好、资源占用率低的优点。

The invention discloses a PCIe interface chip hardware verification method based on an asynchronous physical layer interface, and its implementation steps are as follows: 1) constructing an FPGA hardware platform with a standard PCI Express interface; 2) in the PCI Express interface chip ASIC code to be verified Insert an asynchronous physical layer interface used to match the frequency difference between the PCI Express soft core and the physical layer; 3) Migrate the ASIC code of the PCI Express interface chip to be verified to the FPGA hardware platform for comprehensive implementation, and synthesize it according to the PCI Express interface chip 4) use the test program to carry out functional testing on the PCI Express soft core and user logic of the PCI Express interface chip through the FPGA hardware platform. The invention can realize the down-frequency hardware verification of the PCI Express interface chip, and has the advantages of compatibility with existing test codes, simple and convenient implementation, good versatility, and low resource occupation rate.

Description

PCIe interface chip hardware verification method based on asynchronous physical layer interface

Technical field

The present invention relates to the hardware verification field of asic chip, be specifically related to a kind of PCIe interface chip hardware verification method based on asynchronous physical layer interface.

Background technology

PCI Express (PCIe) is the I/O bus standard that is most widely used at present, based on the asic chip structure of PCI Express interface as shown in Figure 1, mainly is made of Physical layer, the soft core of PCI Express and user logic three parts.Physical layer is responsible for data encoding and string and conversion, PCI Express is soft examines existing PCI Express bus protocol, an industry standard interface between Physical layer and the soft core of PCI Express, be called PCI Express physical layer interface (PHY Interface of PCI Express, be called for short the PIPE interface), user logic is realized the data processing function of asic chip on PCI Express user interface.

The checking of asic chip mainly contains two kinds of methods: software simulation and hardware verification.Software simulation carries out emulated execution based on simulator to code, but simple and convenient speed is slower, is difficult to the profound mistake in the discovery logic design.Hardware verification is comprehensively carried out code on Hardware Verification Platform in real environment, verifying speed is very fast, but comparatively complicated.In the ASIC proof procedure, common two kinds of methods can complement one another, the final all standing that realizes chip functions.

The ASIC code does not reach the frequency of operation of ASIC reality comprehensively in the FPGA time usually, therefore generally all adopts the mode of frequency reducing checking, the FPGA frequency of operation is reduced to the part of ASIC frequency of operation.The frequency reducing of internal logic code is on functional verification not impact usually, external interface generally need to communicate (for example PCI Express end node devices need to be connected the PCI Express root node equipment on mainboard) with FPGA verification platform equipment in addition, if the interface rate of FPGA verification platform and the interface rate of miscellaneous equipment are inconsistent, just can't carry out normal data transmission.Between the frequency of operation of the soft core of PCI Express and physical layer interface speed, strict relation is arranged, the frequency of operation that directly reduces soft core will cause the physical layer interface rate reduction, cause can't connection standard speed PCI Express equipment, so this a kind of method that just needs hardware verification PCI Express interface is to realize the soft core of PCI Express after frequency reducing and the communication between Standard PC I Express equipment.

For above-mentioned technical matters, the solution of prior art mainly contains following two kinds:

(1) the stone Shift Method of Xilinx/Altera company.To replace with for the soft core of PCI Express that ASIC designs the soft core of PCI Express or the stone that to realize in FPGA, then insert asynchronous FIFO and realize the frequency reducing checking on the PCI Express user interface after replacement.The shortcoming of this method first is that the soft core of PCI Express self and interrelated logic can't be verified, second because the user interface of every kind of PCI Express IP is all different, adopt the mode of replacing to change user interface, therefore user logic must be made corresponding modification, cause ASIC code and FPGA code inconsistent, not only increase the checking complicacy, and reduced the confidence level of checking.

(2) SpeedBridge technology.The SpeedBridge technology of Cadence is to insert a special PCI Express bridge device between the PCI Express of frequency reducing on the PCI of standard Express interface and Hardware Verification Platform interface, this bridge device has the port of two different rates, be transmitted to the PCI Express interface of frequency reducing after the packet buffer that it receives Standard PC I Express interface, thereby realize the transparent communication of frequency reducing PCI Express equipment and Standard PC I Express equipment.Card extender and the bridge chip of SpeedBridge Technology Need design specialized are realized very complicatedly, and SpeedBridge can only be used for the Palladium verification platform of Cadence at present, can't be applied on general FPGA verification platform.

In sum, the frequency reducing that how to realize PCI Express interface on general FPGA Hardware Verification Platform verifies it is the technical matters that those skilled in the art very pay close attention to.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind ofly can realize PCI Express interface chip frequency reducing hardware verification, compatible existing test code, realize the PCIe interface chip hardware verification method based on asynchronous physical layer interface simple and convenient, that versatility good, resources occupation rate is low.

In order to solve the problems of the technologies described above, the technical solution used in the present invention is:

A kind of PCIe interface chip hardware verification method based on asynchronous physical layer interface, implementation step is as follows:

1) build the FPGA hardware platform with Standard PC I Express interface, described FPGA hardware platform is connected with main frame with PCI Express root node equipment by Standard PC I Express interface;

2) insert between the soft core of PCI Express in PCI Express interface chip ASIC code to be verified and Physical layer for the poor asynchronous physical layer interface of matching frequency, described asynchronous physical layer interface comprises transmission buffer zone, reception buffer zone, frequency reducing PIPE interface and standard P IPE interface, and described asynchronous physical layer interface is connected with the FPGA hardware platform, is connected with Physical layer by standard P IPE interface by frequency reducing PIPE interface;

3) described PCI Express interface chip ASIC code to be verified is moved to described FPGA hardware platform and comprehensively realize, and according to PCI Express interface chip, the frequency of operation of frequency reducing PIPE interface is set by comprehensive highest frequency;

4) use test program is carried out functional test by described FPGA hardware platform to the soft core of PCI Express and the user logic of PCI Express interface chip, when the soft core of PCI Express sends PCI Express message by asynchronous physical layer interface to Physical layer, the soft core of PCI Express writes PCI Express message by frequency reducing PIPE interface the transmission buffer zone of asynchronous physical layer interface, asynchronous physical layer interface will send buffer cache PCI Express message and send to Physical layer by standard P IPE interface, simultaneously when the transmission buffer zone of asynchronous physical layer interface is sky, asynchronous physical layer interface detects the state of shaking hands of link, the success if shake hands compensate difference on the frequency between the soft core of PCI Express and Physical layer inserting SKP ordered set message on standard P IPE interface, the success if shake hands compensate difference on the frequency between the soft core of PCIExpress and Physical layer inserting the empty message of LIDLE logic on standard P IPE interface, when Physical layer sends PCI Express message by asynchronous physical layer interface to the soft core of PCI Express, asynchronous physical layer interface detects the state of shaking hands of link, the success if shake hands the PCIExpress message that receives is abandoned according to the ratio between the frequency of operation of the frequency of operation of frequency reducing PIPE interface and standard P IPE interface, and the PCI Express message that will not abandon writes the reception buffer zone of asynchronous physical layer interface, the success if shake hands the type of the PCI Express message that judgement receives, when being link layer message or transaction layer message, PCI Express message writes the reception buffer zone of asynchronous physical layer interface, when being the empty message of logic, PCI Express message all abandons, asynchronous physical layer interface sends to Physical layer with reception buffer zone buffer memory PCI Express message by frequency reducing PIPE interface.

As further improvement in the technical proposal of the present invention:

When by comprehensive highest frequency, the frequency of operation of frequency reducing PIPE interface being set according to PCI Express interface chip described step 3), the frequency of operation value rule of frequency reducing PIPE interface is suc as formula shown in (1);

f_l/f_s＝1，4/5，3/4，7/10，2/3，3/5，1/2，2/5 (1)

In formula (1), f_lBe the frequency of operation of frequency reducing PIPE interface, f_sFrequency of operation for standard P IPE interface.

The reception buffer zone capacity of described asynchronous physical layer interface satisfies the funtcional relationship of formula (2);

C_fifo＞C_tlp^*(1-(f_l-f_dllp)/f_s) (2)

In formula (2), C_FifoBe the capacity of reception buffer zone, C_tlpBe the transaction layer message reception buffer zone capacity (concrete numerical value and soft caryogamy are equipped with the pass, generally are no more than 32KB) of the soft core of PCI Express, f_DllpBe the maximum renewal frequency (concrete numerical value and soft caryogamy are equipped with the pass, generally are no more than 1MHz) of data link layer message, f_lBe the frequency of operation of frequency reducing PIPE interface, f_sFrequency of operation for standard P IPE interface.

When described step 4), the PCI Express message that receives being abandoned according to the ratio between the frequency of operation of the frequency of operation of frequency reducing PIPE interface and standard P IPE interface, the ratio of abandoning satisfies the funtcional relationship of formula (3);

M/(M+N)＝f_l/f_s (3)

In formula (3), M is the message number that receives continuously, the message number of N for abandoning continuously, f_lBe the frequency of operation of frequency reducing PIPE interface, f_sFrequency of operation for standard P IPE interface;

Simultaneously describedly abandon the funtcional relationship that ratio also satisfies formula (4) and (5):

f_l/f_s＝M/(M+N)＞8/(delay_tx+delay_link+delay_rx+16) (4)

f_l/f_s＞1/3 (5)

In formula (4), delay_txDelay, the delay of transmit leg_LinkDelay, the delay of physical link_rxTake over party's delay, delay_tx, delay_Link, delay_rxAll to send the time of an ordered set message as the unit interval on standard P IPE interface.

The PCI Express interface chip verification method that the present invention is based on asynchronous physical layer interface has following advantage:

(1) the present invention can realize and the communicating by letter of Standard PC I Express equipment, the soft core of PCIExpress and the difference on the frequency between Physical layer realized by asynchronous physical layer interface mate, after employing the present invention, the transmission receiving velocity of serial link all changes, asynchronous physical layer interface has guaranteed compatibility with PCI Express agreement to the deletion insertion process of data, therefore can with the proper communication of PCIExpress equipment, can realize PCI Express interface chip frequency reducing hardware verification.

(2) the present invention is based on standard P IPE interface, do not increase or reduce any signal, FPGA code to be verified can directly be connected with it, do not need to do any change, therefore the soft core of PCI Express and user logic code to be verified do not need to make any modification, has advantages of to realize simple and convenient, compatible existing test code.

(3) the present invention does not need the support of special hardware, can comprehensively be implemented in general FPGA verification platform as module code direct and to be verified, has advantages of that versatility is good, it is simple to realize, resources occupation rate is low.

Description of drawings

Fig. 1 is the structural representation of PCI Express interface chip in prior art.

Fig. 2 is the method flow schematic diagram of the embodiment of the present invention.

Fig. 3 is the structural representation after the asynchronous physical layer interface of PCI Express interface chip insertion in the embodiment of the present invention.

Fig. 4 syndeton schematic diagram that to be FPGA card authentication in the embodiment of the present invention (frequency reducing PCI Express equipment) be connected with PCI Express slot by PCI Express golden finger with server (Standard PC I Express equipment).

Fig. 5 is the framed structure schematic diagram of asynchronous physical layer interface in the embodiment of the present invention.

Embodiment

As shown in Figures 2 and 3, the present embodiment is as follows based on the implementation step of the PCIe interface chip hardware verification method of asynchronous physical layer interface:

1) build the FPGA hardware platform with Standard PC I Express interface, the PGA hardware platform is connected with main frame with PCI Express root node equipment by Standard PC IExpress interface;

2) insert between the soft core of PCI Express in PCI Express interface chip ASIC code to be verified and Physical layer for the poor asynchronous physical layer interface (as shown in Figure 3) of matching frequency, asynchronous physical layer interface comprises transmission buffer zone, reception buffer zone, frequency reducing PIPE interface and standard P IPE interface, and asynchronous physical layer interface is connected with the FPGA hardware platform, is connected with Physical layer by standard P IPE interface by frequency reducing PIPE interface;

3) PCI Express interface chip ASIC code to be verified is moved to the FPGA hardware platform and comprehensively realize, and according to PCI Express interface chip, the frequency of operation of frequency reducing PIPE interface is set by comprehensive highest frequency;

4) use test program is carried out functional test by the FPGA hardware platform to the soft core of PCI Express and the user logic of PCI Express interface chip, when the soft core of PCI Express sends PCI Express message by asynchronous physical layer interface to Physical layer, the soft core of PCI Express writes PCI Express message by frequency reducing PIPE interface the transmission buffer zone of asynchronous physical layer interface, asynchronous physical layer interface will send buffer cache PCI Express message and send to Physical layer by standard P IPE interface, simultaneously when the transmission buffer zone of asynchronous physical layer interface is sky, asynchronous physical layer interface detects the state of shaking hands of link, the success if shake hands compensate difference on the frequency between the soft core of PCI Express and Physical layer inserting SKP ordered set message on standard P IPE interface, the success if shake hands compensate difference on the frequency between the soft core of PCI Express and Physical layer inserting the empty message of LIDLE logic on standard P IPE interface, when Physical layer sends the PCIExpress message by asynchronous physical layer interface to the soft core of PCI Express, asynchronous physical layer interface detects the state of shaking hands of link, the success if shake hands the PCIExpress message that receives is abandoned according to the ratio between the frequency of operation of the frequency of operation of frequency reducing PIPE interface and standard P IPE interface, and the PCI Express message that will not abandon writes the reception buffer zone of asynchronous physical layer interface, the success if shake hands the type of the PCI Express message that judgement receives, when being link layer message or transaction layer message, PCI Express message writes the reception buffer zone of asynchronous physical layer interface, when being the empty message of logic, PCI Express message all abandons, asynchronous physical layer interface sends to Physical layer with reception buffer zone buffer memory PCI Express message by frequency reducing PIPE interface.

The present embodiment is (PHY Interface of PCI Express on PCI Express physical layer interface, abbreviation PIPE interface) realize frequency-dropping function, do not need to revise the soft core of PCI Express and user logic code, PCI Express after frequency reducing end equipment can and PCI Express root device between proper communication, adopt the mode of soft core to realize, resources occupation rate is low, can directly comprehensively realize to the FPGA verification platform with code to be verified.

As shown in Figure 4, the FPGA hardware platform with Standard PC I Express interface in the present embodiment is the FPGA card authentication, the FPGA card authentication is inserted on the PCI Express slot of server, thereby be connected with the Standard PC I Express equipment on server (with the main frame of PCI Express root node equipment) mainboard, consist of the FPGA hardware platform of a PCI Express interface chip FPGA verification system, so that the function of checking PCIExpress interface chip.

When by comprehensive highest frequency, the frequency of operation of frequency reducing PIPE interface being set according to PCI Express interface chip in the present embodiment, step 3), the frequency of operation value rule of frequency reducing PIPE interface is suc as formula shown in (1);

f_l/f_s＝1，4/5，3/4，7/10，2/3，3/5，1/2，2/5 (1)

In formula (1), f_lBe the frequency of operation of frequency reducing PIPE interface, f_sFrequency of operation for standard P IPE interface.In the present embodiment, the frequency of operation f of standard P IPE interface_sBe 125MHz, f_l/ f_sValue be 3/5,1/2,2/5 o'clock respectively the frequency of corresponding frequency reducing PIPE interface be 75MHz, 62.5MHz, 50MHz, can satisfy the soft core of PCI Express and use FPGA to carry out the frequency requirement of hardware verification.PCI Express interface chip ASIC code to be verified is moved to the FPGA hardware platform when comprehensively realizing, can adopt synthesis tool comprehensively to realize, the highest frequency that can be aggregated into according to PCI Express arranges the frequency of operation of frequency reducing PIPE interface.

In the present embodiment, the reception buffer zone capacity of asynchronous physical layer interface satisfies the funtcional relationship of formula (2);

C_fifo＞C_tlp*(1-(f_l-f_dllp)/f_s) (2)

In formula (2), C_FifoBe the capacity of reception buffer zone, C_tlpBe the transaction layer message reception buffer zone capacity (concrete numerical value and soft caryogamy are equipped with the pass, generally are no more than 32KB) of the soft core of PCI Express, f_DllpBe the maximum renewal frequency (concrete numerical value and soft caryogamy are equipped with the pass, generally are no more than 1MHz) of data link layer message, f_lBe the frequency of operation of frequency reducing PIPE interface, f_sFrequency of operation for standard P IPE interface.After the success of PCIe link handshake, only send the message of two types on the PIPE interface: transaction layer message (Transaction Layer Packet, be called for short TLP) and data link layer message (Data Link Layer Packet, be called for short DLLP), these two kinds of messages all write reception buffer zone as valid data, and the frequency that writes is f_s, to be read by the soft core of the PCIe of frequency reducing again simultaneously, the frequency of reading is f_l, because the speed that the velocity ratio of reading writes is slow, therefore have the part message buffering in asynchronous PIPE interface.The data link layer message is periodically to send, and maximum renewal frequency is f_Dllp, the speed that therefore is used for actual treatment TLP message is (f_l-f_Dllp), and the transaction layer message total volume that the soft core of PCI Express can receive is received buffer capacity C_tlpAs long as restriction is therefore the capacity C of reception buffer zone_Fifo＞C_tlp* (1-(f_l-f_Dllp)/f_s), just can prevent that reception buffer zone from overflowing.

When in the present embodiment, step 4), the PCI Express message that receives being abandoned according to the ratio between the frequency of operation of the frequency of operation of frequency reducing PIPE interface and standard P IPE interface, the ratio of abandoning satisfies the funtcional relationship of formula (3);

M/(M+N)＝f_l/f_s (3)

In formula (3), M is the message number that receives continuously, the message number of N for abandoning continuously, f_lBe the frequency of operation of frequency reducing PIPE interface, f_sFrequency of operation for standard P IPE interface;

The ratio that abandons simultaneously also satisfies the funtcional relationship of formula (4) and (5):

f_l/f_s＝M/(M+N)＞8/(delay_tx+delay_link+delay_rx+16) (4)

f_l/f_s＞1/3 (5)

In formula (4), delay_txDelay, the delay of transmit leg_LinkDelay, the delay of physical link_rxTake over party's delay, delay_tx, delay_Link, delay_rxAll to send the time of an ordered set message as the unit interval on standard P IPE interface.

In the present embodiment, when the transmission buffer zone is sky, asynchronous physical layer interface can insert the idle message of some PCIExpress normalized definitions on standard P IPE interface: asynchronous physical layer interface does not also insert SKP ordered set message before success in link handshake, insert the empty message of LIDLE logic after the link handshake success, compensate the difference on the frequency on asynchronous physical layer interface both sides with this, guarantee that the data on the standard asynchronous physical layer interface are not interrupted; According to PCI Express protocol specification, Standard PC I Express equipment can abandon it after receiving idle message, and therefore inserting these messages can not affect the normal operation of Standard PC I Express equipment.Asynchronous physical layer interface writes asynchronous physical layer interface reception buffer zone with the PCI Express message that receives by standard P IPE interface.According to PCI Express standard, the PCI Express message of receiving before the link handshake success is all the ordered set message, in order to mate the difference on the frequency on asynchronous PIPE interface both sides, need to abandon according to the ratio between the frequency of the frequency of frequency reducing PIPE interface and standard P IPE interface the ordered set message that receives, the ratio of abandoning satisfies the funtcional relationship of formula (3).Abandon the handshake procedure that the part message can have influence on PCI Express agreement, according to PCI Express protocol specification, state transitions need to satisfy two conditions in the link handshake process: (1) receives 8 continuous handshake message, and (2) have sent 16 same messages after receiving first handshake message of the other side continuously.Abandon in order to make the handshake procedure that the part message does not affect link, the highest ratio that can dropping packets satisfies the funtcional relationship of formula (4), in formula (4), and delay_tx, delay_Link, delay_rxBeing respectively transmit leg, physical link, take over party's delay, is all to send an ordered set message as the unit interval (for standard P IPE interface unit interval of 16bit/125MHz as 64ns) on standard P IPE interface.Delay_LinkAnd delay_rxBe the receive delay of link delay and Standard PC I Express equipment, usually unadjustable, delay_txBe the delay (comprising the delay of asynchronous PIPE module) of transmit leg, therefore can change lowest operating frequency by the control lag umber of beats.Consider the factors such as the overtime and retransmission time out of the credit of PCI Express agreement, f_l/ f_sMinimum value should greater than 1/3 (the corresponding minimum frequency reducing frequency of the standard P IPE interface of 16bit/125MHz is 41.67MHz), enough satisfy the frequency requirement of the soft veritification card of PCI Express.

After the link handshake success, the PCIExpress message that asynchronous physical layer interface receives has three kinds: the empty message of link layer message, transaction layer message and logic, wherein link layer message and transaction layer message are effective PCI Express data, the empty message of logic is just in order to fill the free time on link, the message that guarantees the continuity of data and send, abandoning the empty message of logic can not affect the correctness of PCIExpress data transmission.Asynchronous physical layer interface writes inner reception buffer zone with link layer message and the transaction layer message that receives, the empty message of logic all abandons, the control that the link layer message that can send due to transmit leg and transaction layer message amount are received credit, in order to prevent that receiving FIFO overflows, the reception buffer zone capacity satisfies the funtcional relationship of formula (2).Asynchronous physical layer interface is read link layer message and transaction layer message from reception buffer zone, and sends to the soft core of PCI Experss by frequency reducing PIPE interface, when reception buffer zone is sky, sends the empty message of logic to the soft core of PCI Experss.Regulate in this way the ratio of the empty message of logic of filling between PCI Express link layer and transaction layer message, thus the difference on the frequency on asynchronous physical layer interface both sides when compensation receives.

As shown in Figure 5, in the present embodiment, asynchronous physical layer interface upwards connects the soft core of PCIExpress by frequency reducing PIPE interface, connects physical layer block by standard P IPE interface downwards, and asynchronous PLIM is made of four parts.

(1) clock module

Clock module carries out frequency division with the clock of inputting on standard P IPE interface by frequency synthesizer PLL, and the frequency reducing clock that obtains uses for the soft core of PCIExpress to be verified, and asynchronous PIPE both sides clock ratio can be got following value:

Frequency reducing PIPE clock f_l/ standard P IPE clock f_s=Isosorbide-5-Nitrae/5,3/4,7/10,2/3,3/5,1/2,2/5

The selection of these values is can insert uniformly and the deletion message according to ratio of integers in PCI Express handshake procedure in order to guarantee, prevents that the message amount of insert continually and deletion from too much affecting PCI Express link handshake process.

(2) state and control module

State and control module realize the control of physical layer block and the collection of status signal, in the PIPE interface standard, defined signal is except PHYSTATUS and RXSTATUS signal, to following signal (TXDETECTRX, POWERDOWN, TXELECIDLE, RXELECIDLE, RXPOLARITY, TXCOMPLIANCE, RXVLAID) be left intact, signal corresponding on frequency reducing PIPE interface and standard P IPE interface directly is connected; PHYSTATUS and RXSTATUS signal demand are expanded phystatus and the rxstatus signal of Physical layer output, to guarantee to adopt this signal at clock zone at a slow speed, should satisfy following relation (phystatus and rxstatus are postponed four to be clapped or can satisfy this condition together) after after expansion, deration of signal ratio rounds: [T_l/ T_s]＞[f_s/ f_l], T_lThe cycle of PHYSTATUS and RXSTATUS on expression frequency reducing interface, T_sThe phystatus of expression physical layer interface output and the cycle of rxstatus.

(3) sending module

Sending module sends to the quick clock territory with the soft caryogenic data of PCI Express from clock zone at a slow speed, and sending module is divided into again following three submodules:

a) FIFO writing module: be used for to input data when the TXELECIDLE invalidating signal and write the transmission fifo module, the distinguishing mark that to input simultaneously data and PCI Express type of message compares that (ordered set is designated the COM symbol, the data link layer message be designated the SDP/ENDB/ENDG symbol, the transaction layer message be designated the STP/ENDB/ENDG symbol, the empty message of logic is complete zero), obtain the type of message PKT_TYPE of current data, can judge beginning and the end of message according to PKT_TYPE, when running into the message trailer sign, message total counter PKT_NUM adds 1 at every turn, PKT_NUM is converted to sends to the quick clock territory after gray code (Gray code) for the transmit control device module.

B) send fifo module: send the transmission buffer zone that fifo module is preceding method, be used for preserving data to be sent, sending fifo module has an empty sign prog_empty, and this empty sign prog_empty is set to 1 when remaining data bulk is less than 16 (maximum lengths of 2 ordered sets) in sending fifo module.At first the data that the transmit control device module is read from send fifo module also compare with the distinguishing mark of PCI Express type of message, obtain the type of message pkt_type of current data, according to beginning and the end of pkt_type judgement message, when running into the message trailer sign, message total counter pkt_num adds 1 at every turn.

C) transmit control device module: be used for from the FIFO sense data and send to Physical layer.

The course of work of transmit control device module is divided into following step:

The first step: will read useful signal and set to 0 (being rd_en=0), message is skipped total counter and is set to 0 (skp_num=0);

Second step: when the TXELECIDLE invalidating signal and when sending the empty sign of fifo module prog_empty and equaling 0, the transmit control device module enables to send reading useful signal (rd_en equals 1) beginning sense data and sending of fifo module, until prog_empty equal 1 and the data of current output be the head (type of message pkt_type equals ordered set sign COM) of an ordered set, will read useful signal and set to 0 (rd_en equals 0) and turned for the 3rd step; Perhaps run into the LIDL message and forwarded for the 4th step to.

The 3rd step: send continuously SKP ordered set message, until prog_empty equals 0, forward second step to;

the 4th step: (sending fifo module is asynchronous FIFO if pkt_num is less than PKT_NUM, packet counting will be carried out simultaneously at the end that writes and read of asynchronous FIFO, writing the end packet counting represents with PKT_NUM, reading the end packet counting represents with pkt_num, by comparing the size of these two counters, can know and whether also have message in asynchronous FIFO, therefore these two counters are with identical name, distinguish by capital and small letter) rd_en equal 1, sense data and send to Physical layer continuously from send FIFO, rd_en equals 0 and forwarded for the 5th step to when pkt_hum equals PKT_NUM,

The 5th step: send continuously the LIDL message, LIDL message skp_num of every transmission adds 1, inserts a SKP ordered set message and skp_num is clear 0 greater than 1000 the time as skp_num, until pkt_num turned for the 4th step during less than PKT_NUM;

In case in above-mentioned steps, the TXELECIDLE signal effectively get back to the first step.

(4) receiver module

Receiver module is divided into following three submodules:

A) receive controller module: receive and write the reception fifo module after controller module (RECV_CONTROLLER) filters the data that receive.

The course of work that receives controller module is divided into following step:

The first step: the distinguishing mark of receive data and type of message is compared (ordered set is designated the COM symbol, DLLP is designated the SDP/ENDB/ENDG symbol, TLP is designated the STP/ENDB/ENDG symbol, the empty message of logic is complete zero), thereby obtain the type of message rxpkt_type of current data, can judge that according to rxpkt_type the current data that receive are start of message (SOM), end or are in the middle of message;

Second step: if the current data of receiving are ordered set heading (being rxpkt_type=COM), beginning writes M ordered set message (write enable signal wt_en and equal 1) to receiving in fifo module continuously, then abandon N ordered set message (write enable signal wt_en and equal 0), if the data of receiving are logic sky messages forwarded for the 3rd step to;

The 3rd step: write continuously the empty message (write enable signal wt_en and equal 1) of M logic in FIFO to receiving, then abandon the empty message (write enable signal wt_en and equal 0) of N logic, forwarded for the 4th step to until current data is the data link layer heading;

The 4th step: if what receive is that the ordered set message forwards second step to, if data link layer message or transaction layer message write the reception fifo module, if the empty message of logic and current data are not that DLLP or transaction layer message abandon;

In case in the above-mentioned steps implementation, the rxelecidle of Physical layer output effectively directly get back to the first step.

B) receive fifo module: receive the reception buffer zone that fifo module is preceding method, receiving fifo module is the asynchronous FIFO of standard, receive the fifo module correspondence and be provided with a sky sign empty who is used for record storage dummy status, after the total data in receiving fifo module is read out, sky is indicated that empty puts 1.

C) FIFO reads module: receive when sky sign empty equals 0 FIFO to read enable signal effective, the data of reading from receive fifo module are directly exported, the empty message LIDL of output logic when sky sign empty equals 1.

The above is only the preferred embodiment of the present invention, and protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes that belongs under thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art, in the some improvements and modifications that do not break away under principle of the invention prerequisite, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (4)

Translated fromChinese

1.一种基于异步物理层接口的PCIe接口芯片硬件验证方法，其特征在于实施步骤如下：1. a kind of PCIe interface chip hardware verification method based on asynchronous physical layer interface, it is characterized in that implementation steps are as follows:1)构建具有标准PCI Express接口的FPGA硬件平台，将所述FPGA硬件平台通过标准PCI Express接口与带有PCI Express根节点设备的主机相连；1) build the FPGA hardware platform with standard PCI Express interface, described FPGA hardware platform is connected with the host computer that has PCI Express root node device by standard PCI Express interface;2)在待验证的PCI Express接口芯片ASIC代码中的PCI Express软核与物理层之间插入用于匹配频率差的异步物理层接口，所述异步物理层接口包含发送缓冲区、接收缓冲区、降频PIPE接口和标准PIPE接口，所述异步物理层接口通过降频PIPE接口与FPGA硬件平台相连、通过标准PIPE接口与物理层相连；2) Insert between the PCI Express soft core and the physical layer in the PCI Express interface chip ASIC code to be verified and be used for matching the asynchronous physical layer interface of frequency difference, described asynchronous physical layer interface comprises sending buffer, receiving buffer, A frequency reduction PIPE interface and a standard PIPE interface, the asynchronous physical layer interface is connected to the FPGA hardware platform through the frequency reduction PIPE interface, and is connected to the physical layer through the standard PIPE interface;3)将所述待验证的PCI Express接口芯片ASIC代码迁移到所述FPGA硬件平台综合实现，并根据PCI Express接口芯片被综合的最高频率设置降频PIPE接口的工作频率；3) the PCI Express interface chip ASIC code to be verified is migrated to the integrated realization of the FPGA hardware platform, and the operating frequency of the down-frequency PIPE interface is set according to the integrated highest frequency of the PCI Express interface chip;4)使用测试程序通过所述FPGA硬件平台对PCI Express接口芯片的PCI Express软核和用户逻辑进行功能测试；当PCI Express软核通过异步物理层接口向物理层发送PCI Express报文时，PCI Express软核通过降频PIPE接口将PCI Express报文写入异步物理层接口的发送缓冲区，异步物理层接口将发送缓冲区缓存PCI Express报文通过标准PIPE接口发送给物理层，同时当异步物理层接口的发送缓冲区为空时，异步物理层接口检测链路的握手状态，如果握手未成功则在标准PIPE接口上插入SKP有序集报文来补偿PCI Express软核与物理层之间的频率差，如果握手已经成功则在标准PIPE接口上插入LIDLE逻辑空报文来补偿PCIExpress软核与物理层之间的频率差；当物理层通过异步物理层接口向PCI Express软核发送PCI Express报文时，异步物理层接口检测链路的握手状态，如果握手未成功则将接收到的PCIExpress报文按照降频PIPE接口的工作频率和标准PIPE接口的工作频率之间的比值进行丢弃，并将未丢弃的PCI Express报文写入异步物理层接口的接收缓冲区，如果握手已经成功则判断接收到的PCI Express报文的类型，当PCI Express报文是链路层报文或者事务层报文时写入异步物理层接口的接收缓冲区，当PCI Express报文是逻辑空报文时全部丢弃，异步物理层接口将接收缓冲区缓存PCI Express报文通过降频PIPE接口发送给物理层。4) use test program to carry out function test to the PCI Express soft core and user logic of PCI Express interface chip by described FPGA hardware platform; When PCI Express soft core sends PCI Express message to physical layer by asynchronous physical layer interface, PCI Express The soft core writes the PCI Express message into the sending buffer of the asynchronous physical layer interface through the down-frequency PIPE interface, and the asynchronous physical layer interface buffers the PCI Express message in the sending buffer and sends it to the physical layer through the standard PIPE interface. When the sending buffer of the interface is empty, the asynchronous physical layer interface detects the handshake status of the link. If the handshake is unsuccessful, an SKP ordered set message is inserted on the standard PIPE interface to compensate for the frequency between the PCI Express soft core and the physical layer. Poor, if the handshake is successful, insert a LIDLE logical empty message on the standard PIPE interface to compensate for the frequency difference between the PCIExpress soft core and the physical layer; when the physical layer sends a PCI Express message to the PCI Express soft core through the asynchronous physical layer interface , the asynchronous physical layer interface detects the handshake status of the link. If the handshake is unsuccessful, the received PCIExpress packets are discarded according to the ratio between the working frequency of the down-clocked PIPE interface and the working frequency of the standard PIPE interface, and unused The discarded PCI Express message is written into the receiving buffer of the asynchronous physical layer interface. If the handshake is successful, the type of the received PCI Express message is judged. When the PCI Express message is a link layer message or a transaction layer message Write to the receiving buffer of the asynchronous physical layer interface. When the PCI Express message is a logical empty message, all are discarded. The asynchronous physical layer interface buffers the PCI Express message in the receiving buffer and sends it to the physical layer through the down-frequency PIPE interface.2.根据权利要求1所述的基于异步物理层接口的PCIe接口芯片硬件验证方法，其特征在于，所述步骤3)中根据PCI Express接口芯片被综合的最高频率设置降频PIPE接口的工作频率时，降频PIPE接口的工作频率取值规则如式(1)所示；2. the PCIe interface chip hardware verification method based on the asynchronous physical layer interface according to claim 1, it is characterized in that, in described step 3) according to the integrated highest frequency setting of PCI Express interface chip, the operating frequency of down-frequency PIPE interface When , the working frequency value selection rule of the down-frequency PIPE interface is shown in formula (1);f_l/f_s＝1，4/5，3/4，7/10，2/3，3/5，1/2，2/5    (1)f_l /f_s = 1, 4/5, 3/4, 7/10, 2/3, 3/5, 1/2, 2/5 (1)式(1)中，f_l为降频PIPE接口的工作频率，f_s为标准PIPE接口的工作频率。In the formula (1), f_l is the working frequency of the down-frequency PIPE interface, and f_s is the working frequency of the standard PIPE interface.3.根据权利要求1所述的基于异步物理层接口的PCIe接口芯片硬件验证方法，其特征在于，所述异步物理层接口的接收缓冲区容量满足式(2)的函数关系；3. the PCIe interface chip hardware verification method based on asynchronous physical layer interface according to claim 1, is characterized in that, the receiving buffer capacity of described asynchronous physical layer interface satisfies the functional relation of formula (2);C_fifo＞C_tlp*(1-(f_l-f_dllp)/f_s)    (2)C_fifo >C_tlp *(1-(f_l -f_dllp )/f_s ) (2)式(2)中，C_fifo为接收缓冲区的容量，C_tlp为PCI Express软核的事务层报文接收缓冲区容量，f_dllp为数据链路层报文的最大更新频率，f_l为降频PIPE接口的工作频率，f_s为标准PIPE接口的工作频率。In the formula (2), C_fifo is the capacity of the receiving buffer, C_tlp is the transaction layer message receiving buffer capacity of the PCI Express soft core, f_dllp is the maximum update frequency of the data link layer message, and f_l is the drop rate frequency PIPE interface operating frequency, f_s is the operating frequency of the standard PIPE interface.4.根据权利要求1或2或3所述的基于异步物理层接口的PCIe接口芯片硬件验证方法，其特征在于：所述步骤4)中将接收到的PCI Express报文按照降频PIPE接口的工作频率和标准PIPE接口的工作频率之间的比值进行丢弃时，丢弃比例满足式(3)的函数关系；4. according to claim 1 or 2 or 3 described based on the PCIe interface chip hardware verification method of asynchronous physical layer interface, it is characterized in that: the PCI Express message that will receive in described step 4) according to down-frequency PIPE interface When the ratio between the operating frequency and the operating frequency of the standard PIPE interface is discarded, the discarding ratio satisfies the functional relationship of formula (3);M/(M+N)＝f_l/f_s    (3)M/(M+N)＝f_l /f_s (3)式(3)中，M为连续接收的报文个数，N为连续丢弃的报文个数，f_l为降频PIPE接口的工作频率，f_s为标准PIPE接口的工作频率；In formula (3), M is the number of messages received continuously, N is the number of messages discarded continuously, f_l is the operating frequency of the down-frequency PIPE interface, and f_s is the operating frequency of the standard PIPE interface;同时所述丢弃比例还满足式(4)和(5)的函数关系：Simultaneously described discard ratio also satisfies the functional relationship of formula (4) and (5):f_l/f_s＝M/(M+N)＞8/(delay_tx+delay_link+delay_rx+16)    (4)f_l /f_s ＝M/(M+N)＞8/(delay_tx +delay_link +delay_rx +16) (4)fl/f_s＞1/3    (5)fl/f_s >1/3 (5)式(4)中，delay_tx是发送方的延迟、delay_link是物理链路的延迟、delay_rx是接收方的延迟，delay_tx、delay_link、delay_rx都是以在标准PIPE接口上发送一个有序集报文的时间作为单位时间。In formula (4), delay_tx is the delay of the sender, delay_link is the delay of the physical link, and delay_rx is the delay of the receiver. Delay_tx , delay_link , and delay_rx are based on sending an effective link on the standard PIPE interface. The time of the sequenced message is taken as the unit time.

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