CN103152275A - Router suitable for network on chip and allowable for configuring switching mechanisms - Google Patents

Abstract

Translated fromChinese

本发明属于集成电路的片上网络技术领域，具体为一种可配置为电路交换或包交换两种交换机制的路由器。通常的路由器由输入缓冲队列、路由计算模块、仲裁器和交换开关组成，具有东、南、西、北和本地5组端口。本发明在通常路由器的数据输入端口增加一个二选一的数据选择器（MUX），外部输入的数据分两个支路，一路与MUX的一个端口连接，另一路通过输入缓冲队列后与MUX的另一端口相连。本发明可在不明显增加电路总面积的前提下根据数据包长灵活地选择不同的交换机制，从而充分发挥两种交换机制在各自特定包长下的通信效率和能量效率的优势。

The invention belongs to the technical field of on-chip networks of integrated circuits, and in particular relates to a router which can be configured as two switching mechanisms of circuit switching or packet switching. A common router is composed of an input buffer queue, a routing calculation module, an arbiter and a switching switch, and has 5 groups of ports of east, south, west, north and local. The present invention adds a two-to-one data selector (MUX) to the data input port of the usual router. The externally input data is divided into two branches. connected to another port. The present invention can flexibly select different switching mechanisms according to the data packet length without obviously increasing the total area of the circuit, thereby giving full play to the advantages of the communication efficiency and energy efficiency of the two switching mechanisms under their respective specific packet lengths.

Description

Translated fromChinese

一种适用于片上网络的可配置交换机制的路由器A Router with Configurable Switching Mechanism Suitable for Network-on-Chip

技术领域technical field

本发明属于集成电路的片上网络技术领域，具体涉及一种适用于片上网络的可配置交换机制的路由器。The invention belongs to the technical field of on-chip networks of integrated circuits, and in particular relates to a router with a configurable switching mechanism suitable for on-chip networks.

背景技术Background technique

近年来，随着半导体工艺水平和集成电路设计技术的飞速发展，以软硬件协同设计、IP复用和超深亚微米技术为支撑的SoC设计方法逐渐成为超大规模集成电路（VLSI）的主流设计技术。人们在一个芯片上集成一个或者更多的IP核成为现实。与此同时，提升单核的性能变得越来越困难，为此人们提出了多核的设计方法，采用多个低功耗的单核协同工作，以面积来换取性能的提升及功耗的降低。在未来大规模应用的一块芯片中可能集成几十甚至上百个IP核，IP核之间的互联和通信变得越来越复杂，传统的总线结构已经很难满足芯片模块间的通信需求，存在着诸多的局限性。而片上网络（Network-on-chip，NoC）由于优良的并行性、可扩展性和较高的通信效率，成为多核处理器系统最理想的互联结构。In recent years, with the rapid development of semiconductor technology level and integrated circuit design technology, the SoC design method supported by software and hardware co-design, IP multiplexing and ultra-deep submicron technology has gradually become the mainstream design of VLSI. technology. It becomes a reality to integrate one or more IP cores on a chip. At the same time, it is becoming more and more difficult to improve the performance of a single core. For this reason, people have proposed a multi-core design method, using multiple low-power single-cores to work together to exchange area for performance improvement and power consumption reduction. . In the future, dozens or even hundreds of IP cores may be integrated in a chip for large-scale application. The interconnection and communication between IP cores become more and more complicated. The traditional bus structure has been difficult to meet the communication requirements between chip modules. There are many limitations. The Network-on-chip (NoC) has become the most ideal interconnection structure for multi-core processor systems due to its excellent parallelism, scalability and high communication efficiency.

片上网络的路由模块负责各IP核之间的连接和通信，是片上网络的拓扑结构、路由算法、交换机制、流控机制、仲裁算法、服务质量、容错性能的硬件实现单元，对系统的数据吞吐率、通信延时、面积、功耗等有着举足轻重的作用。The routing module of the on-chip network is responsible for the connection and communication between IP cores. Throughput rate, communication delay, area, power consumption, etc. play a decisive role.

片上网络中，交换机制决定着一段数据以怎样的方式从源节点出发，通过路径上的各交换节点最终传输到目的节点的过程，交换机制直接影响着网络的延时、吞吐率和能量效率。In an on-chip network, the switching mechanism determines how a piece of data starts from the source node and is finally transmitted to the destination node through the switching nodes on the path. The switching mechanism directly affects the delay, throughput and energy efficiency of the network.

电路交换（Circuit Switch）是一种面向连接的交换机制。它要求每次传输数据前都要在源节点和目的节点之间建立一条物理专用链路。一次完整的电路交换分为4个阶段，首先源节点向网络中发送一个含有源地址和目的地址信息的建立包，该建立包根据路由算法边路由边建立路径，最终到达目的节点。接着，目的节点向源节点返还一个应答包，表示通信路径已经完整建立，可以传输。当源节点收到此应答包后，正式的数据传输开始，直到发送完毕。最后，源节点向目的节点发送一个释放包，释放包沿着之前建立的路径边路由边释放已占链路，供其他数据传输使用。Circuit Switching (Circuit Switch) is a connection-oriented switching mechanism. It requires the establishment of a physical dedicated link between the source node and the destination node before each data transmission. A complete circuit switching is divided into four stages. First, the source node sends a setup packet containing source address and destination address information to the network. The setup packet establishes a path while routing according to the routing algorithm, and finally reaches the destination node. Then, the destination node returns a response packet to the source node, indicating that the communication path has been completely established and can be transmitted. When the source node receives the response packet, the formal data transmission starts until the sending is completed. Finally, the source node sends a release packet to the destination node, and the release packet is routed along the previously established path to release the occupied link for other data transmission.

包交换（Packet Switch）是一种无连接的交换机制，它并不要求源、目的节点在数据正式发送前建立一个类似硬连线的电路连接，而是将数据（或称消息Message）切割成几组（或称数据包Packet），每个Packet含有一定长度的微片（flit），微片的位宽和通道宽度相同。每个数据包的第一个微片为包头，含有源地址、目的地址、包长等信息。然后每组数据在网络中边路由边前进。Packet Switching (Packet Switch) is a connectionless switching mechanism. It does not require the source and destination nodes to establish a hardwired circuit connection before the data is officially sent, but cuts the data (or message Message) into Several groups (or data packets Packet), each Packet contains flits of a certain length, and the bit width of the flits is the same as the channel width. The first microchip of each data packet is the packet header, which contains information such as source address, destination address, and packet length. Each set of data is then routed through the network as it progresses.

在通信与多媒体应用下，通过挖掘程序的任务级并行性，可将程序映射到多核处理器中。在程序工作时，核间通信的数据长度多则上百甚至上千字（Word），少则几个字（Word）。假设一个片上网络只支持电路交换机制，则传输几个字时的建链和拆链所花费的时间远高于实际数据传输所用的时间，造成延时增大；若假设只支持包交换机制，在发送大量数据前会拆分成多个小的数据包，并在每个数据包前加一个含有地址信息的包头，这样一方面每个数据包的路由延时累加会带来不小的延时，另一方面额外增加的包头也会导致传输的有效数据率下降。所以，单一的交换机制不可能使片上网络在面向所有情况下的数据通信达到性能最优，在实际应用中，NoC需要能够同时支持电路交换和包交换两种通信的交换机制，它们具体的应用的情形如下：In communication and multimedia applications, by mining the task-level parallelism of the program, the program can be mapped to the multi-core processor. When the program is working, the length of the inter-core communication data ranges from hundreds or even thousands of words (Word) to as few as a few words (Word). Assuming that an on-chip network only supports the circuit switching mechanism, the time it takes to establish and tear down the link when transmitting a few words is much higher than the time used for actual data transmission, resulting in increased delay; if it is assumed that only the packet switching mechanism is supported, Before sending a large amount of data, it will be split into multiple small data packets, and a packet header containing address information will be added in front of each data packet, so that on the one hand, the accumulation of routing delays for each data packet will bring a considerable delay On the other hand, additional headers will also lead to a decrease in the effective data rate of the transmission. Therefore, it is impossible for a single switching mechanism to optimize the data communication performance of the network on chip in all situations. In practical applications, NoC needs to be able to support both circuit switching and packet switching communication switching mechanisms. Their specific applications The situation is as follows:

包交换应用于：1）少量数据传输，主要用来配置模块、传递参数、同步电路等；2） 偶然的突发的数据流传输，即不需要长时间占用某一通道。电路交换应用于：1） 大量数据流的传输；2）两点间在某一时间段内频繁地间断的数据交换，即长时间占用某一通道。Packet switching is used for: 1) a small amount of data transmission, mainly used to configure modules, transfer parameters, synchronize circuits, etc.; 2) occasional burst data stream transmission, that is, it does not need to occupy a certain channel for a long time. Circuit switching is applied to: 1) the transmission of a large number of data streams; 2) frequent and intermittent data exchange between two points within a certain period of time, that is, a certain channel is occupied for a long time.

发明内容Contents of the invention

本发明的目的在于提供一种适用于片上网络的可根据发送数据的包长灵活地选择不同交换机制（具体为电路交换（Circuit Switch）和包交换（Packet Switch）两种交换机制）的路由器，并具有面积小、功耗低、通信效率高的优点。The purpose of the present invention is to provide a router suitable for on-chip networks that can flexibly select different switching mechanisms (specifically two switching mechanisms, circuit switching (Circuit Switch) and packet switching (Packet Switch)) according to the packet length of the sent data. And it has the advantages of small area, low power consumption and high communication efficiency.

基于以上发明目的，本发明提出一种可配置交换机制的路由器。在目前通常用的路由器基础上增加一个数据选择器（MUX）和一些控制信号，使得路由器的交换机制可以配置为电路交换或者包交换。Based on the purpose of the above invention, the present invention proposes a router with a configurable switching mechanism. A data selector (MUX) and some control signals are added on the basis of the currently commonly used routers, so that the switching mechanism of the router can be configured as circuit switching or packet switching.

具体地说，通常用的路由器一般有以下模块组成：输入缓冲队列、路由计算模块、仲裁器和交换开关，具有东、南、西、北和本地5组端口，外部输入的数据通过输入缓冲队列后送给交换开关，一般只支持单一的交换机制，如图1所示。Specifically, a commonly used router generally consists of the following modules: an input buffer queue, a routing calculation module, an arbiter and a switch, with 5 groups of ports of east, south, west, north and local, and externally input data passes through the input buffer queue After sending to the switching switch, generally only a single switching mechanism is supported, as shown in Figure 1.

本发明提出的可配置交换机制的路由器，是在上述通常用的路由器的数据输入端口增加一个二选一的数据选择器（MUX），外部输入的数据分两个支路，一个支路与MUX的一个端口连接，另一个支路通过输入缓冲队列后与MUX的另一个端口相连，如图2所示。The router with a configurable switching mechanism proposed by the present invention is to add a two-to-one data selector (MUX) at the data input port of the above-mentioned commonly used router, and the externally input data is divided into two branches, one branch and MUX One port of the MUX is connected, and the other branch is connected to another port of the MUX after passing through the input buffer queue, as shown in Figure 2.

本发明提出的可配置交换机制的路由器，在电路交换机制下，设置包头中相应的配置位，将MUX的输出通道来源切换至外部输入的数据，从而使数据不通过输入缓冲队列而直接输出，同时关断输入缓冲队列的时钟，以节约功耗、降低延时。The router with a configurable switching mechanism proposed by the present invention, under the circuit switching mechanism, sets the corresponding configuration bit in the packet header, switches the source of the output channel of the MUX to externally input data, so that the data is directly output without passing through the input buffer queue, At the same time, the clock of the input buffer queue is turned off to save power consumption and reduce delay.

 本发明提出的可配置交换机制的路由器，其电路交换的建立路径配置包通过包交换方式路由，具有共用路由计算模块，以减小硬件开销。In the router with a configurable switching mechanism proposed by the present invention, the path configuration packet of circuit switching is routed through packet switching, and has a common routing calculation module to reduce hardware overhead.

本发明提出的可配置交换机制的路由器，其在输出仲裁方面设定电路交换请求包的仲裁优先级高于包交换，以减少电路交换的阻塞等待时间，提高网络吞吐量、减少延时。The router with a configurable switching mechanism proposed by the present invention sets the arbitration priority of circuit switching request packets higher than packet switching in terms of output arbitration, so as to reduce the blocking waiting time of circuit switching, improve network throughput and reduce delay.

本发明提出的可配置交换机制的路由器，其电路交换和包交换机制共用输出交换开关，以减小硬件开销。In the router with a configurable switching mechanism proposed by the invention, the circuit switching and packet switching mechanisms share an output switching switch to reduce hardware overhead.

本发明提出的可配置交换机制的路由器，其数据包格式如图3所示。其中，“建立”位作为路由器的交换机制模式的配置信号。“交换机制模式”信号一路与MUX的选择端连接，另一路与时钟“相与”后送给输入缓冲队列，可作为门控时钟，降低系统功耗，如图4所示。The data packet format of the router with a configurable switching mechanism proposed by the present invention is shown in FIG. 3 . Among them, the "establish" bit is used as a configuration signal of the switching mechanism mode of the router. One path of the “Swap Mechanism Mode” signal is connected to the selection terminal of the MUX, and the other path is “ANDed” with the clock and then sent to the input buffer queue, which can be used as a gate control clock to reduce system power consumption, as shown in Figure 4.

本发明的可配置交换机制的路由器，其工作过程如下：The router of the configurable switching mechanism of the present invention, its work process is as follows:

（1）系统初始工作在包交换机制下，当有数据发送时，路由计算模块去检测包头的“建立”位。当此位为高电平时，表示将交换机制的模式配置为电路交换。此时将MUX输出选择来自外部的数据，并且将输入缓冲队列的时钟关断；(1) The system initially works under the packet switching mechanism. When there is data to be sent, the routing calculation module detects the "establishment" bit of the packet header. When this bit is high, it means that the mode of the switching mechanism is configured as circuit switching. At this time, the MUX output selects data from the outside, and the clock of the input buffer queue is turned off;

（2）当不同端口的路由计算模块在同一时刻向某一端口的发出输出请求时，优先响应电路交换建立包的申请。当电路交换建立包通过仲裁后，固定该交换通路的连接；(2) When the routing calculation modules of different ports send output requests to a certain port at the same time, they will respond to the application of the circuit switching establishment packet first. When the circuit switching establishment packet passes the arbitration, the connection of the switching path is fixed;

（3）当电路交换建立包到达目的节点时，目的节点向源节点发送一个应答包，表示链路建立完成。源节点接受到应答包后开始传输数据，并在最后一个数据包时将“释放”位拉高，释放链路资源，结束一个电路交换传输数据的过程；(3) When the circuit switching establishment packet arrives at the destination node, the destination node sends a response packet to the source node, indicating that the link establishment is completed. The source node starts to transmit data after receiving the response packet, and pulls the "release" bit high at the last data packet to release link resources and end a process of circuit switching data transmission;

（4）当有数据发送时，路由计算模块去检测包头的“建立”位。当此位为低电平时，表示将交换机制的模式保持为包交换。此后，数据包通过输入缓冲队列发送，并且缓冲队列时钟正常工作。(4) When there is data to send, the routing calculation module detects the "establishment" bit of the packet header. When this bit is low, it means that the mode of the switching mechanism is kept as packet switching. Thereafter, packets are sent through the input buffer queue, and the buffer queue clock works normally.

传统的路由器只支持单一的交换机制，灵活性不强。本发明的优点在于充分挖掘硬件的复用性，可在不明显增加电路总面积的前提下根据数据包长灵活地选择不同的交换机制，从而充分发挥了两种交换机制在各自特定包长下的通信效率和能量效率的优势。Traditional routers only support a single switching mechanism, and their flexibility is not strong. The invention has the advantages of fully exploiting the reusability of the hardware, and can flexibly select different switching mechanisms according to the length of the data packet without significantly increasing the total area of the circuit, thereby fully utilizing the two switching mechanisms under the respective specific packet lengths. The advantages of communication efficiency and energy efficiency.

附图说明Description of drawings

图1  片上网络路由器的通常组成结构。Figure 1. The general structure of a network-on-chip router.

图2  可配置交换机制的路由器结构。Figure 2. Router structure with configurable switching mechanism.

图3  数据包格式示意图。Figure 3 Schematic diagram of the packet format.

图4  “交换机制模式信号”控制电路图。Figure 4 "Switch Mechanism Mode Signal" control circuit diagram.

具体实施方式Detailed ways

可配置交换机制路由器的数据包分为以下类型：包交换的包头、数据体包，电路交换的建立包、应答包、数据体包、释放包。除了数据体包，其它包的格式是一样的，如图3所示。释放位只在电路交换过程中有意义，当其为高电平时表示释放包，其余时间为低电平；对于包交换中的包头，若建立位为1，则为电路交换建立包，若应答位为1，则为应答包，若建立位和应答位都为0，则为包交换的包头。源地址和目的地址都是6位，高三位为Y坐标，低三位为X坐标。包长为5位，表明包交换一次发送的微片数目包括头微片长度最大为31。The data packets of the configurable switching mechanism router are divided into the following types: packet header, data body packet for packet switching, establishment packet, response packet, data body packet, and release packet for circuit switching. Except for the data body package, the formats of other packages are the same, as shown in FIG. 3 . The release bit is only meaningful in the process of circuit switching. When it is high, it means to release the packet, and the rest of the time is low; for the packet header in packet switching, if the establishment bit is 1, the packet is established for circuit switching. If the bit is 1, it is a response packet, if both the establishment bit and the response bit are 0, it is the header of the packet exchange. Both the source address and the destination address are 6 bits, the upper three bits are the Y coordinate, and the lower three bits are the X coordinate. The packet length is 5 bits, indicating that the number of microchips sent at one time in packet switching, including the length of the header microchip, is up to 31.

可配置交换机制的路由器初始工作在包交换模式，此时若需要通过包交换方式向某一节点发送n（n<31）个微片的数据，则先发送一个头微片，释放、建立、应答位都为0，源地址为本地地址，包长为包括头微片的数量，接着发送体微片，即有效数据。当一个中间结点收到头微片时，通过解析目的地址进行路由计算后申请一个输出端口，这个输出端口会一直保持下去，直到后面的体微片发送完毕。 The router with a configurable switching mechanism initially works in the packet switching mode. At this time, if it is necessary to send n (n<31) microchip data to a certain node through packet switching, it first sends a header microchip, releases, establishes, and The response bits are all 0, the source address is the local address, the packet length is the number including the header flits, and then the body flits, that is, valid data, are sent. When an intermediate node receives the header flit, it applies for an output port after analyzing the destination address for routing calculation, and this output port will remain until the subsequent body flits are sent. the

当需要使用电路交换方式时，则先向网络发送一个建立包，它和正常头微片的区别是建立位为1、包长为5’b11111，之后建立包会边路由边建立路径，同时将沿途路由器切入电路交换模式以及将相应端口的输入缓冲队列的时钟关断，直到建立包到达目的节点。到达后，目的节点将建立包的源地址和目的地址互换并将应答位置1、建立位清零、包长设为1后改造成应答包发送出去。源节点在收到应答包时可确认该路径建立成功，于是开始发送数据。数据在已经建立好的从源节点到目的节点之间的组合逻辑路径高速无阻塞地传输，在发送最后一位数据时将释放位置1，则最后一个数据边传输边释放路径，路由器切回至包交换模式。When the circuit switching mode needs to be used, firstly send a setup packet to the network. The difference between it and the normal header chip is that the setup bit is 1 and the packet length is 5'b11111. After that, the setup packet will establish a path while routing, and at the same time Routers along the way switch into circuit switching mode and turn off the clock of the input buffer queue of the corresponding port until the establishment packet reaches the destination node. After arriving, the destination node will exchange the source address and the destination address of the establishment packet and change the response packet to 1, clear the establishment bit, and set the packet length to 1, and send it out. When the source node receives the response packet, it can confirm that the path is successfully established, and then starts to send data. The data is transmitted at high speed and non-blockingly on the established combined logical path from the source node to the destination node. When the last bit of data is sent, the position 1 will be released, and the path will be released while the last data is being transmitted, and the router will switch back to Packet switching mode.

当不同端口的路由计算模块在同一时刻向某一端口的发出输出请求时，以及当某一端口正在发送数据时有新的输出请求出现时，本端口需要按照一定规则仅响应其中的一个请求。这个规则就是仲裁算法，由仲裁器实现。本发明采用了改进的轮询仲裁算法，即优先查询电路交换的建立包申请，再按照固定的顺序轮流查询各个端口的请求信号。这样可以减少端口的空闲占用时间，降低链路资源竞争的概率。When the routing calculation modules of different ports send output requests to a certain port at the same time, and when a new output request appears when a certain port is sending data, the port needs to respond to only one of the requests according to certain rules. This rule is the arbitration algorithm, implemented by the arbitrator. The invention adopts an improved polling arbitration algorithm, that is, it first inquires the application for establishing a packet of circuit switching, and then inquires the request signals of each port in turn according to a fixed order. This can reduce the idle time of the port and reduce the probability of link resource competition.

Claims (5)

Translated fromChinese

1. 一种适用于片上网络的可配置交换机制的路由器，有以下模块组成：输入缓冲队列、路由计算模块、仲裁器和交换开关，具有东、南、西、北和本地5组端口，其特征在于：在数据输入端口增设一个二选一的数据选择器，外部输入的数据分两个支路，一个支路与所述数据选择器的一个端口连接，另一个支路通过输入缓冲队列后与所述数据选择器的另一个端口相连。1. A router with a configurable switching mechanism suitable for on-chip networks, which consists of the following modules: input buffer queue, routing calculation module, arbitrator and switching switch, with 5 groups of ports of east, south, west, north and local, among which It is characterized in that a data selector is added to the data input port, and the externally input data is divided into two branches, one branch is connected to a port of the data selector, and the other branch passes through the input buffer queue Connect with another port of the data selector.2. 根据权利要求1所述的可配置交换机制的路由器，其特征在于在电路交换机制下，设置包头中相应的配置位，将所述数据选择器的输出通道来源切换至外部输入的数据，从而使数据不通过输入缓冲队列而直接输出，同时关断输入缓冲队列的时钟，以节约功耗、降低延时。2. The router of the configurable switching mechanism according to claim 1, characterized in that under the circuit switching mechanism, the corresponding configuration bit in the header is set, the output channel source of the data selector is switched to the externally input data, Therefore, the data is directly output without passing through the input buffer queue, and at the same time, the clock of the input buffer queue is turned off, so as to save power consumption and reduce delay.3. 根据权利要求2所述的可配置交换机制的路由器，其特征在于电路交换的建立路径配置包通过包交换方式路由，具有共用路由计算模块，以减小硬件开销。3. The router with configurable switching mechanism according to claim 2, characterized in that the path configuration packet of circuit switching is routed through packet switching, and has a shared routing calculation module to reduce hardware overhead.4. 根据权利要求3所述的可配置交换机制的路由器，其特征在于在输出仲裁方面设定电路交换请求包的仲裁优先级高于包交换，以减少电路交换的阻塞等待时间，提高网络吞吐量、减少延时。4. The router with configurable switching mechanism according to claim 3, characterized in that the arbitration priority of the circuit switching request packet is set higher than the packet switching in the output arbitration, so as to reduce the blocking waiting time of the circuit switching and improve the network throughput amount and reduce delay.5. 根据权利要求4所述的可配置交换机制的路由器，其特征在于电路交换和包交换机制共用输出交换开关，以减小硬件开销。5. The router with configurable switching mechanism according to claim 4, characterized in that circuit switching and packet switching mechanisms share an output switching switch to reduce hardware overhead.

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