技术领域technical field
本发明涉及存储器的技术领域，特别是涉及一种存储器的感测放大器与一种位线对的电压判读方法。The invention relates to the technical field of memory, in particular to a sense amplifier of the memory and a method for judging the voltage of a bit line pair.
背景技术Background technique
在现有的存储器技术中，有些是采用模拟的感测放大器(sense amplifier)来进行位线对(bit line pair)的讯号放大工作。模拟的感测放大器具有操作速度快的优点，然由于这种感测放大器是以差动放大器(differential amplifier)来实现，故常因制程问题而发生晶体管的临界电压(Vth)不同的问题(即所谓的mismatch问题)，导致这种感测放大器会有电压偏移(offset)的缺点。In existing memory technologies, some analog sense amplifiers are used to amplify signals of bit line pairs. The analog sense amplifier has the advantage of fast operation speed. However, since this sense amplifier is implemented as a differential amplifier, the problem of different threshold voltages (Vth) of transistors often occurs due to process problems (the so-called The mismatch problem), resulting in the disadvantage of this sense amplifier having a voltage offset (offset).
此外，有些存储器技术是采用数字的感测放大器来进行讯号放大的工作，然而因数字的感测放大器需要以全摆幅(full swing)的方式来进行操作，故其有操作速度慢的缺点。In addition, some memory technologies use digital sense amplifiers to amplify signals. However, since digital sense amplifiers need to operate in a full swing mode, they have the disadvantage of slow operation speed.
发明内容Contents of the invention
本发明提供一种感测放大器，其操作速度快，且电压偏移问题小。The present invention provides a sense amplifier with fast operation speed and less voltage offset problem.
本发明还提供一种位线对的电压判读方法，其适合与前述的感测放大器搭配使用。The present invention also provides a method for judging the voltage of a bit line pair, which is suitable for use in conjunction with the aforementioned sense amplifier.
本发明提出一种感测放大器，其包括有一第一延迟链与一第二延迟链。所述的第一延迟链用以电性连接一位线，并用以接收一时钟讯号与位线上的第一电压，以依据第一电压的电压大小来延迟时钟讯号，据以产生第一延迟讯号。而所述的第二延迟链用以电性连接一互补位线，并用以接收上述时钟讯号与互补位线上的第二电压，以依据第二电压的电压大小来延迟时钟讯号，据以产生第二延迟讯号。The invention provides a sense amplifier, which includes a first delay chain and a second delay chain. The first delay chain is used to electrically connect the bit line, and is used to receive a clock signal and the first voltage on the bit line, so as to delay the clock signal according to the voltage of the first voltage, thereby generating the first delay signal. The second delay chain is used to electrically connect a complementary bit line, and is used to receive the clock signal and the second voltage on the complementary bit line, so as to delay the clock signal according to the voltage of the second voltage, thereby generating Second delayed signal.
本发明还提出一种位线对的电压判读方法，其包括有下列步骤：依据一位线上的第一电压的电压大小来延迟一时钟讯号，据以产生第一延迟讯号，并依据一互补位线上的第二电压的电压大小来延迟上述时钟讯号，据以产生一第二延迟讯号；以及依据第一延迟讯号与第二延迟讯号二者的相位关来判定上述第一电压与第二电压二者的电压大小。The present invention also proposes a method for judging the voltage of a bit line pair, which includes the following steps: delaying a clock signal according to the voltage magnitude of the first voltage on the bit line, thereby generating a first delay signal, and according to a complementary The voltage of the second voltage on the bit line is used to delay the clock signal, so as to generate a second delayed signal; The voltage of the two voltages.
本发明是采用二个延迟链来分别将位线与互补位线上的电压大小转换成相位上的延迟。因此，使用者仅需依据第一延迟讯号与第二延迟讯号二者的相位关系，就可以判定位线与互补位线上的电压大小。由于电压越大，延迟就越小，因此当第一延迟讯号的相位超前第二延迟讯号的相位时，便可判定位线上的电压大于互补位线上的电压；而当判定第二延迟讯号的相位超前第一延迟讯号的相位时，则可判定互补位线上的电压大于位线上的电压。The present invention uses two delay chains to respectively convert the voltage magnitudes of the bit line and the complementary bit line into phase delays. Therefore, the user can judge the voltages on the bit line and the complementary bit line only according to the phase relationship between the first delay signal and the second delay signal. Since the larger the voltage, the smaller the delay, so when the phase of the first delayed signal is ahead of the phase of the second delayed signal, it can be determined that the voltage on the bit line is greater than the voltage on the complementary bit line; When the phase of is ahead of the phase of the first delayed signal, it can be determined that the voltage on the complementary bit line is greater than the voltage on the bit line.
为使本发明的上述和其他目的、特征和优点能更明显易懂，下文特举较佳实施例，并结合附图详细说明如下。In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings.
附图说明Description of drawings
图1示出了依照本发明一实施例的一种感测放大器。FIG. 1 shows a sense amplifier according to an embodiment of the present invention.
图2示出了延迟链120中的反相器的其中一种电路架构。FIG. 2 shows one circuit architecture of the inverter in the delay chain 120 .
图3示出了延迟链140中的反相器的其中一种电路架构。FIG. 3 shows one circuit architecture of the inverter in the delay chain 140 .
图4示出了有时钟讯号CLK、延迟讯号DS1与延迟讯号DS2这三者的其中一种时序关系。FIG. 4 shows one of the timing relationships among the clock signal CLK, the delayed signal DS1 and the delayed signal DS2.
图5示出了延迟链120中的反相器的另一种电路架构。FIG. 5 shows another circuit architecture of the inverter in the delay chain 120 .
图6示出了延迟链140中的反相器的另一种电路架构。FIG. 6 shows another circuit architecture of the inverter in the delay chain 140 .
图7示出了延迟链120中的反相器的再一种电路架构。FIG. 7 shows another circuit architecture of the inverter in the delay chain 120 .
图8示出了延迟链140中的反相器的再一种电路架构。FIG. 8 shows another circuit architecture of the inverter in the delay chain 140 .
图9为依照本发明另一实施例的一种感测放大器。FIG. 9 is a sense amplifier according to another embodiment of the present invention.
图10示出了相位变化检测器930的其中一种实现方式。FIG. 10 shows one implementation of the phase change detector 930 .
图11为依照本发明一实施例的位线对的电压判读方法的基本步骤。FIG. 11 shows basic steps of a method for judging the voltage of a bit line pair according to an embodiment of the present invention.
附图符号说明Description of reference symbols
102：位线102: bit line
104：互补位线104: complementary bit line
110、900：感测放大器110, 900: sense amplifier
120、140、910、920：延迟链120, 140, 910, 920: delay chain
122～132、142～152、200、300、500、600、700、800：反相器122～132, 142～152, 200, 300, 500, 600, 700, 800: Inverter
202、204、302、304、502、602、702、704、802、804：P型晶体管202, 204, 302, 304, 502, 602, 702, 704, 802, 804: P-type transistors
206、208、306、308、504、506、604、606、706、806：N型晶体管206, 208, 306, 308, 504, 506, 604, 606, 706, 806: N-type transistors
930：相位变化检测器930: Phase Change Detector
932、934、936、938：D型触发器932, 934, 936, 938: D-type flip-flop
940：比较电路940: comparison circuit
942、944：多工器942, 944: multiplexer
CLK：时钟讯号CLK: clock signal
DS1、DS2：延迟讯号DS1, DS2: delayed signal
EN：读取致能讯号EN: read enable signal
IN：反相器的输入讯号IN: The input signal of the inverter
INI：初始设定讯号INI: initial setting signal
OUT：反相器的输出讯号OUT: the output signal of the inverter
SAO、SAOB：相位变化检测器的输出讯号SAO, SAOB: Output signal of phase change detector
Td1：延迟讯号DS1的延迟时间Td1: Delay time of delay signal DS1
Td2：延迟讯号DS2的延迟时间Td2: Delay time of delay signal DS2
V1：位线102上的电压V1: Voltage on bit line 102
V2：互补位线104上的电压V2: voltage on complementary bit line 104
VDD：电源电压VDD: supply voltage
SEL：选择讯号SEL: select signal
VSS：参考电位VSS: reference potential
Qn、Qbn、Qi、Qbi：D型触发器所输出的讯号Qn, Qbn, Qi, Qbi: Signals output by D-type flip-flops
D：D型触发器的数据输入端D: Data input terminal of D-type flip-flop
Q：D型触发器的数据输出端Q: The data output terminal of the D-type flip-flop
R：D型触发器的重置端R: The reset terminal of the D-type flip-flop
S1102、S1104：步骤S1102, S1104: steps
具体实施方式detailed description
图1示出了有依照本发明一实施例的一种感测放大器。此感测放大器110适用于存储器，例如是随机存取存储器(random access memory，RAM)。请参照图1，此感测放大器110用以电性连接由位线102与互补位线104所组成的一位线对。在此例中，感测放大器110包括有延迟链120与130，且每一延迟链具有偶数个反相器(如标示122～132、142～152所示)。FIG. 1 shows a sense amplifier according to an embodiment of the present invention. The sense amplifier 110 is suitable for memory, such as random access memory (random access memory, RAM). Referring to FIG. 1 , the sense amplifier 110 is used to electrically connect the bit line pair formed by the bit line 102 and the complementary bit line 104 . In this example, the sense amplifier 110 includes delay chains 120 and 130, and each delay chain has an even number of inverters (shown as 122-132, 142-152).
延迟链120用以电性连接位线102，并用以接收时钟讯号CLK与位线102上的电压V1，以依据电压V1的电压大小来延迟时钟讯号CLK，据以产生延迟讯号DS1。而延迟链140用以电性连接互补位线104，并用以接收时钟讯号CLK与互补位线104上的电压V2，以依据电压V2的电压大小来延迟时钟讯号CLK，据以产生延迟讯号DS2。此外，在此例中，每一反相器皆接收读取致能讯号EN，以供进行读取控制用。The delay chain 120 is electrically connected to the bit line 102 and used to receive the clock signal CLK and the voltage V1 on the bit line 102 to delay the clock signal CLK according to the voltage of the voltage V1 to generate the delayed signal DS1. The delay chain 140 is electrically connected to the complementary bit line 104 and used to receive the clock signal CLK and the voltage V2 on the complementary bit line 104 to delay the clock signal CLK according to the voltage of the voltage V2 to generate the delayed signal DS2. In addition, in this example, each inverter receives the read enable signal EN for read control.
图2示出了延迟链120中的反相器的其中一种电路架构。请参照图2，此反相器200包括有二个P型晶体管(分别以202与204来标示)以及二个N型晶体管(分别以206与208来标示)。P型晶体管202的其中一源/漏极用以电性连接电源电压VDD，而P型晶体管202的栅极用以接收读取致能讯号EN。P型晶体管204的其中一源/漏极电性连接P型晶体管202的另一源/漏极，P型晶体管204的栅极用以作为反相器200的输入端，以接收输入讯号IN，而P型晶体管204的另一源/漏极则用以作为反相器200的输出端，以提供输出讯号OUT。FIG. 2 shows one circuit architecture of the inverter in the delay chain 120 . Please refer to FIG. 2 , the inverter 200 includes two P-type transistors (marked as 202 and 204 respectively) and two N-type transistors (marked as 206 and 208 respectively). One source/drain of the P-type transistor 202 is electrically connected to the power supply voltage VDD, and the gate of the P-type transistor 202 is used for receiving the read enable signal EN. One source/drain of the P-type transistor 204 is electrically connected to the other source/drain of the P-type transistor 202, and the gate of the P-type transistor 204 is used as an input terminal of the inverter 200 to receive the input signal IN, The other source/drain of the P-type transistor 204 is used as the output terminal of the inverter 200 to provide the output signal OUT.
此外，N型晶体管206的其中一源/漏极电性连接P型晶体管204的另一源/漏极，而N型晶体管206的栅极电性连接P型晶体管204的栅极。N型晶体管208的其中一源/漏极电性连接N型晶体管206的另一源/漏极，N型晶体管208的栅极用以接收电压V1(即位线102上的电压)，而N型晶体管208的另一源/漏极用以电性连接参考电位VSS。由图2所示的电路架构可知，当电压V1的值越大，反相器200的输出端电位的充、放电速度就会越快。In addition, one source/drain of the N-type transistor 206 is electrically connected to the other source/drain of the P-type transistor 204 , and the gate of the N-type transistor 206 is electrically connected to the gate of the P-type transistor 204 . One source/drain of the N-type transistor 208 is electrically connected to the other source/drain of the N-type transistor 206, the gate of the N-type transistor 208 is used to receive the voltage V1 (ie, the voltage on the bit line 102), and the N-type The other source/drain of the transistor 208 is electrically connected to the reference potential VSS. It can be seen from the circuit structure shown in FIG. 2 that when the value of the voltage V1 is larger, the charging and discharging speed of the potential at the output terminal of the inverter 200 is faster.
图3示出了延迟链140中的反相器的其中一种电路架构。请参照图3，此反相器300同样包括有二个P型晶体管(分别以302与304来标示)以及二个N型晶体管(分别以306与308来标示)。由图3可知，此反相器300的电路架构与反相器200的电路架构相同，只是反相器300中的N型晶体管308的栅极用以接收电压V2(即互补位线104上的电压)。由图3所示的电路架构可知，当电压V2的值越大，反相器300的输出端电位的充、放电速度就会越快。FIG. 3 shows one circuit architecture of the inverter in the delay chain 140 . Please refer to FIG. 3 , the inverter 300 also includes two P-type transistors (marked as 302 and 304 respectively) and two N-type transistors (marked as 306 and 308 respectively). It can be seen from FIG. 3 that the circuit structure of the inverter 300 is the same as that of the inverter 200, except that the gate of the N-type transistor 308 in the inverter 300 is used to receive the voltage V2 (that is, the voltage on the complementary bit line 104 Voltage). From the circuit structure shown in FIG. 3 , it can be seen that when the value of the voltage V2 is larger, the charging and discharging speed of the potential at the output terminal of the inverter 300 is faster.
请再参照图1，由于延迟链120中的每一反相器的输出端的充、放电速度是根据电压V1的大小来决定，而延迟链140中的每一反相器的输出端的充、放电速度是根据电压V2的大小来决定，因此若是电压V1与V2的大小不同，那么延迟链120所输出的延迟讯号DS1与延迟链140所输出的延迟讯号DS2这二者的延迟程度就会不同。因此，后端电路就可以根据这二个延迟讯号的延迟程度来判定电压V1与V2谁大谁小，以图4来举例说明。Please refer to Fig. 1 again, since the charging and discharging speed of the output terminal of each inverter in the delay chain 120 is determined according to the magnitude of the voltage V1, and the charging and discharging speed of the output terminal of each inverter in the delay chain 140 The speed is determined according to the magnitude of the voltage V2. Therefore, if the magnitudes of the voltages V1 and V2 are different, the delays of the delayed signal DS1 output by the delay chain 120 and the delayed signal DS2 output by the delay chain 140 will be different. Therefore, the back-end circuit can determine which of the voltages V1 and V2 is larger and which is smaller according to the delay degrees of the two delayed signals, as illustrated in FIG. 4 .
图4示出了有时钟讯号CLK、延迟讯号DS1与延迟讯号DS2这三者的其中一种时序关系。如图所示，延迟讯号DS1是延迟了Td1的时间，而延迟讯号DS2是延迟了Td2的时间。也就是说，延迟讯号DS1的相位超前延迟讯号DS2的相位。由于每一延迟讯号的延迟程度与电压V1或V2的大小成反比，因此可判定电压V1大于电压V2。反之，若是延迟讯号DS2的相位超前延迟讯号DS1的相位，便可判定电压V2大于电压V1。FIG. 4 shows one of the timing relationships among the clock signal CLK, the delayed signal DS1 and the delayed signal DS2. As shown in the figure, the delayed signal DS1 is delayed by Td1, and the delayed signal DS2 is delayed by Td2. That is to say, the phase of the delayed signal DS1 is ahead of the phase of the delayed signal DS2. Since the delay degree of each delay signal is inversely proportional to the magnitude of the voltage V1 or V2, it can be determined that the voltage V1 is greater than the voltage V2. On the contrary, if the phase of the delayed signal DS2 is ahead of the phase of the delayed signal DS1, it can be determined that the voltage V2 is greater than the voltage V1.
由于上述每一延迟链皆由多个反相器所组成，因此即使有某个晶体管的临界电压(Vth)因工艺问题而有所不同，电压偏移问题也会随着每一延迟链所采用的反相器数目的增加而减小。因此，相对于传统的模拟式感测放大器而言，本发明的感测放大器的电压偏移问题小。此外，由于上述每一延迟链中的反相器采用低摆幅(small swing)的电路架构，因此相对于传统的数字式感测放大器而言，本发明的感测放大器的操作速度较快。Since each of the above-mentioned delay chains is composed of multiple inverters, even if the threshold voltage (Vth) of a certain transistor is different due to process issues, the voltage offset problem will vary with each delay chain. decreases with the increase of the number of inverters. Therefore, compared with the conventional analog sense amplifier, the voltage offset problem of the sense amplifier of the present invention is small. In addition, since the inverters in each of the above delay chains adopt a low swing (small swing) circuit structure, compared with the conventional digital sense amplifier, the operation speed of the sense amplifier of the present invention is faster.
以下将再举出二种低摆幅的反相器的电路架构。请参照图5，其示出了延迟链120中的反相器的另一种电路架构。请参照图5，此反相器500包括有一个P型晶体管(以502来标示)以及二个N型晶体管(分别以504与506来标示)。P型晶体管502的其中一源/漏极用以电性连接电源电压VDD，P型晶体管502的栅极用以作为反相器500的输入端，以接收输入讯号IN，而P型晶体管502的另一源/漏极用以作为反相器500的输出端，以提供输出讯号OUT。N型晶体管504的其中一源/漏极电性连接P型晶体管502的另一源/漏极，而N型晶体管504的栅极电性连接P型晶体管502的栅极。N型晶体管506的其中一源/漏极电性连接N型晶体管504的另一源/漏极，N型晶体管506的栅极用以接收电压V1(即位线102上的电压)，而N型晶体管506的另一源/漏极用以电性连接参考电位VSS。The circuit structures of two low-swing inverters will be listed below. Please refer to FIG. 5 , which shows another circuit architecture of the inverter in the delay chain 120 . Please refer to FIG. 5 , the inverter 500 includes a P-type transistor (marked by 502 ) and two N-type transistors (marked by 504 and 506 respectively). One of the source/drain of the P-type transistor 502 is used to electrically connect the power supply voltage VDD, the gate of the P-type transistor 502 is used as the input terminal of the inverter 500 to receive the input signal IN, and the P-type transistor 502 The other source/drain is used as the output terminal of the inverter 500 to provide the output signal OUT. One source/drain of the N-type transistor 504 is electrically connected to the other source/drain of the P-type transistor 502 , and the gate of the N-type transistor 504 is electrically connected to the gate of the P-type transistor 502 . One source/drain of the N-type transistor 506 is electrically connected to the other source/drain of the N-type transistor 504, the gate of the N-type transistor 506 is used to receive the voltage V1 (ie, the voltage on the bit line 102), and the N-type The other source/drain of the transistor 506 is electrically connected to the reference potential VSS.
图6示出了延迟链140中的反相器的另一种电路架构。请参照图6，此反相器600同样包括有一个P型晶体管(以602来标示)以及二个N型晶体管(分别以604与606来标示)。由图6可知，此反相器600的电路架构与反相器500的电路架构相同，只是反相器600中的N型晶体管606的栅极用以接收电压V2(即互补位线104上的电压)。FIG. 6 shows another circuit architecture of the inverter in the delay chain 140 . Please refer to FIG. 6 , the inverter 600 also includes a P-type transistor (marked by 602 ) and two N-type transistors (marked by 604 and 606 respectively). It can be seen from FIG. 6 that the circuit structure of the inverter 600 is the same as that of the inverter 500, except that the gate of the N-type transistor 606 in the inverter 600 is used to receive the voltage V2 (that is, the voltage on the complementary bit line 104 Voltage).
图7示出了延迟链120中的反相器的再一种电路架构。请参照图7，此反相器700包括有二个P型晶体管(以702与704来标示)以及一个N型晶体管(以706来标示)。P型晶体管702的其中一源/漏极用以电性连接电源电压VDD，而P型晶体管702的栅极用以接收电压V1(即位线102上的电压)。P型晶体管704的其中一源/漏极电性连接P型晶体管702的另一源/漏极，P型晶体管704的栅极作为反相器700的输入端，以接收输入讯号IN，而P型晶体管704的另一源/漏极用以作为反相器700的输出端，以提供输出讯号OUT。N型晶体管706的其中一源/漏极电性连接P型晶体管704的另一源/漏极，N型晶体管706的栅极电性连接P型晶体管704的栅极，而N型晶体管706的另一源/漏极用以电性连接参考电位VSS。FIG. 7 shows another circuit architecture of the inverter in the delay chain 120 . Please refer to FIG. 7 , the inverter 700 includes two P-type transistors (marked by 702 and 704 ) and an N-type transistor (marked by 706 ). One source/drain of the P-type transistor 702 is electrically connected to the power supply voltage VDD, and the gate of the P-type transistor 702 is used to receive the voltage V1 (ie, the voltage on the bit line 102 ). One source/drain of the P-type transistor 704 is electrically connected to the other source/drain of the P-type transistor 702, and the gate of the P-type transistor 704 serves as the input terminal of the inverter 700 to receive the input signal IN, and the P The other source/drain of the type transistor 704 is used as the output terminal of the inverter 700 to provide the output signal OUT. One source/drain of the N-type transistor 706 is electrically connected to the other source/drain of the P-type transistor 704, the gate of the N-type transistor 706 is electrically connected to the gate of the P-type transistor 704, and the gate of the N-type transistor 706 The other source/drain is electrically connected to the reference potential VSS.
图8示出了延迟链140中的反相器的再一种电路架构。请参照图8，此反相器800同样包括有二个P型晶体管(以802与804来标示)以及一个N型晶体管(以806来标示)。由图8可知，此反相器800的电路架构与反相器700的电路架构相同，只是反相器800中的P型晶体管802的栅极用以接收电压V2(即互补位线104上的电压)。FIG. 8 shows another circuit architecture of the inverter in the delay chain 140 . Please refer to FIG. 8 , the inverter 800 also includes two P-type transistors (marked by 802 and 804 ) and an N-type transistor (marked by 806 ). It can be seen from FIG. 8 that the circuit structure of the inverter 800 is the same as that of the inverter 700, except that the gate of the P-type transistor 802 in the inverter 800 is used to receive the voltage V2 (that is, the voltage on the complementary bit line 104 Voltage).
此外，为了避免延迟讯号DS1与延迟讯号DS2的相位相同而使得后端电路无法判定位线102上的电压与互补位线104上的电压究竟是谁大谁小，设计者可在感测放大器中增设一相位变化检测器来帮助辨识，如图9所示。In addition, in order to prevent the delayed signal DS1 and the delayed signal DS2 from being in the same phase, making it difficult for the back-end circuit to determine which is larger and which is smaller between the voltage on the bit line 102 and the voltage on the complementary bit line 104 , the designer can set the voltage in the sense amplifier Add a phase change detector to help identification, as shown in Figure 9.
图9为依照本发明另一实施例的一种感测放大器。请参照图9，此感测放大器900包括有延迟链910、延迟链920与相位变化检测器930。延迟链910用以依据一位线(未示出了)上的电压V1的电压大小来延迟时钟讯号CLK，并据以产生延迟讯号DS1。而延迟链920用以依据一互补位线(未示出了)上的电压V2的电压大小来延迟时钟讯号CLK，并据以产生延迟讯号DS2。至于相位变化检测器930，其具有一初始操作阶段与一感测操作阶段，其中感测操作阶段是在初始操作阶段之后。在所述的初始操作阶段中，相位变化检测器930会检测延迟讯号DS1与DS2二者的相位的先后顺序，并据以储存成第一检测结果。因此，可在此初始操作阶段中使电压V1与V2的电压大小一样，使得相位变化检测器930所储存的第一检测结果可以反应出延迟链910与920二者于充、放电速度上的差异。FIG. 9 is a sense amplifier according to another embodiment of the present invention. Referring to FIG. 9 , the sense amplifier 900 includes a delay chain 910 , a delay chain 920 and a phase change detector 930 . The delay chain 910 is used to delay the clock signal CLK according to the voltage level of the voltage V1 on the bit line (not shown), and thereby generate the delayed signal DS1 . The delay chain 920 is used to delay the clock signal CLK according to the voltage V2 on a complementary bit line (not shown), and thereby generate the delayed signal DS2. As for the phase change detector 930, it has an initial operation stage and a sensing operation stage, wherein the sensing operation stage is after the initial operation stage. In the initial operation stage, the phase change detector 930 detects the sequence of the phases of the delay signals DS1 and DS2 and stores it as the first detection result. Therefore, the voltages V1 and V2 can be made the same in this initial operation stage, so that the first detection result stored by the phase change detector 930 can reflect the difference between the charging and discharging speeds of the delay chains 910 and 920 .
在储存完第一检测结果之后，接着便可使相位变化检测器930进入感测操作阶段，并使存储器开始正常操作，以使电压V1与V2能分别反应出位线(未示出了)与互补位线(未示出了)上的电压变化。而在感测操作阶段中，相位变化检测器930会检测延迟讯号DS1与DS2的相位的先后顺序，并据以储存成第二检测结果。当第二检测结果显示出延迟讯号DS1与DS2的相位为相同时，相位变化检测器930便会利用其输出讯号SAO与SAOB来输出与第一检测结果相反的结果；而当第二检测结果显示出延迟讯号DS1与DS2的相位为不同时，相位变化检测器930便会利用其输出讯号SAO与SAOB来输出第二检测结果。以下将进一步举例来作解释。After storing the first detection result, the phase change detector 930 can then enter the sensing operation phase, and the memory can be started to operate normally, so that the voltages V1 and V2 can reflect the bit line (not shown) and the bit line respectively. The voltage change on the complementary bit line (not shown). In the sensing operation stage, the phase change detector 930 detects the sequence of the phases of the delay signals DS1 and DS2 , and stores it as a second detection result. When the second detection result shows that the phases of the delay signals DS1 and DS2 are the same, the phase change detector 930 will use its output signals SAO and SAOB to output a result opposite to the first detection result; and when the second detection result shows When the phases of the output delay signals DS1 and DS2 are different, the phase change detector 930 uses its output signals SAO and SAOB to output a second detection result. Further examples will be given below for explanation.
假设第一检测结果显示延迟讯号DS2超前延迟讯号DS1，表示在电压V1与V2相同的情况下，延迟链920的充、放电速度快于延迟链910的充、放电速度。因此，当第二检测结果显示延迟讯号DS1与DS2同相位时，表示实际上的检测结果应与第一检测结果相反，因此相位变化检测器930便会利用其输出讯号SAO与SAOB来输出与第一检测结果相反的结果，也就是利用输出讯号SAO与SAOB来输出延迟讯号DS1为超前延迟讯号DS2的结果。而当第二检测结果显示出延迟讯号DS1与DS2的相位为不同时，表示实际上的检测结果应与第二检测结果相同，因此相位变化检测器930便会便会利用其输出讯号SAO与SAOB来输出第二检测结果。Assuming that the first detection result shows that the delay signal DS2 is ahead of the delay signal DS1, it means that the charge and discharge speed of the delay chain 920 is faster than that of the delay chain 910 when the voltages V1 and V2 are the same. Therefore, when the second detection result shows that the delayed signals DS1 and DS2 have the same phase, it means that the actual detection result should be opposite to the first detection result, so the phase change detector 930 will use its output signals SAO and SAOB to output the same phase as the first detection result. A result in which the detection result is opposite, that is, the result of using the output signals SAO and SAOB to output the delayed signal DS1 to be ahead of the delayed signal DS2. And when the second detection result shows that the phases of the delayed signals DS1 and DS2 are different, it means that the actual detection result should be the same as the second detection result, so the phase change detector 930 will use its output signals SAO and SAOB to output the second detection result.
图10示出了相位变化检测器930的其中一种实现方式。请参照图10，此相位变化检测器930包括有四个D型触发器(分别以932、934、936与938来标示)、一个比较电路(以940来标示)与二个多工器(分别以942与944来标示)。每一D型触发器皆具有一数据输入端(以D来标示)、一数据输出端(以Q来标示)与一时钟输入端(以三角形来标示)。D型触发器932的数据输入端D用以接收延迟讯号DS1，而D型触发器932的时钟输入端用以接收延迟讯号DS2。D型触发器934的数据输入端D用以接收延迟讯号DS2，而D型触发器934的时钟输入端用以接收延迟讯号DS1。D型触发器936的数据输入端D用以接收D型触发器932的数据输出端Q所输出的讯号Qn，而D型触发器936的时钟输入端用以接收初始设定讯号INI。此初始设定讯号INI用以决定相位变化检测器930处于初始操作阶段或感测操作阶段。D型触发器938的数据输入端D用以接收D型触发器934的数据输出端Q所输出的讯号Qbn，而D型触发器938的时钟输入端用以接收初始设定讯号INI。FIG. 10 shows one implementation of the phase change detector 930 . Please refer to FIG. 10, the phase change detector 930 includes four D-type flip-flops (respectively marked with 932, 934, 936 and 938), a comparison circuit (marked with 940) and two multiplexers (respectively marked with 942 and 944). Each D-type flip-flop has a data input end (marked by D), a data output end (marked by Q) and a clock input end (marked by triangle). The data input terminal D of the D-type flip-flop 932 is used to receive the delayed signal DS1, and the clock input terminal of the D-type flip-flop 932 is used to receive the delayed signal DS2. The data input terminal D of the D-type flip-flop 934 is used to receive the delayed signal DS2, and the clock input terminal of the D-type flip-flop 934 is used to receive the delayed signal DS1. The data input terminal D of the D-type flip-flop 936 is used to receive the signal Qn output from the data output terminal Q of the D-type flip-flop 932 , and the clock input terminal of the D-type flip-flop 936 is used to receive the initial setting signal INI. The initial setting signal INI is used to determine whether the phase change detector 930 is in the initial operation stage or the sensing operation stage. The data input terminal D of the D-type flip-flop 938 is used to receive the signal Qbn output from the data output terminal Q of the D-type flip-flop 934 , and the clock input terminal of the D-type flip-flop 938 is used to receive the initial setting signal INI.
此外，多工器942用以接收讯号Qn与Qbi，并依据选择讯号SEL输出讯号Qn与Qbi二者其中之一。多工器944用以接收讯号Qbn与Qi，并依据选择讯号SEL输出讯号Qbn与Qi二者其中之一。至于比较电路940，其用以接收讯号Qn、Qbn、Qi与Qbi，并用以比较讯号Qn、Qbn二者的相位是否相同，据以输出上述的选择讯号SEL。当比较结果为是时，比较电路940便利用选择讯号SEL控制多工器942与944分别输出讯号Qbi与Qi，以分别作为相位变化检测器930的输出讯号SAO与SAOB，并作为与第一检测结果相反的结果来输出。而当比较结果为否时，比较电路940便利用选择讯号SEL控制多工器942与944分别输出讯号Qn与Qbn，以分别作为相位变化检测器930的输出讯号SAO与SAOB，并作为第二检测结果来输出。In addition, the multiplexer 942 is used to receive the signals Qn and Qbi, and output one of the signals Qn and Qbi according to the selection signal SEL. The multiplexer 944 is used to receive the signals Qbn and Qi, and output one of the signals Qbn and Qi according to the selection signal SEL. As for the comparing circuit 940, it is used to receive the signals Qn, Qbn, Qi and Qbi, and compare whether the phases of the signals Qn and Qbn are the same, so as to output the above-mentioned selection signal SEL. When the comparison result is yes, the comparison circuit 940 uses the selection signal SEL to control the multiplexers 942 and 944 to output signals Qbi and Qi, respectively, as the output signals SAO and SAOB of the phase change detector 930, and as the first detection signal. The opposite result is output. And when the comparison result is negative, the comparison circuit 940 uses the selection signal SEL to control the multiplexers 942 and 944 to output signals Qn and Qbn, respectively, as the output signals SAO and SAOB of the phase change detector 930, and as the second detection result to output.
藉由上述各实施方式的教示，本领域的技术人员可归纳出一种位线对的电压判读方法的基本步骤，如图11所示。请参照图11，此电压判读方法的步骤包括：依据一位线上的第一电压的电压大小来延迟一时钟讯号，据以产生第一延迟讯号，并依据一互补位线上的第二电压的电压大小来延迟上述时钟讯号，据以产生一第二延迟讯号(如步骤S1102所示)；以及依据第一延迟讯号与第二延迟讯号二者的相位关系来判定上述第一电压与第二电压二者的电压大小(如步骤S1104所示)。Based on the teachings of the above-mentioned embodiments, those skilled in the art can summarize the basic steps of a method for detecting the voltage of a bit line pair, as shown in FIG. 11 . Please refer to FIG. 11 , the steps of the voltage judgment method include: delaying a clock signal according to the voltage magnitude of the first voltage on a bit line, thereby generating a first delayed signal, and according to the second voltage on a complementary bit line The above-mentioned clock signal is delayed by the magnitude of the voltage, so as to generate a second delay signal (as shown in step S1102); The voltages of the two voltages (as shown in step S1104).
而上述的电压判读方法还可包括下列步骤：当判定第一延迟讯号的相位超前第二延迟讯号的相位时，则判定第一电压大于第二电压，而当判定第二延迟讯号的相位超前第一延迟讯号的相位时，则判定第二电压大于第一电压。The above-mentioned voltage reading method may also include the following steps: when it is determined that the phase of the first delay signal is ahead of the phase of the second delay signal, then it is determined that the first voltage is greater than the second voltage, and when it is determined that the phase of the second delay signal is ahead of the phase of the second delay signal When the phase of a delayed signal is determined, it is determined that the second voltage is greater than the first voltage.
综上所述，本发明是采用二个延迟链来分别将位线与互补位线上的电压大小转换成相位上的延迟。因此，使用者仅需依据第一延迟讯号与第二延迟讯号二者的相位关系，就可以判定位线与互补位线上的电压大小。由于电压越大，延迟就越小，因此当第一延迟讯号的相位超前第二延迟讯号的相位时，便可判定位线上的电压大于互补位线上的电压；而当判定第二延迟讯号的相位超前第一延迟讯号的相位时，则可判定互补位线上的电压大于位线上的电压。To sum up, the present invention adopts two delay chains to respectively convert the voltages on the bit line and the complementary bit line into phase delays. Therefore, the user can judge the voltages on the bit line and the complementary bit line only according to the phase relationship between the first delay signal and the second delay signal. Since the larger the voltage, the smaller the delay, so when the phase of the first delayed signal is ahead of the phase of the second delayed signal, it can be determined that the voltage on the bit line is greater than the voltage on the complementary bit line; When the phase of is ahead of the phase of the first delayed signal, it can be determined that the voltage on the complementary bit line is greater than the voltage on the bit line.
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，本领域的技术人员，在不脱离本发明的精神和范围的前提下，可作若干的更动与润饰，因此本发明的保护范围是以本发明的权利要求为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention is based on the claims of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110393475.8ACN103137174B (en) | 2011-12-01 | Voltage Determination Method of Sense Amplifier and Bit Line Pair |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110393475.8ACN103137174B (en) | 2011-12-01 | Voltage Determination Method of Sense Amplifier and Bit Line Pair |
| Publication Number | Publication Date |
|---|---|
| CN103137174A CN103137174A (en) | 2013-06-05 |
| CN103137174Btrue CN103137174B (en) | 2016-12-14 |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246271B1 (en)* | 1999-03-11 | 2001-06-12 | Kabushiki Kaisha Toshiba | Frequency multiplier capable of generating a multiple output without feedback control |
| CN1466147A (en)* | 2002-07-02 | 2004-01-07 | 旺宏电子股份有限公司 | Control clock generator for high-speed sense amplifier and control clock generation method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246271B1 (en)* | 1999-03-11 | 2001-06-12 | Kabushiki Kaisha Toshiba | Frequency multiplier capable of generating a multiple output without feedback control |
| CN1466147A (en)* | 2002-07-02 | 2004-01-07 | 旺宏电子股份有限公司 | Control clock generator for high-speed sense amplifier and control clock generation method |
| Publication | Publication Date | Title |
|---|---|---|
| US10024916B2 (en) | Sequential circuit with error detection | |
| US8742830B2 (en) | Fuse sensing circuits | |
| US8301970B2 (en) | Sequential circuit with error detection | |
| US9520877B2 (en) | Apparatus and method for detecting or repairing minimum delay errors | |
| US9418730B2 (en) | Handshaking sense amplifier | |
| KR102060073B1 (en) | Semiconductor circuit | |
| US20130188428A1 (en) | Apparatuses, circuits, and methods for reducing metastability in latches | |
| CN103544990B (en) | Static random access memory device and bit line voltage control circuit thereof | |
| KR101906371B1 (en) | Duty cycle error accumulation circuit and duty cycle correction circuit having the same | |
| US7843244B1 (en) | Low latency synchronizer circuit | |
| CN104579259B (en) | Clock signal missing detecting circuit | |
| EP1355315B1 (en) | Voltage detection circuit and method for semiconductor memory devices | |
| CN107390080B (en) | battery disconnection detection circuit | |
| TWI496156B (en) | Elastic register file circuit for dynamic change tolerance and method of operating the same | |
| CN103137174B (en) | Voltage Determination Method of Sense Amplifier and Bit Line Pair | |
| US8588020B2 (en) | Sense amplifier and method for determining values of voltages on bit-line pair | |
| CN107818801B (en) | Sense amplifier circuit and memory | |
| TWI512753B (en) | Sense amplifier and method for determining values of voltages on bit line pair | |
| US7501836B2 (en) | Apparatus and method for determining capacitance variation in an integrated circuit | |
| US8988957B2 (en) | Sense amplifier soft-fail detection circuit | |
| CN103137174A (en) | Voltage Determination Method of Sense Amplifier and Bit Line Pair | |
| CN103633963B (en) | Based on duty ratio comparison circuit and the method for single-wire-protocol | |
| US8780649B2 (en) | Buffer and control circuit for synchronous memory controller | |
| US8194491B2 (en) | Power-up circuit | |
| US20190362768A1 (en) | Memory apparatus and majority detector thereof |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |