CN103107103A - Reconfigurable operator array structure scale extension method based on wafer level packaging (WLP) form - Google Patents

Abstract

Translated fromChinese

本发明公开了一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法，所述方法即通过在晶圆级将多个可重构算子阵列结构芯片的临近IO相连，未连接IO引出，经过切割和封装，从而形成多种规模的阵列结构芯片。步骤包括：光刻，在晶圆上所有芯片的IO处形成连接通孔，在需要连接的IO之间形成通道；蒸铝，填充IO的连接通孔以及IO之间的通道，形成第一层金属层；光刻，在需要连接出的IO处形成连接通孔；蒸铝，填充IO的连接通孔，露出电性端子；在每个电性端子处生长凸点；切割，得到不同规模的可重构算子阵列结构芯片；单个独立芯片的外围覆盖一层封装材料，提供保护。本发明提供一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法，使得同一种设计可适应不同规模的应用需求。

The invention discloses a method for expanding the scale of a reconfigurable operator array structure based on WLP packaging. The IO is led out, cut and packaged to form array structure chips of various scales. The steps include: photolithography, forming connection vias at the IOs of all chips on the wafer, forming channels between the IOs that need to be connected; steaming aluminum, filling the connection vias of the IOs and the channels between the IOs, and forming the first layer Metal layer; photolithography, forming connection via holes at the IOs that need to be connected; steaming aluminum, filling the connection via holes of the IOs, exposing electrical terminals; growing bumps at each electrical terminal; cutting, to obtain different scales Reconfigurable operator array structure chip; the periphery of a single independent chip is covered with a layer of packaging material to provide protection. The invention provides a method for expanding the scale of the reconfigurable operator array structure based on the WLP packaging form, so that the same design can adapt to application requirements of different scales.

Description

Translated fromChinese

一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法A Scale Expansion Method of Reconfigurable Operator Array Structure Based on WLP Package

【技术领域】【Technical field】

本发明涉及集成电路设计和封装技术领域，具体涉及一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法。The invention relates to the technical field of integrated circuit design and packaging, in particular to a method for expanding the scale of a reconfigurable operator array structure based on WLP packaging.

【背景技术】【Background technique】

随着集成电路制造工艺进入45-22nm阶段，在单个芯片上集成晶体管数目已经达几十亿这个规模，使得实现阵列规模的结构成为可能。北京大学深圳研究生院集成微系统实验室提出的一种适用于并行计算技术的统一架构的阵列处理结构，并针对该结构申请专利“一种可重构算子的阵列结构201110083948.2”。该阵列结构含有丰富的可重构运算算子、存储算子支持处理的需求，同时大量的路径算子和布线资源支持数据传输的实现，该系统适用于可重构算子的设计能够反复编程支撑多种应用实现的需要。As the integrated circuit manufacturing process enters the 45-22nm stage, the number of integrated transistors on a single chip has reached the scale of billions, making it possible to realize an array-scale structure. An array processing structure suitable for a unified architecture of parallel computing technology was proposed by the Integrated Microsystem Laboratory of Shenzhen Graduate School of Peking University, and a patent was applied for "A reconfigurable operator array structure 201110083948.2" for this structure. The array structure contains rich reconfigurable operation operators and storage operators to support processing requirements, and a large number of path operators and wiring resources support the realization of data transmission. The system is suitable for the design of reconfigurable operators and can be programmed repeatedly Support the needs of various application implementations.

不同的应用对阵列结构的规模需求不一样，为了满足不同的需求，需要提供多个系列的不同规模的可重构算子阵列结构。本专利提出一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法，只设计一种规模的可重构算子阵列结构芯片，在晶圆级将多个该类阵列结构芯片连接后封装，从而形成任意规模的可重构算子阵列结构芯片。Different applications have different requirements for the scale of the array structure. In order to meet different requirements, it is necessary to provide multiple series of reconfigurable operator array structures of different sizes. This patent proposes a scale expansion method of reconfigurable operator array structure based on WLP packaging form. Only one scale of reconfigurable operator array structure chips is designed, and multiple such array structure chips are connected at the wafer level. After packaging, a reconfigurable operator array structure chip of any scale can be formed.

【发明内容】【Content of invention】

本发明的目的是提供一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法，使得同一种设计可适应不同规模的应用需求。The purpose of the present invention is to provide a method for expanding the scale of a reconfigurable operator array structure based on WLP packaging, so that the same design can adapt to application requirements of different scales.

为实现上述目的，本发明提供一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法。所述方法通过在晶圆级将多个可重构算子阵列结构芯片的临近IO相连，单个芯片的未连接IO作为阵列结构的IO被引出，经过切割和封装，从而形成多种规模的阵列结构芯片。步骤如下：In order to achieve the above object, the present invention provides a method for expanding the scale of a reconfigurable operator array structure based on WLP packaging. The method connects adjacent IOs of multiple reconfigurable operator array structure chips at the wafer level, unconnected IOs of a single chip are drawn out as IOs of an array structure, and are cut and packaged to form arrays of various sizes Structural chips. Proceed as follows:

步骤一：光刻，在晶圆上所有可重构算子阵列结构芯片的IO处形成连接通孔，在需要连接的IO之间形成通道，其它地方被绝缘的氧化物所覆盖；Step 1: Photolithography, forming connection via holes at the IOs of all reconfigurable operator array structure chips on the wafer, forming channels between the IOs that need to be connected, and covering other places with insulating oxides;

所述步骤一中需要连接的IO为邻近可重构算子阵列结构芯片相邻边的IO，根据需要可以将n个邻近芯片的相邻边的IO相连，n代表等于大于1的整数；The IOs that need to be connected in the step 1 are the IOs adjacent to the adjacent sides of the reconfigurable operator array structure chip, and the IOs on the adjacent sides of n adjacent chips can be connected as required, and n represents an integer greater than 1;

所述步骤一中邻近芯片的分布可以是一维线性相邻，也可是二维相邻；The distribution of adjacent chips in the step 1 can be one-dimensional linear adjacent or two-dimensional adjacent;

步骤二：蒸铝，填充IO的连接通孔以及IO之间的通道，形成第一层金属层；Step 2: Steaming aluminum, filling the connection vias of IOs and the channels between IOs to form the first metal layer;

所述步骤二中将需要引出的IO通过连接通孔引到第一层金属上，为最后引到芯片外做准备。同时在第一层金属上实现邻近芯片的相邻边的IO的连接。In the second step, the IOs that need to be led out are led to the first layer of metal through connection vias, in preparation for the final lead out of the chip. At the same time, the connection of the IOs adjacent to the adjacent edge of the chip is realized on the first layer of metal.

步骤三：光刻，在需要连接出的IO处形成连接通孔，其它地方被绝缘氧化物所覆盖；Step 3: Photolithography, forming connection via holes at the IOs that need to be connected, and other places are covered with insulating oxide;

步骤四：蒸铝，填充IO的连接通孔，露出电性端子；Step 4: Steam aluminum, fill the connection through hole of IO, and expose the electrical terminal;

步骤五：在每个电性端子处生长凸点；Step five: growing bumps at each electrical terminal;

步骤六：以凸点之间的区域为界进行切割，得到不同规模的可重构算子阵列结构芯片；Step 6: Carry out cutting with the area between the bumps as the boundary to obtain reconfigurable operator array structure chips of different scales;

步骤七：在单个独立芯片的外围覆盖一层封装材料，露出凸点。Step 7: Covering a layer of encapsulation material on the periphery of a single independent chip to expose bumps.

所述步骤七是为了给单个独立的芯片提供一层保护，使其不易被损伤。The seventh step is to provide a layer of protection for a single independent chip, so that it is not easy to be damaged.

本发明的有益效果是：本发明提供一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法，使得同一种设计可适应不同规模的应用需求。The beneficial effects of the present invention are: the present invention provides a method for expanding the scale of the reconfigurable operator array structure based on the WLP packaging form, so that the same design can adapt to application requirements of different scales.

【附图说明】【Description of drawings】

图1为一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法流程图的实施例；Fig. 1 is an embodiment of a scale expansion method flow chart of a reconfigurable operator array structure based on WLP packaging;

图2为一种装载可重构算子阵列结构芯片的晶圆示意图；Fig. 2 is a schematic diagram of a wafer loaded with a reconfigurable operator array structure chip;

图3为一种4个可重构算子阵列结构芯片搭建的更大规模阵列结构示意图；Figure 3 is a schematic diagram of a larger-scale array structure built by four reconfigurable operator array structure chips;

图4至图11为图1所示流程中封装体示意图。4 to 11 are schematic diagrams of packages in the process shown in FIG. 1 .

【具体实施方式】【Detailed ways】

本申请的特征及优点将通过实施例，结合附图进行说明。The features and advantages of the present application will be described with reference to the accompanying drawings.

本发明提出一种基于WLP封装形式的可重构算子阵列结构的规模扩展方法，所述方法通过在晶圆级将多个可重构算子阵列结构芯片的临近IO相连，单个芯片的未连接IO作为阵列结构的IO被引出，从而形成更大规模的阵列结构。该方法可以使得同一种设计可适应不同规模的应用需求。The present invention proposes a method for expanding the scale of the reconfigurable operator array structure based on the WLP packaging form. The method connects adjacent IOs of multiple reconfigurable operator array structure chips at the wafer level. Connection IOs are drawn out as IOs of the array structure, thereby forming a larger-scale array structure. This method can make the same design adaptable to application requirements of different scales.

所述方法的步骤如图1所示。The steps of the method are shown in FIG. 1 .

步骤一S101：光刻，在晶圆上所有可重构算子阵列结构芯片的IO处形成连接通孔，在需要连接的IO之间形成通道，其它地方被绝缘的氧化物所覆盖。Step 1 S101: Photolithography, forming connection via holes at the IOs of all reconfigurable operator array structure chips on the wafer, forming channels between IOs that need to be connected, and covering other places with insulating oxide.

S101中所述晶圆即图2中的201，在201上分布着很多可重构算子阵列结构芯片202，其IO分布在四周。根据应用的需要可以将n个邻近芯片的相邻边的IO相连，n代表等于大于1的整数。同时邻近芯片的分布可以是一维线性相邻，也可是二维相邻。203、204、205、206分别为2个、3个、4个、6个芯片组成更大规模的可重构算子阵列结构。The wafer mentioned in S101 is 201 in FIG. 2 , and many reconfigurableoperator array chips 202 are distributed on 201 , and their IOs are distributed around. According to the needs of the application, the IOs of the adjacent sides of n adjacent chips can be connected, and n represents an integer equal to or greater than 1. At the same time, the distribution of adjacent chips can be one-dimensional linearly adjacent, or two-dimensionally adjacent. 203, 204, 205, and 206 respectively form a larger-scale reconfigurable operator array structure with 2, 3, 4, and 6 chips.

在图三中给出了以二维相邻方式进行规模扩展的可重构算子阵列结构芯片的IO连接示意图。301为单个可重构算子阵列结构芯片，302为IO，303为相邻芯片邻近边IO相连的连接线。Figure 3 shows the schematic diagram of the IO connection of the reconfigurable operator array structure chip that scales up in a two-dimensional adjacent manner. 301 is a single reconfigurable operator array chip, 302 is an IO, and 303 is a connection line connecting the adjacent side IOs of adjacent chips.

步骤二S102：蒸铝，填充IO的连接通孔以及IO之间的通道，形成第一层金属层。将S101中形成的连接通孔和通道填充铝，形成导电的第一层金属层，没有被通道相连的IO为最后引出芯片外做准备。Step 2 S102: steaming aluminum, filling the connection via holes of the IOs and the channels between the IOs to form the first metal layer. The connection vias and channels formed in S101 are filled with aluminum to form the first conductive metal layer, and the IOs not connected by the channels are prepared for the final lead out of the chip.

步骤三S103：光刻，在需要连接出的IO处形成连接通孔，其它地方被绝缘氧化物所覆盖。Step 3 S103: photolithography, forming connection via holes at the IOs that need to be connected, and covering other places with insulating oxide.

步骤四S104：蒸铝，填充IO的连接通孔，露出电性端子。所谓电性端子即可以与外界进行相连的导电引脚。Step 4 S104: Aluminum steaming, filling the IO connection through holes, exposing electrical terminals. The so-called electrical terminals are conductive pins that can be connected with the outside world.

步骤五S105：在每个电性端子处生长凸点。Step 5 S105: growing bumps at each electrical terminal.

所述S105中的凸点为封装完成后与其它元件连接的单元。The bumps in S105 are units that are connected to other components after the packaging is completed.

步骤六S106：以凸点之间的区域为界进行切割，得到不同规模的可重构算子阵列结构芯片。Step 6 S106: Carry out cutting with the area between the bumps as the boundary to obtain reconfigurable operator array structure chips of different scales.

步骤七S107：步骤七：在单个独立芯片的外围覆盖一层封装材料，露出凸点。Step 7 S107: Step 7: Cover a layer of encapsulation material on the periphery of a single independent chip to expose bumps.

所述S107是为了给单个独立的芯片提供一层保护，使其不易被损伤。The S107 is to provide a layer of protection for a single independent chip, so that it is not easy to be damaged.

在图4至图11中，针对图1中每步流程进行了图示说明。In Fig. 4 to Fig. 11, each step of the process in Fig. 1 is illustrated.

图4中401为晶圆，402为晶圆上的IO。401 in FIG. 4 is a wafer, and 402 is an IO on the wafer.

图5即对应S101，在402处形成连接通孔501，在需要连接的402之间形成通道502，其它地方被绝缘的氧化物503所覆盖。FIG. 5 corresponds to S101 , a connection via 501 is formed at 402 , achannel 502 is formed between 402 to be connected, and other places are covered byinsulating oxide 503 .

图6即对应S102，用铝601填充501和502，形成第一层金属层。FIG. 6 corresponds to S102, filling 501 and 502 withaluminum 601 to form the first metal layer.

图7即对应S103，在需要引出的IO处形成连接通孔701，其它地方被绝缘氧化物702覆盖。FIG. 7 corresponds to S103 , formingconnection vias 701 at the IOs that need to be led out, and covering other places withinsulating oxide 702 .

图8即对应S104，用铝801填充701，802为可导电的电性端子。FIG. 8 corresponds to S104, and aluminum 801 is used to fill 701, and 802 is a conductive electrical terminal.

图9即对应S105，在802上生长凸点901。FIG. 9 corresponds to S105 , growingbumps 901 on 802 .

图10即对应S106，将晶圆进行切割，得到不同规模的可重构算子阵列结构芯片。Figure 10 corresponds to S106, cutting the wafer to obtain reconfigurable operator array chips of different sizes.

图11即对应S107，在单个独立的可重构算子阵列结构芯片外围形成一层封装材料1101，为该芯片提供保护。Figure 11 corresponds to S107, forming a layer ofencapsulation material 1101 on the periphery of a single independent reconfigurable operator array structure chip to provide protection for the chip.

以上内容是结合实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。The above content is a further detailed description of the present invention in conjunction with the embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. Expansion method based on the reconfigurable operator array structure of WLP packing forms, described method is namely by being connected at the IO that closes on of wafer scale with a plurality of reconfigurable operator array structure chips, do not connect IO and draw, through cutting and encapsulation, thereby form more massive array structure chip.It is characterized in that: described method step one is photoetching, and IO place's formation connecting through hole of all chips, form passage between the IO that needs connect on wafer;

2. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: needing the IO that connects in described method step one is the IO on contiguous reconfigurable operator array structure chip by chip limit, the IO of the adjacent edge of n adjacent chips can be connected as required, the n representative equals the integer greater than 1;

3. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: in described method step one, the distribution of adjacent chips can be that one-dimensional linear is adjacent, also two dimension is adjacent;

4. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step two is evaporation of aluminum, the connecting through hole of the I that obtains in filling step one and the passage between IO form the first layer metal layer;

5. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step three is photoetching, connect the IO place's formation connecting through hole that at needs, other place is insulated oxide and covers;

6. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step four is evaporation of aluminum, fills the connecting through hole of IO, exposes electric terminal;

7. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1 is characterized in that: described method step five is at each electric terminal place's growth salient point;

8. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step six obtains the reconfigurable operator array structure chip of different scales for to cut take the zone between salient point as the boundary;

9. the Expansion method of a kind of reconfigurable operator array structure based on the WLP packing forms as claimed in claim 1, it is characterized in that: described method step seven exposes salient point for the periphery in single individual chips covers one deck encapsulating material.

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