技术领域technical field
本发明涉及一种记忆体结构及其制造方法，特别是涉及一种具有垂直通道的记忆体结构及其制造方法。The invention relates to a memory structure and a manufacturing method thereof, in particular to a memory structure with vertical channels and a manufacturing method thereof.
背景技术Background technique
记忆体是设计用来储存资讯或资料的半导体元件。当电脑微处理器的功能变得越来越强，软件所进行的程序与运算也随之增加。因此，记忆体的容量需求也就越来越高。在各式的记忆体产品中，非挥发性记忆体，例如可电抹除可程序化只读记忆体(Electrically Erasable ProgrammableRead Only Memory，EEPROM)允许多次的资料程序化、读取及抹除操作，且其中储存的资料即使在记忆体被断电后仍可以保存。基于上述优点，可电抹除可程序化只读记忆体已成为个人电脑和电子设备所广泛采用的一种记忆体。Memory is a semiconductor device designed to store information or data. As the functions of computer microprocessors become more and more powerful, the programs and calculations performed by the software also increase. Therefore, the memory capacity requirements are getting higher and higher. Among various memory products, non-volatile memory, such as Electrically Erasable Programmable Read Only Memory (EEPROM) allows multiple data programming, reading and erasing operations , and the data stored in it can still be saved even after the memory is powered off. Based on the above advantages, EEPROM has become a memory widely used in personal computers and electronic devices.
典型的可电抹除且可程序化只读记忆体是以掺杂的多晶硅制作浮置栅极(floating gate)与控制栅极(control gate)。当记忆体进行程序化(program)时，注入浮置栅极的电子会均匀分布于整个多晶硅浮置栅极之中。然而，当多晶硅浮置栅极下方的穿隧氧化层有缺陷存在时，就容易造成元件的漏电流，影响元件的可靠度。A typical EEPROM uses doped polysilicon to make a floating gate and a control gate. When the memory is programmed, the electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate. However, when there are defects in the tunnel oxide layer under the polysilicon floating gate, it is easy to cause leakage current of the element and affect the reliability of the element.
因此，为了解决可电抹除可程序化只读记忆体漏电流的问题，目前现有习知的一种方法是采用含有非导体的电荷捕捉层的栅极结构来取代多晶硅浮置栅极。以电荷捕捉层取代多晶硅浮置栅极的另一项优点是，在元件程序化时，仅会将电子局部性地储存在接近源极或漏极上方的电荷捕捉层中。因此，在进行程序化时，可以分别对堆叠式栅极一端的源极区与控制栅极施加电压，而在接近于源极区的电荷捕捉层中产生高斯分布的电子，并且也可以分别对堆叠式栅极一端的漏极区与控制栅极施加电压，而在接近于漏极区的电荷捕捉层中产生高斯分布的电子。故而，藉由改变控制栅极与其两侧的源极区与漏极区所施加的电压，可以在单一的电荷捕捉层之中存在两群具有高斯分布的电子、一群具有高斯分布的电子或是不存在电子。因此，此种以电荷捕捉层取代浮置栅极的快闪记忆体，可以在单一的记忆胞之中写入四种状态，是一种单一记忆胞二位元(2bits/cell)储存的快闪记忆体。Therefore, in order to solve the problem of EEPROM leakage current, a conventional method is to replace the polysilicon floating gate with a gate structure including a non-conductive charge trapping layer. Another advantage of replacing the polysilicon floating gate with a charge trapping layer is that when the device is programmed, electrons are only stored locally in the charge trapping layer close to the top of the source or drain. Therefore, when programming, voltages can be applied to the source region and the control gate at one end of the stacked gate respectively, and electrons with a Gaussian distribution can be generated in the charge trapping layer close to the source region, and can also be applied to the A voltage is applied to the drain region at one end of the stacked gate and the control gate to generate Gaussian distribution of electrons in the charge trapping layer close to the drain region. Therefore, by changing the voltage applied to the control gate and the source region and drain region on both sides, two groups of electrons with Gaussian distribution, a group of electrons with Gaussian distribution or There are no electrons. Therefore, this kind of flash memory, which replaces the floating gate with a charge trapping layer, can write four states in a single memory cell, which is a flash memory stored in two bits (2bits/cell) in a single memory cell. flash memory.
然而，随着半导体元件积集度(degree of integration)的增加，非挥发性记忆体的尺寸也不断地微缩。由于通道长度(channel length)的微缩，会使得源极区与漏极区之间容易产生电性击穿漏电流(punch throughleakage current)，而降低记忆体元件的效能。此外，由于源极区与漏极区的微缩，源极区与漏极区阻挡不了由程序化选定的记忆胞时所产生的二次热电子(secondary hot electron)，而造成二次热电子注入到相邻的记忆胞中，所以会产生程序化干扰(program disturbance)的问题，从而降低记忆体元件的可靠度。However, as the degree of integration of semiconductor devices increases, the size of the non-volatile memory is also continuously shrinking. Due to the miniaturization of the channel length, an electrical breakdown leakage current (punch through leakage current) is likely to occur between the source region and the drain region, thereby reducing the performance of the memory device. In addition, due to the miniaturization of the source region and the drain region, the source region and the drain region cannot block the secondary hot electrons (secondary hot electrons) generated when programming the selected memory cells, resulting in secondary hot electrons Injected into adjacent memory cells, so there will be a problem of program disturbance, thereby reducing the reliability of memory components.
由此可见，上述现有的记忆体结构及其制造方法在产品结构、制造方法与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决上述存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品及方法又没有适切的结构及方法能够解决上述问题，此显然是相关业者急欲解决的问题。因此如何能创设一种新的记忆体结构及其制造方法，实属当前重要研发课题之一，亦成为当前业界极需改进的目标。It can be seen that the above-mentioned existing memory structure and its manufacturing method obviously still have inconveniences and defects in product structure, manufacturing method and use, and need to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new memory structure and its manufacturing method is one of the current important research and development topics, and it has also become a goal that the industry needs to improve.
发明内容Contents of the invention
本发明的的目的在于，克服现有的记忆体结构存在的缺陷，而提供一种新的记忆体结构，所要解决的技术问题是使其可以抑制电性击穿漏电流的产生，非常适于实用。The purpose of the present invention is to overcome the defects existing in the existing memory structure and provide a new memory structure. The technical problem to be solved is to make it possible to suppress the generation of electrical breakdown leakage current, which is very suitable for practical.
本发明的另一目的在于，克服现有的记忆体结构的制造方法存在的缺陷，而提供一种新的记忆体结构的制造方法，所要解决的技术问题是使其所形成的记忆体结构可以防止由二次热电子所造成的程序化干扰，从而更加适于实用。Another object of the present invention is to overcome the defects of the existing memory structure manufacturing method and provide a new memory structure manufacturing method. The technical problem to be solved is to make the formed memory structure Prevent programming interference caused by secondary thermal electrons, and thus be more suitable for practical use.
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种记忆体结构，包括记忆胞，且记忆胞包括第一介电层、栅极、半导体层、第一掺杂区、第二掺杂区及电荷储存层。第一介电层设置于基底上。栅极包括基部及突出部。基部设置于第一介电层上。突出部设置于基部上，且暴露出部分基部。半导体层共形地设置于栅极上，且包括顶部、底部及侧部。顶部设置于突出部上方。底部设置于由突出部所暴露的基部上方。侧部位于突出部的侧壁，且连接顶部与底部。第一掺杂区及第二掺杂区分别设置于顶部中与底部中，而侧部作为通道区。电荷储存层设置于栅极与半导体层之间。The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A memory structure according to the present invention includes a memory cell, and the memory cell includes a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer. The first dielectric layer is disposed on the base. The gate includes a base and a protrusion. The base is disposed on the first dielectric layer. The protrusion is disposed on the base and exposes part of the base. The semiconductor layer is conformally disposed on the gate and includes a top, a bottom and a side. The top is disposed above the protrusion. The base is disposed over the base exposed by the protrusion. The side part is located on the side wall of the protruding part and connects the top and the bottom. The first doped region and the second doped region are respectively arranged in the top and the bottom, and the side is used as a channel region. The charge storage layer is disposed between the gate and the semiconductor layer.
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.
前述的记忆体结构，当记忆体结构包括多个记忆胞时，在同一条字元线上相邻的栅极藉由基部相互连接。In the aforementioned memory structure, when the memory structure includes a plurality of memory cells, adjacent gates on the same word line are connected to each other through the base.
前述的记忆体结构，当记忆体结构包括多个记忆胞时，位于相邻两个突出部之间的相邻两个侧部彼此隔离设置。In the aforementioned memory structure, when the memory structure includes a plurality of memory cells, two adjacent side portions located between two adjacent protruding portions are isolated from each other.
前述的记忆体结构，还包括多个接触窗，分别连接至第一掺杂区及第二掺杂区。The aforementioned memory structure further includes a plurality of contact windows respectively connected to the first doped region and the second doped region.
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种记忆体结构的制造方法，包括下列步骤。首先，在基底上形成第一介电层。接着，在第一介电层上形成字元线，且字元线包括基部及多个突出部。基部设置于第一介电层上。突出部设置于基部上，且暴露出部分基部。然后，在字元线上共形地形成电荷储存层。接下来，在电荷储存层上共形地形成半导体层，且半导体层包括多个顶部、多个底部及多个侧部。顶部分别设置于突出部上方。底部分别设置于由突出部所暴露的基部上方。侧部分别位于突出部的侧壁，且连接顶部与底部，其中位于相邻两个突出部之间的相邻两个侧部彼此隔离设置。之后，在各个顶部中形成第一掺杂区，且在各个底部中形成第二掺杂区，而各个侧部作为通道区。The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A method for manufacturing a memory structure according to the present invention includes the following steps. First, a first dielectric layer is formed on a substrate. Then, a word line is formed on the first dielectric layer, and the word line includes a base and a plurality of protrusions. The base is disposed on the first dielectric layer. The protrusion is disposed on the base and exposes part of the base. A charge storage layer is then conformally formed on the wordlines. Next, a semiconductor layer is conformally formed on the charge storage layer, and the semiconductor layer includes a plurality of tops, a plurality of bottoms and a plurality of sides. The tops are respectively arranged above the protruding parts. The bottoms are respectively disposed above the bases exposed by the protrusions. The side parts are respectively located on the side walls of the protruding part and connect the top and the bottom, wherein two adjacent side parts located between two adjacent protruding parts are isolated from each other. Afterwards, a first doped region is formed in each top and a second doped region is formed in each bottom, and each side serves as a channel region.
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.
前述的记忆体结构的制造方法，其中所述的字元线的形成方法包括下列步骤。首先，在第一介电层上形成字元线材料层。接着，移除部分字元线材料层。In the aforementioned manufacturing method of the memory structure, the method for forming the word line includes the following steps. First, a word line material layer is formed on the first dielectric layer. Next, part of the word line material layer is removed.
前述的记忆体结构的制造方法，其中所述的半导体层的形成方法例如是先藉由非晶硅工艺(amorphous silicon process)形成非晶硅层，再对非晶硅层进行固相结晶(solid phase crystalization，SPC)工艺而形成。The manufacturing method of the aforementioned memory structure, wherein the method for forming the semiconductor layer is, for example, to form an amorphous silicon layer by an amorphous silicon process (amorphous silicon process), and then carry out solid phase crystallization (solid phase crystallization) to the amorphous silicon layer phase crystallization, SPC) process and formed.
前述的记忆体结构的制造方法，其中所述的半导体层的形成方法例如是化学气相沉积法。In the aforementioned manufacturing method of the memory structure, the method for forming the semiconductor layer is, for example, chemical vapor deposition.
前述的记忆体结构的制造方法，其中所述的各突出部与基部形成栅极。In the aforementioned manufacturing method of the memory structure, each protrusion and the base form a gate.
前述的记忆体结构的制造方法，还包括形成多个接触窗，分别连接至第一掺杂区及第二掺杂区。The aforementioned manufacturing method of the memory structure further includes forming a plurality of contact windows respectively connected to the first doped region and the second doped region.
本发明与现有技术相比具有明显的优点和有益效果。借由上述技术方案，本发明记忆体结构及其制造方法至少具有下列优点及有益效果：Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the memory structure and its manufacturing method of the present invention have at least the following advantages and beneficial effects:
在本发明所提出的记忆体结构中，由于通道区为垂直通道区，所以可以具有较长的通道长度，因而能够有效地抑制电性击穿的现象产生，进而可以避免产生电性击穿漏电流。In the memory structure proposed by the present invention, since the channel area is a vertical channel area, it can have a longer channel length, thereby effectively suppressing the occurrence of electrical breakdown, thereby avoiding the occurrence of electrical breakdown leakage. current.
此外，在本发明所提出的记忆体结构的制造方法中，由于位于相邻两个突出部之间的相邻两个侧部彼此隔离设置，因而能够防止由程序化选定的记忆胞时所产生的二次热电子注入到相邻的记忆胞中，因此可以防止由二次热电子所造成的程序化干扰。In addition, in the manufacturing method of the memory structure proposed by the present invention, since the two adjacent side portions between the adjacent two protruding portions are isolated from each other, it is possible to prevent the selected memory cells from being programmed. The generated secondary hot electrons are injected into adjacent memory cells, thereby preventing programming interference caused by the secondary hot electrons.
综上所述，本发明是有关于一种记忆体结构及其制造方法。该记忆体结构，包括记忆胞，且记忆胞包括第一介电层、栅极、半导体层、第一掺杂区、第二掺杂区及电荷储存层。第一介电层设置于基底上。栅极包括基部及突出部。基部设置于第一介电层上。突出部设置于基部上，且暴露出部分基部。半导体层共形地设置于栅极上，且包括顶部、底部及侧部。顶部设置于突出部上方。底部设置于由突出部所暴露的基部上方。侧部位于突出部的侧壁，且连接顶部与底部。第一掺杂区及第二掺杂区分别设置于顶部中与底部中，而侧部作为通道区。电荷储存层设置于栅极与半导体层之间。本发明在技术上有显著的进步，并具有明显的积极效果，诚为一新颖、进步、实用的新设计。To sum up, the present invention relates to a memory structure and a manufacturing method thereof. The memory structure includes a memory cell, and the memory cell includes a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer. The first dielectric layer is disposed on the base. The gate includes a base and a protrusion. The base is disposed on the first dielectric layer. The protrusion is disposed on the base and exposes part of the base. The semiconductor layer is conformally disposed on the gate and includes a top, a bottom and a side. The top is disposed above the protrusion. The base is disposed over the base exposed by the protrusion. The side part is located on the side wall of the protruding part and connects the top and the bottom. The first doped region and the second doped region are respectively arranged in the top and the bottom, and the side is used as a channel region. The charge storage layer is disposed between the gate and the semiconductor layer. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design.
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.
附图说明Description of drawings
图1A至图1E是本发明的一实施例的记忆体结构的制造流程的剖面图。1A to 1E are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the present invention.
100：基底 102、114、118：介电层100: Substrate 102, 114, 118: Dielectric layer
104：字元线材料层 106：图案化光阻层104: word line material layer 106: patterned photoresist layer
108：字元线 110：基部108: character line 110: base
112：突出部 116：电荷捕捉层112: protrusion 116: charge trapping layer
120：电荷储存层 122：半导体层120: charge storage layer 122: semiconductor layer
124：顶部 126：底部124: Top 126: Bottom
128：侧部 130：凹陷128: Side 130: Depression
132、134：掺杂区 136：通道区132, 134: doped area 136: channel area
138：记忆胞 140：栅极138: Memory cell 140: Gate
142：介电层 144：接触窗142: Dielectric layer 144: Contact window
具体实施方式Detailed ways
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的记忆体结构及其制造方法其具体实施方式、结构、方法、步骤、特征及其功效，详细说明如后。In order to further explain the technical means and effects that the present invention adopts to achieve the intended invention purpose, the specific implementation, structure and method of the memory structure and its manufacturing method according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , steps, features and effects thereof are described in detail below.
有关本发明的前述及其他技术内容、特点及功效，在以下配合参考图式的较佳实施例的详细说明中将可清楚呈现。通过具体实施方式的说明，应当可对本发明为达成预定目的所采取的技术手段及功效获得一更加深入且具体的了解，然而所附图式仅是提供参考与说明之用，并非用来对本发明加以限制。The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation, it should be possible to obtain a deeper and more specific understanding of the technical means and effects of the present invention to achieve the intended purpose, but the attached drawings are only for reference and description, not for the purpose of the present invention. be restricted.
图1A至图1E是本发明的一实施例的记忆体结构的制造流程的剖面图。1A to 1E are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the present invention.
首先，请参阅图1A所示，在基底100上形成介电层102。介电层102可作为缓冲介电层使用，以隔离基底100与后续形成于基底100上的字元线。介电层102的材料例如是氧化硅。介电层102的形成方法例如是化学气相沉积法。First, as shown in FIG. 1A , a dielectric layer 102 is formed on a substrate 100 . The dielectric layer 102 can be used as a buffer dielectric layer to isolate the substrate 100 from word lines subsequently formed on the substrate 100 . The material of the dielectric layer 102 is, for example, silicon oxide. The method for forming the dielectric layer 102 is, for example, chemical vapor deposition.
接着，在介电层102上形成字元线材料层104。字元线材料层104的材料例如是导体材料，如掺杂多晶硅。字元线材料层104的形成方法例如是化学气相沉积法。Next, a word line material layer 104 is formed on the dielectric layer 102 . The material of the word line material layer 104 is, for example, a conductive material such as doped polysilicon. The word line material layer 104 is formed by chemical vapor deposition, for example.
然后，在字元线材料层104上形成图案化光阻层106。图案化光阻层106的形成方法例如是藉由进行微影工艺而形成。Then, a patterned photoresist layer 106 is formed on the word line material layer 104 . The method for forming the patterned photoresist layer 106 is, for example, by performing a lithography process.
接下来，请参阅图1B所示，以图案化光阻层106作为罩幕，移除部分字元线材料层104，以在介电层102上形成字元线108。字元线108包括基部110及突出部112。基部110设置于介电层102上。突出部112设置于基部110上，且暴露出部分基部110。部分字元线材料层104的移除方法例如是干式蚀刻法。此外，虽然字元线108是藉由上述方法所形成，但本发明并不以此为限。Next, as shown in FIG. 1B , using the patterned photoresist layer 106 as a mask, part of the word line material layer 104 is removed to form word lines 108 on the dielectric layer 102 . The wordline 108 includes a base 110 and a protrusion 112 . The base 110 is disposed on the dielectric layer 102 . The protrusion 112 is disposed on the base 110 and exposes a part of the base 110 . A method for removing part of the word line material layer 104 is, for example, a dry etching method. In addition, although the word lines 108 are formed by the above method, the present invention is not limited thereto.
之后，移除图案化光阻层106。图案化光阻层106的移除方法例如是干式去光阻法。Afterwards, the patterned photoresist layer 106 is removed. The removal method of the patterned photoresist layer 106 is, for example, a dry stripping method.
再者，请参阅图1C所示，在字元线108上形成介电层114。介电层114的材料例如是氧化硅。介电层114的形成方法例如是化学气相沉积法。Furthermore, as shown in FIG. 1C , a dielectric layer 114 is formed on the word line 108 . The material of the dielectric layer 114 is, for example, silicon oxide. The dielectric layer 114 is formed by, for example, chemical vapor deposition.
然后，在介电层114上形成电荷捕捉层116。电荷捕捉层116的材料例如是高介电常数材料或纳米晶粒材料。其中，高介电常数材料例如是氮化硅，而纳米晶粒材料例如是硅、锗或其他金属的纳米晶粒。电荷捕捉层116的形成方法例如是化学气相沉积法。Then, a charge trapping layer 116 is formed on the dielectric layer 114 . The material of the charge trapping layer 116 is, for example, a high dielectric constant material or a nano-grain material. Wherein, the high dielectric constant material is, for example, silicon nitride, and the nano-grain material is, for example, nano-grains of silicon, germanium or other metals. The method of forming the charge trapping layer 116 is, for example, chemical vapor deposition.
然后，在电荷捕捉层116上形成介电层118。介电层118的材料例如是氧化硅。介电层118的形成方法例如是化学气相沉积法。Then, a dielectric layer 118 is formed on the charge trapping layer 116 . The material of the dielectric layer 118 is, for example, silicon oxide. The dielectric layer 118 is formed by, for example, chemical vapor deposition.
藉此，可在字元线108上共形地形成电荷储存层120，其中电荷储存层120包括介电层114、电荷捕捉层116及介电层118。此外，虽然电荷储存层120是藉由上述方法所形成，但本发明并不以此为限。Accordingly, a charge storage layer 120 can be conformally formed on the word line 108 , wherein the charge storage layer 120 includes the dielectric layer 114 , the charge trapping layer 116 and the dielectric layer 118 . In addition, although the charge storage layer 120 is formed by the above method, the present invention is not limited thereto.
接着，请参阅图1D所示，在电荷储存层120上共形地形成半导体层122，且半导体层122包括顶部124、底部126及侧部128。顶部124分别设置于突出部112上方。底部126分别设置于由突出部112所暴露的基部110上方。侧部128分别位于突出部112的侧壁，且连接顶部124与底部126。其中，由于电荷储存层120与半导体层122是依序且共形地形成于字元线108上方且字元线108具有突出部112，因此半导体层122在位于相邻两个突出部112之间的相邻两个侧部128之间会具有凹陷130，而使得位于相邻两个突出部112之间的相邻两个侧部128彼此隔离设置。Next, as shown in FIG. 1D , a semiconductor layer 122 is conformally formed on the charge storage layer 120 , and the semiconductor layer 122 includes a top 124 , a bottom 126 and a side 128 . The tops 124 are respectively disposed above the protrusions 112 . The bottoms 126 are respectively disposed above the bases 110 exposed by the protrusions 112 . The side portions 128 are respectively located on sidewalls of the protruding portion 112 and connect the top portion 124 and the bottom portion 126 . Wherein, since the charge storage layer 120 and the semiconductor layer 122 are sequentially and conformally formed above the word line 108 and the word line 108 has the protruding portion 112, the semiconductor layer 122 is located between two adjacent protruding portions 112 There is a recess 130 between two adjacent side portions 128 of the two adjacent side portions 128 , so that two adjacent side portions 128 located between two adjacent protruding portions 112 are isolated from each other.
此外，半导体层122的材料例如是多晶硅。半导体层122的形成方法例如是先藉由非晶硅工艺形成非晶硅层，再对非晶硅层进行固相结晶工艺而形成。在其他实施例中，半导体层122的形成方法也可藉由化学气相沉积法所形成。In addition, the material of the semiconductor layer 122 is, for example, polysilicon. The method for forming the semiconductor layer 122 is, for example, to first form an amorphous silicon layer by an amorphous silicon process, and then perform a solid phase crystallization process on the amorphous silicon layer. In other embodiments, the formation method of the semiconductor layer 122 may also be formed by chemical vapor deposition.
接下来，在顶部124中形成掺杂区132，且在底部126中形成掺杂区134，而侧部128作为通道区136。掺杂区132与掺杂区134的形成方法例如是离子植入法，如垂直式离子植入法。一般来说，以离子植入法所形成的掺杂区134会形成在由凹陷130所暴露的底部126中。然而，更可藉由额外进行热工艺或藉由后续工艺中的热工艺使得掺杂区134进一步地扩散到侧部128下方的底部126中。Next, doped region 132 is formed in top 124 and doped region 134 is formed in bottom 126 , while side 128 serves as channel region 136 . The method for forming the doped region 132 and the doped region 134 is, for example, an ion implantation method, such as a vertical ion implantation method. Generally, the doped region 134 formed by ion implantation is formed in the bottom 126 exposed by the recess 130 . However, the doped region 134 can be further diffused into the bottom 126 below the side portion 128 by additionally performing a thermal process or by a thermal process in a subsequent process.
再者，请参阅图1E所示，在半导体层122上形成介电层142。介电层142的材料例如是氧化硅。介电层142的形成方法例如是化学气相沉积法。Furthermore, as shown in FIG. 1E , a dielectric layer 142 is formed on the semiconductor layer 122 . The material of the dielectric layer 142 is, for example, silicon oxide. The forming method of the dielectric layer 142 is, for example, chemical vapor deposition.
随后，在介电层142中形成接触窗144，且接触窗144分别连接至掺杂区132及掺杂区134。接触窗144的材料例如是钨等导体材料。接触窗144的形成方法例如是先在介电层142中形成多个开口，再形成填满开口的导体材料层，接着移除开口以外的导体材料层而形成。Subsequently, contact windows 144 are formed in the dielectric layer 142 , and the contact windows 144 are respectively connected to the doped region 132 and the doped region 134 . The material of the contact window 144 is, for example, a conductive material such as tungsten. The contact window 144 is formed by, for example, firstly forming a plurality of openings in the dielectric layer 142 , then forming a conductive material layer filling the openings, and then removing the conductive material layer outside the openings.
基于上述实施例可知，由侧部128所形成的通道区136为垂直通道区，所以可将通道区136设计成具有较长的通道长度，而能有效地抑制电性击穿的现象产生，进而可避免产生电性击穿漏电流。Based on the above-mentioned embodiment, it can be seen that the channel region 136 formed by the side portion 128 is a vertical channel region, so the channel region 136 can be designed to have a longer channel length, which can effectively suppress the phenomenon of electrical breakdown, and then Can avoid electric breakdown leakage current.
此外，由于位于相邻两个突出部112之间的相邻两个侧部128彼此隔离设置，而能防止由程序化选定的记忆胞时所产生的二次热电子注入到相邻的记忆胞中，因此可防止由二次热电子所造成的程序化干扰，进而提升记忆体元件的可靠度。In addition, since the two adjacent side portions 128 between the adjacent two protruding portions 112 are isolated from each other, it is possible to prevent the secondary thermal electrons generated when programming the selected memory cell from being injected into the adjacent memory cells. In the cell, the programming interference caused by the secondary hot electrons can be prevented, thereby improving the reliability of the memory device.
以下，藉由图1E说明本发明的一实施例的记忆体结构。Hereinafter, the memory structure of an embodiment of the present invention will be described with reference to FIG. 1E .
记忆体结构包括记忆胞138，且各个记忆胞138包括介电层102、栅极140、半导体层122、掺杂区132、掺杂区134及电荷储存层120。介电层102设置于基底100上。栅极140为字元线108的一部分，且包括基部110及突出部112。基部110设置于介电层102上。此外，在同一条字元线108上相邻的栅极140藉由基部110相互连接。突出部112设置于基部110上，且暴露出部分基部110。半导体层122共形地设置于栅极140上，且包括顶部124、底部126及侧部128。顶部124设置于突出部112上方。底部126设置于由突出部112所暴露的基部110上方。侧部128位于突出部112的侧壁，且连接顶部124与底部126。掺杂区132及掺杂区134分别设置于顶部124中与底部126中，掺杂区132及掺杂区134分别可作为源极区与漏极区(位元线)，而侧部128作为通道区136。电荷储存层120设置于栅极140与半导体层122之间。电荷储存层120包括介电层114、介电层118及电荷捕捉层116。介电层114设置于栅极140上。介电层118设置于介电层114上。电荷捕捉层116设置于介电层114与介电层118之间。当记忆体结构包括多个记忆胞138时，位于相邻两个突出部112之间的相邻两个侧部128彼此隔离设置。记忆体结构更可选择性地包括介电层142及接触窗144中的至少一者。介电层142设置于半导体层122上。接触窗144设置于介电层142中，且分别连接至掺杂区132及掺杂区134。此外，记忆体结构中的各构件的材料、制造方法及功效已在上述实施例中进行详尽地说明，故在此不再赘述。The memory structure includes memory cells 138 , and each memory cell 138 includes a dielectric layer 102 , a gate 140 , a semiconductor layer 122 , a doped region 132 , a doped region 134 and a charge storage layer 120 . The dielectric layer 102 is disposed on the substrate 100 . Gate 140 is part of wordline 108 and includes base 110 and protrusion 112 . The base 110 is disposed on the dielectric layer 102 . In addition, adjacent gates 140 on the same word line 108 are connected to each other through the base portion 110 . The protrusion 112 is disposed on the base 110 and exposes a part of the base 110 . The semiconductor layer 122 is conformally disposed on the gate 140 and includes a top 124 , a bottom 126 and a side 128 . The top 124 is disposed above the protrusion 112 . The bottom 126 is disposed above the base 110 exposed by the protrusion 112 . The side portion 128 is located on the sidewall of the protruding portion 112 and connects the top 124 and the bottom 126 . The doped region 132 and the doped region 134 are respectively disposed in the top 124 and the bottom 126. The doped region 132 and the doped region 134 can be used as a source region and a drain region (bit line) respectively, and the side portion 128 can be used as a Passage area 136. The charge storage layer 120 is disposed between the gate 140 and the semiconductor layer 122 . The charge storage layer 120 includes a dielectric layer 114 , a dielectric layer 118 and a charge trapping layer 116 . The dielectric layer 114 is disposed on the gate 140 . The dielectric layer 118 is disposed on the dielectric layer 114 . The charge trapping layer 116 is disposed between the dielectric layer 114 and the dielectric layer 118 . When the memory structure includes a plurality of memory cells 138 , two adjacent side portions 128 between adjacent two protruding portions 112 are isolated from each other. The memory structure further optionally includes at least one of the dielectric layer 142 and the contact window 144 . The dielectric layer 142 is disposed on the semiconductor layer 122 . The contact windows 144 are disposed in the dielectric layer 142 and connected to the doped region 132 and the doped region 134 respectively. In addition, the materials, manufacturing methods and functions of each component in the memory structure have been described in detail in the above-mentioned embodiments, so details will not be repeated here.
综上所述，上述实施例至少具有下列优点：In summary, the above embodiment has at least the following advantages:
1.上述实施例所提出的记忆体结构可以避免电性击穿漏电流的产生。1. The memory structure proposed in the above embodiments can avoid the generation of electrical breakdown leakage current.
2.藉由上述实施例所提出的方法所制造的记忆体结构可防止由二次热电子所造成的程序化干扰。2. The memory structure manufactured by the method proposed in the above embodiments can prevent programming interference caused by secondary hot electrons.
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but if they do not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solutions of the present invention.
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| CN201110342695.8ACN103077948B (en) | 2011-10-25 | 2011-10-25 | Memory structure and manufacturing method thereof |
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