CN103050544A - Bottom-gate thin film transistor and preparation method thereof - Google Patents

Abstract

Translated fromChinese

本发明公开了一种底栅薄膜晶体管及其制备方法。本发明在玻璃或者塑料的衬底上制备薄膜晶体管，采用掺镓的氧化锌半导体材料作为透明半导体导电的沟道层，在制备过程中采用独特工艺加入适量的氧气使掺镓的氧化锌呈现出半导体特性，并且显示出高迁移特性，有效的提高了薄膜晶体管的性能。本发明的制备方法步骤简单，制备成本低，对提高薄膜晶体管器件的性能具有积极效果，改善了器件性能，降低了制备成本。同时，氧化锌镓薄膜是环保材料，工艺简单，制备成本低，具有广泛的应用前景。

The invention discloses a bottom gate thin film transistor and a preparation method thereof. The present invention prepares a thin film transistor on a glass or plastic substrate, uses gallium-doped zinc oxide semiconductor material as a transparent semiconductor conductive channel layer, and uses a unique process to add an appropriate amount of oxygen during the preparation process to make the gallium-doped zinc oxide exhibit a It has semiconducting characteristics, and shows high migration characteristics, which effectively improves the performance of thin film transistors. The preparation method of the invention has simple steps and low preparation cost, has a positive effect on improving the performance of the thin film transistor device, improves the device performance and reduces the preparation cost. At the same time, the ZnGa thin film is an environmentally friendly material with a simple process and low preparation cost, and has wide application prospects.

Description

Translated fromChinese

一种底栅薄膜晶体管及其制备方法A kind of bottom gate thin film transistor and its preparation method

技术领域technical field

本发明属于平板显示领域，具体涉及一种在玻璃衬底或者塑料衬底上的底栅薄膜晶体管及其制备方法。The invention belongs to the field of flat panel display, and in particular relates to a bottom-gate thin film transistor on a glass substrate or a plastic substrate and a preparation method thereof.

背景技术Background technique

半导体产业是当今信息化社会的支柱产业，而其中起放大以及开关作用的晶体管具有极为重要的地位。晶体管从最初简单的结型和点接触晶体管到现在大规模产业化的非晶硅薄膜晶体管已有80多年的历史。20世纪六、七十年代开发的CdS、CdSe薄膜晶体管虽在有源液晶显示器AMLCD获得应用,但由于硫化物有源层的不稳定和高昂的制作成本,没有获得有产业意义的突破。稍后开发的以硅基晶体管为代表的金属-氧化物-半导体晶体管MOSFET极大地推动了平板显示器特别是有源液晶显示器的产业化进程。The semiconductor industry is the pillar industry of today's information society, and transistors, which play the role of amplification and switching, play an extremely important role. Transistors have a history of more than 80 years from the initial simple junction and point contact transistors to the large-scale industrialized amorphous silicon thin film transistors. Although the CdS and CdSe thin film transistors developed in the 1960s and 1970s were applied in the active liquid crystal display AMLCD, but due to the instability of the sulfide active layer and the high production cost, no industrial breakthrough was achieved. The metal-oxide-semiconductor transistor MOSFET developed later, represented by silicon-based transistors, has greatly promoted the industrialization process of flat panel displays, especially active liquid crystal displays.

传统工艺使用非晶硅薄膜晶体管技术，后来，又研究开发多晶硅技术。但非晶硅薄膜晶体管工艺逐渐显露出其局限性,主要是低的迁移率和不透明性。前者限制了器件的响应速度,后者则降低器件的开口率。非晶硅晶体管的另一个突出问题是带隙小（1.17eV）,需要黑矩阵来阻挡可见光照射,以免产生额外的光生载流子,这就增加了工艺的复杂性和成本。多晶硅技术又由于制备温度高、工艺复杂、大面积均匀性差等因素很难实际应用，显示技术的发展遇到了瓶颈。近来又发展了一种基于氧化锌基的新型薄膜晶体管技术。The traditional process uses amorphous silicon thin film transistor technology, and later, polysilicon technology was researched and developed. However, the amorphous silicon TFT process gradually revealed its limitations, mainly low mobility and opacity. The former limits the response speed of the device, while the latter reduces the aperture ratio of the device. Another outstanding problem of amorphous silicon transistors is the small band gap (1.17eV), which requires a black matrix to block visible light irradiation, so as not to generate additional photogenerated carriers, which increases the complexity and cost of the process. Polysilicon technology is difficult to be practically applied due to factors such as high preparation temperature, complex process, and poor uniformity in large areas, and the development of display technology has encountered a bottleneck. Recently, a new type of thin film transistor technology based on zinc oxide has been developed.

ZnO是宽禁带II-VI族半导体，原子间主要以极性共价键结合，为纤锌矿结构，禁带宽度约为3.37eV，在可见光区的透光率达到80%以上，可用于全透明显示器；其次，氧化锌基ＴＦＴ的迁移率一般比传统非晶硅ＴＦＴ高一个数量级，电流驱动能力更强（Ｉ∝μ·Ｗ／Ｌ），更适合用于驱动有源发光二极管显示屏AMOLED。另外，它在室温下可通过磁控溅射大面积均匀成膜，因此可用于柔性显示器。由于氧化锌基薄膜晶体管TFT所展示出来的优良电学性能和较为简单的制备条件，与硅基薄膜晶体管TFT相比，氧化锌基TFT比较适合应用于新型显示器件。ZnO is a wide bandgap II-VI semiconductor. The atoms are mainly bonded by polar covalent bonds. It is a wurtzite structure. The bandgap width is about 3.37eV. The light transmittance in the visible light region reaches more than 80%. Fully transparent display; Secondly, the mobility of zinc oxide-based TFT is generally an order of magnitude higher than that of traditional amorphous silicon TFT, and the current driving capability is stronger (I∝μ·W/L), which is more suitable for driving active light-emitting diode displays. AMOLED. In addition, it can be uniformly formed into a large area by magnetron sputtering at room temperature, so it can be used for flexible displays. Due to the excellent electrical properties and relatively simple preparation conditions exhibited by the zinc oxide-based thin film transistor TFT, compared with the silicon-based thin film transistor TFT, the zinc oxide-based TFT is more suitable for application in new display devices.

目前，关于氧化锌基半导体薄膜材料的研究有很多，比如氧化锌镓ZnO＋Ga₂O₃，氧化锌铝ZnO＋Al₂O₃，氧化锌铟ZnO＋In₂O₃，氧化锌镉ZnO＋Gd₂O₃，氧化锌镁ZnO＋MgO，氧化锌铟镓（Indium Gallium Zinc Oxide，IGZO）等等。其中，IGZO是目前最受欢迎的透明半导体材料，然而由于材料中的In是稀有元素，地球中含量稀少而且有毒，制造本高而且不环保，因此很难在大规模生中应用。氧化锌镓ZnO＋Ga₂O₃还较少有人研究，而且氧化锌镓通常被当成透明导电材料研究。At present, there are many studies on zinc oxide-based semiconductor thin film materials, such as zinc gallium oxide ZnO+Ga₂ O₃ , zinc aluminum oxide ZnO+Al₂ O₃ , zinc indium oxide ZnO+In₂ O₃ , zinc cadmium oxide ZnO+Gd₂ O₃ , zinc magnesium oxide ZnO+MgO, Indium Gallium Zinc Oxide (IGZO) and so on. Among them, IGZO is currently the most popular transparent semiconductor material. However, because In in the material is a rare element, the content in the earth is rare and toxic, the manufacturing cost is high and it is not environmentally friendly, so it is difficult to apply in large-scale production. Zinc gallium oxide ZnO+Ga₂ O₃ is still less studied, and zinc gallium oxide is usually studied as a transparent conductive material.

发明内容Contents of the invention

针对现有技术中存在的问题，提出本发明。In view of the problems existing in the prior art, the present invention is proposed.

本发明的一个目的在于提供一种薄膜晶体管。An object of the present invention is to provide a thin film transistor.

本发明的薄膜晶体管包括：衬底、栅电极、栅介质层、沟道层、源电极和漏电极，其中，在衬底上形成栅电极，在栅电极上形成栅介质层，在栅介质层上形成沟道层，以及在沟道层的两端分别形成源电极和漏电极，沟道层的材料采用掺镓的氧化锌半导体材料，其中镓的含量为1%~10%（质量）。The thin film transistor of the present invention comprises: a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode, wherein a gate electrode is formed on the substrate, a gate dielectric layer is formed on the gate electrode, and a gate dielectric layer is formed on the gate dielectric layer A channel layer is formed on the channel layer, and a source electrode and a drain electrode are respectively formed at both ends of the channel layer. The material of the channel layer is a gallium-doped zinc oxide semiconductor material, wherein the content of gallium is 1% to 10% (by mass).

衬底的材料为透明的玻璃或者柔性的塑料。The material of the substrate is transparent glass or flexible plastic.

栅电极的材料为氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。The material of the gate electrode is a transparent conductive material such as indium tin oxide ITO or zinc gallium oxide GZO.

栅介质层的材料采用二氧化硅或者氮化硅等的绝缘材料。The gate dielectric layer is made of insulating materials such as silicon dioxide or silicon nitride.

源电极和漏电极为氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。The source electrode and the drain electrode are transparent conductive materials such as indium tin oxide ITO or zinc gallium oxide GZO.

本发明的另一个目的在于提供一种薄膜晶体管的制备方法。Another object of the present invention is to provide a method for preparing a thin film transistor.

本发明的薄膜晶体管的制备方法包括以下步骤：The preparation method of the thin film transistor of the present invention comprises the following steps:

1）在玻璃或者塑料的衬底上生长一层透明的导电薄膜，光刻刻蚀形成栅电极；1) A transparent conductive film is grown on a glass or plastic substrate, and a gate electrode is formed by photolithography;

2）紧接着生长一层绝缘的栅介质材料，光刻刻蚀形成栅介质层；2) Next, a layer of insulating gate dielectric material is grown, and a gate dielectric layer is formed by photolithography;

3）在栅介质层上生长一层掺镓的氧化锌半导体材料，并通入适量的氧气，光刻刻蚀形成沟道层；3) A layer of gallium-doped zinc oxide semiconductor material is grown on the gate dielectric layer, and an appropriate amount of oxygen is introduced, and the channel layer is formed by photolithography;

4）生长一层导电薄膜，光刻刻蚀形成源电极和漏电极；4) Grow a layer of conductive film, photolithography and etching to form source and drain electrodes;

5）生长一层钝化介质层，光刻和刻蚀形成栅电极、源电极和漏电极的引出孔；5) Grow a layer of passivation dielectric layer, photolithography and etching to form the lead-out holes of gate electrode, source electrode and drain electrode;

6）生长一层金属薄膜，光刻和刻蚀形成金属电极和互连。6) Grow a layer of metal film, photolithography and etching to form metal electrodes and interconnections.

其中，在步骤1）中，形成栅电极所生长的导电薄膜采用氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。Wherein, in step 1), transparent conductive materials such as indium tin oxide ITO or zinc gallium oxide GZO are used as the conductive film grown to form the gate electrode.

在步骤2）中，形成栅介质层所生长的栅介质材料采用二氧化硅或者氮化硅等的绝缘材料。In step 2), insulating materials such as silicon dioxide or silicon nitride are used as the gate dielectric material grown to form the gate dielectric layer.

在步骤3）中，利用溅射工艺生长一层掺镓的氧化锌半导体材料形成沟道层，并且在溅射过程中加入5%~25%（气体流量）适量的氧气；溅射使用的靶材为掺镓的氧化锌陶瓷靶，其中镓的含量为1%~10%（质量）。In step 3), use a sputtering process to grow a layer of gallium-doped zinc oxide semiconductor material to form a channel layer, and add an appropriate amount of oxygen at 5% to 25% (gas flow rate) during the sputtering process; the target used for sputtering The material is zinc oxide ceramic target doped with gallium, and the content of gallium is 1%~10% (mass).

在步骤4）中，形成源电极和漏电极所生长的导电薄膜采用氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。In step 4), transparent conductive materials such as indium tin oxide ITO or zinc gallium oxide GZO are used for the conductive film grown on the source electrode and the drain electrode.

本发明的有益效果：Beneficial effects of the present invention:

本发明提供了一种在玻璃或者塑料的衬底上制备薄膜晶体管的制备方法，采用掺镓的氧化锌半导体材料作为透明半导体导电的沟道层，在制备过程中采用独特工艺加入适量的氧气使掺镓的氧化锌呈现出半导体特性，并且显示出高迁移特性，有效的提高了薄膜晶体管的性能。本发明的制备方法步骤简单，制备成本低，对提高薄膜晶体管器件的性能具有积极效果，改善了器件性能，降低了制备成本。同时，氧化锌镓薄膜是环保材料，工艺简单，制备成本低，适用于透明显示和柔性显示技术，具有广泛的应用前景。The invention provides a method for preparing a thin film transistor on a glass or plastic substrate. Gallium-doped zinc oxide semiconductor material is used as a transparent semiconductor conductive channel layer. During the preparation process, an appropriate amount of oxygen is added to make the Gallium-doped zinc oxide exhibits semiconductor characteristics and high mobility characteristics, which effectively improves the performance of thin film transistors. The preparation method of the invention has simple steps and low preparation cost, has a positive effect on improving the performance of the thin film transistor device, improves the device performance and reduces the preparation cost. At the same time, zinc gallium oxide thin film is an environmentally friendly material with simple process and low preparation cost, suitable for transparent display and flexible display technology, and has broad application prospects.

附图说明Description of drawings

图1为本发明的薄膜晶体管的剖面图；Fig. 1 is the sectional view of thin film transistor of the present invention;

图2为本发明的薄膜晶体管的俯视图；2 is a top view of the thin film transistor of the present invention;

图3（a）～（e）依次示出了本发明的薄膜晶体管的制备方法的一个实施例的主要工艺步骤，其中，（a）为衬底的结构示意图，（b）为形成栅电极的工艺步骤，（c）为形成栅介质层的工艺步骤，（d）为形成沟道层的工艺步骤，（e）为形成源电极和漏电极的工艺步骤。Figure 3 (a) to (e) sequentially show the main process steps of an embodiment of the thin film transistor manufacturing method of the present invention, wherein (a) is a schematic structural view of the substrate, (b) is the structure of the gate electrode Process steps, (c) is a process step of forming a gate dielectric layer, (d) is a process step of forming a channel layer, and (e) is a process step of forming a source electrode and a drain electrode.

具体实施方式Detailed ways

下面结合附图，通过具体实施例，进一步阐述本发明。The present invention will be further elaborated below through specific embodiments in conjunction with the accompanying drawings.

如图1和图2所示，本发明的薄膜晶体管包括：衬底1、栅电极2、栅介质层3、沟道层4、源电极和漏电极5，其中，在衬底1上形成栅电极2，在栅电极2上形成栅介质层3，在栅介质层3上形成沟道层4，以及在沟道层4的两端分别形成源电极和漏电极5。As shown in Figure 1 and Figure 2, the thin film transistor of the present invention comprises:substrate 1,gate electrode 2, gatedielectric layer 3,channel layer 4, source electrode anddrain electrode 5, wherein, form gate onsubstrate 1electrode 2 , forming a gatedielectric layer 3 on thegate electrode 2 , forming achannel layer 4 on the gatedielectric layer 3 , and forming a source electrode and adrain electrode 5 at both ends of thechannel layer 4 .

本发明的薄膜晶体管的制备制作方法的一个实施例由图3（a）至图3（e）所示，包括以下步骤：An embodiment of the manufacturing method of the thin film transistor of the present invention is shown in Figure 3(a) to Figure 3(e), including the following steps:

1）采用透明的玻璃或者塑料作为衬底1，如图3（a）所示，在衬底1上采用磁控溅射技术生长一层10~100纳米厚的ITO的导电薄膜，然后光刻刻蚀出栅电极2，如图3（b）所示；1) Use transparent glass or plastic as thesubstrate 1, as shown in Figure 3(a), grow a conductive thin film of ITO with a thickness of 10-100 nanometers on thesubstrate 1 using magnetron sputtering technology, and then photolithography Etching thegate electrode 2, as shown in FIG. 3(b);

2）利用等离子体增强化学气相沉积法PECVD生长一层50～200纳米厚的二氧化硅的栅介质材料，然后光刻刻蚀形成栅介质层3，如图3（c）所示；2) A layer of silicon dioxide gate dielectric material with a thickness of 50 to 200 nanometers is grown by plasma-enhanced chemical vapor deposition method PECVD, and then the gatedielectric layer 3 is formed by photolithography and etching, as shown in FIG. 3(c);

3）利用溅射工艺生长一层掺镓的氧化锌半导体材料，溅射过程中加入5%-25%的氧气，光刻刻蚀形成沟道层4，溅射使用的靶材为掺镓的氧化锌陶瓷靶，镓的含量为1%-10%，如图（d）所示；3) A layer of gallium-doped zinc oxide semiconductor material is grown by sputtering, 5%-25% oxygen is added during the sputtering process, and thechannel layer 4 is formed by photolithography. The target used for sputtering is gallium-doped Zinc oxide ceramic target, the content of gallium is 1%-10%, as shown in figure (d);

4）采用磁控溅射技术生长一层20~300纳米厚的ITO的导电薄膜，然后光刻刻蚀形成源电极和漏电极5，如图（e）所示；4) Using magnetron sputtering technology to grow a conductive thin film of ITO with a thickness of 20-300 nanometers, and then photolithography and etching to form the source electrode anddrain electrode 5, as shown in figure (e);

5）按照标准工艺生长一层钝化介质层，光刻和刻蚀形成栅电极、源电极和漏电极的引出孔；5) Grow a layer of passivation dielectric layer according to the standard process, photolithography and etching to form the lead-out holes of the gate electrode, source electrode and drain electrode;

6）生长一层Al或者透明的导电的金属薄膜，光刻和刻蚀形成电极和互连。6) A layer of Al or a transparent conductive metal film is grown, and electrodes and interconnections are formed by photolithography and etching.

最后需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附的权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。Finally, it should be noted that the purpose of the disclosed embodiments is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications can be made without departing from the spirit and scope of the present invention and the appended claims. It is possible. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

Claims (10)

Translated fromChinese

1.一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：衬底（1）、栅电极（2）、栅介质层（3）、沟道层（4）、源电极和漏电极（5），其中，在所述衬底（1）上形成所述栅电极（2），在所述栅电极（2）上形成所述栅介质层（3），在所述栅介质层（3）上形成所述沟道层（4），以及在所述沟道层（4）的两端分别形成所述源电极和漏电极（5），所述沟道层（4）的材料采用掺镓的氧化锌半导体材料，其中镓的含量为1%~10%（质量）。1. A thin film transistor, characterized in that the thin film transistor comprises: a substrate (1), a gate electrode (2), a gate dielectric layer (3), a channel layer (4), a source electrode and a drain electrode (5 ), wherein the gate electrode (2) is formed on the substrate (1), the gate dielectric layer (3) is formed on the gate electrode (2), and the gate dielectric layer (3) The channel layer (4) is formed on the channel layer (4), and the source electrode and the drain electrode (5) are respectively formed at both ends of the channel layer (4), and the material of the channel layer (4) is gallium-doped Zinc oxide semiconductor material, wherein the content of gallium is 1%~10% (mass).2.如权利要求1所述的薄膜晶体管，其特征在于，所述衬底的材料为透明的玻璃或者柔性的塑料。2. The thin film transistor according to claim 1, wherein the material of the substrate is transparent glass or flexible plastic.3.如权利要求1所述的薄膜晶体管，其特征在于，所述栅电极的材料为氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。3 . The thin film transistor according to claim 1 , wherein the material of the gate electrode is a transparent conductive material such as indium tin oxide (ITO) or zinc gallium oxide (GZO). 4 .4.如权利要求1所述的薄膜晶体管，其特征在于，所述栅介质层的材料采用二氧化硅或者氮化硅等的绝缘材料。4. The thin film transistor according to claim 1, wherein the material of the gate dielectric layer is an insulating material such as silicon dioxide or silicon nitride.5.如权利要求1所述的薄膜晶体管，其特征在于，所述源电极和漏电极为氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。5. The thin film transistor according to claim 1, wherein the source electrode and the drain electrode are transparent conductive materials such as indium tin oxide (ITO) or zinc gallium oxide (GZO).6.一种薄膜晶体管的制备方法，其特征在于，所述制备方法包括以下步骤：6. A preparation method of a thin film transistor, characterized in that the preparation method comprises the following steps:1）在玻璃或者塑料的衬底上生长一层透明的导电薄膜，光刻刻蚀形成栅电极；1) A transparent conductive film is grown on a glass or plastic substrate, and a gate electrode is formed by photolithography;2）紧接着生长一层绝缘的栅介质材料，光刻刻蚀形成栅介质层；2) Next, a layer of insulating gate dielectric material is grown, and a gate dielectric layer is formed by photolithography;3）在栅介质层上生长一层掺镓的氧化锌半导体材料，并通入适量的氧气，光刻刻蚀形成沟道层；3) A layer of gallium-doped zinc oxide semiconductor material is grown on the gate dielectric layer, and an appropriate amount of oxygen is introduced, and the channel layer is formed by photolithography;4）生长一层导电薄膜，光刻刻蚀形成源电极和漏电极；4) Grow a layer of conductive film, photolithography and etching to form source and drain electrodes;5）生长一层钝化介质层，光刻和刻蚀形成栅电极、源电极和漏电极的引出孔；5) Grow a layer of passivation dielectric layer, photolithography and etching to form the lead-out holes of gate electrode, source electrode and drain electrode;6）生长一层金属薄膜，光刻和刻蚀形成金属电极和互连。6) Grow a layer of metal film, photolithography and etching to form metal electrodes and interconnections.7.如权利要求6所述的制备方法，其特征在于，在步骤1）中，形成所述栅电极所生长的导电薄膜采用氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。7 . The preparation method according to claim 6 , wherein in step 1), transparent conductive materials such as indium tin oxide (ITO) or zinc gallium oxide (GZO) are used for the conductive thin film grown on the gate electrode.8.如权利要求6所述的制备方法，其特征在于，在步骤2）中，形成所述栅介质层所生长的栅介质材料采用二氧化硅或者氮化硅等的绝缘材料。8 . The preparation method according to claim 6 , wherein in step 2), the gate dielectric material grown to form the gate dielectric layer is an insulating material such as silicon dioxide or silicon nitride.9.如权利要求6所述的制备方法，其特征在于，在步骤3）中，利用溅射工艺生长一层掺镓的氧化锌半导体材料形成沟道层，并且在溅射过程中加入5%~25%（气体流量）的氧气；溅射使用的靶材为掺镓的氧化锌陶瓷靶，镓的含量为1%~10%（质量）。9. The preparation method according to claim 6, characterized in that, in step 3), a layer of gallium-doped zinc oxide semiconductor material is grown by sputtering to form a channel layer, and 5% ~25% (gas flow rate) of oxygen; the target used for sputtering is gallium-doped zinc oxide ceramic target, and the content of gallium is 1%~10% (mass).10.如权利要求6所述的制备方法，其特征在于，在步骤4）中，形成源电极和漏电极所生长的导电薄膜采用氧化铟锡ITO或氧化锌镓GZO等的透明的导电材料。10 . The preparation method according to claim 6 , wherein in step 4), transparent conductive materials such as indium tin oxide (ITO) or zinc gallium oxide (GZO) are used for the conductive film grown on the source electrode and the drain electrode.

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