SiGe heterojunction bipolar transistor and manufacture method thereofTechnical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of germanium silicon (SiGe) heterojunction bipolar transistor (HBT).The invention still further relates to the manufacture method of SiGe heterojunction bipolar transistor.
Background technology
Because modern communications is to the demand of the RF assembly of high-performance, low noise and low cost under high frequency band, existing Si material devices cannot meet the new requirement of specification, power output and the linearity, and power SiGe HBT then plays a significant role in the power amplifier of higher, wider frequency range.Compared with GaAs device, although SiGe HBT also locates inferior position in frequency, but SiGe HBT is with better thermal conductivity and good substrate mechanical performance, and solve the heat dissipation problem of power amplifier preferably, SiGe HBT also has the better linearity, more high integration; SiGe HBT still belongs to silicon-based technologies, and CMOS technology has good compatibility, and SiGe BiCMOS technique provides great facility for the integrated of power amplifier andlogic control circuit, also reduces process costs.
SiGe HBT has extensively been adopted to be applied to radio communication product as high-frequency high-power power discharging device, as the power amplifier in mobile phone and low noise amplifier etc. in the world at present.In order to improve the power output of radio-frequency power amplifier, passing through to improve operating current and improve operating voltage within the scope of proper device operation is all effective mode.The collector region resistance being reduced germanium silicium HBT by various technological design and device layout is also most important to the maximum frequency of oscillation reducing power consumption and raising device.Meanwhile, the size of device is reduced to improving the integrated level of integrated circuit and reducing some parasitic parameters (as base resistance, collector region resistance, electric capacity etc.), improve the performance of device to be also important means.For for germanium silicium HBT, high resistance to voltage device can make circuit obtain small electric stream under equal-wattage, thus reduces power consumption, and thus demand is extensive.Therefore how retainer member characteristic frequency while improve the withstand voltage study hotspot more and more becoming germanium silicium HBT device of SiGe HBT further.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of SiGe heterojunction bipolar transistor, the Electric Field Distribution of collector region can be improved, improve the junction breakdown voltage between collector region and base thus the puncture voltage of raising device, can the area of reduction of device, reduce the junction capacitance of base and collector region and improve the frequency characteristic of device.For this reason, the present invention also provides a kind of manufacture method of SiGe heterojunction bipolar transistor.
For solving the problems of the technologies described above, SiGe heterojunction bipolar transistor provided by the invention is formed on silicon substrate, and active area is isolated by shallow groove field oxygen, and SiGe heterojunction bipolar transistor comprises:
Collector region, is made up of the N-type ion implanted region be formed in described active area, and the described collector region degree of depth is greater than the degree of depth bottom described shallow groove field oxygen and the horizontal expansion of described collector region enters bottom the shallow groove field oxygen of described active area week side.
Counterfeit buried regions, by be formed at described active area week side shallow groove field oxygen bottom N-type ion implanted region form, the edge of described counterfeit buried regions and described active area be separated by a segment distance and and the extension of described collector region touch at described shallow groove field oxygen bottom connection, in the described shallow groove field oxygen at described counterfeit buried regions top, be formed with deep hole contact, this deep hole contact draws collector electrode.
Polysilicon field plate, is formed at described shallow groove field oxygen upper of described active area week side, and the region that described polysilicon field plate covers comprises the part extending to part bottom described shallow groove field oxygen and described counterfeit buried regions of described collector region; Above described polysilicon field plate, be formed with Metal Contact, this Metal Contact is connected with described collector electrode.
Base, is made up of the P type germanium silicon epitaxial layer be formed on described active area, and described base contacts on the surface of described active area and described collector region.
Emitter region, is made up of the N-type polycrystalline silicon being formed at top, described base, and described emitter region and described base contact, and the size of described emitter region is less than the size of described base; Be formed with Metal Contact at the top of described emitter region, this Metal Contact contacts with described emitter region and draws emitter.
Be intrinsic base region with the described base that described emitter region contacts, the described base outside described intrinsic base region is outer base area, and the doping content of described outer base area is greater than the doping content of described intrinsic base region; Be formed with Metal Contact at the top of described outer base area, this Metal Contact contacts with described outer base area and draws base stage.
Further improvement is, in the side of described emitter region, the side of the side of described base and described polysilicon field plate is all formed with side wall.
For solving the problems of the technologies described above, the manufacture method of SiGe heterojunction bipolar transistor provided by the invention comprises the steps:
Step one, on a silicon substrate formation shallow trench and active area.
Step 2, described active area week side the N-type ion implantation of carrying out of bottom of described shallow trench form counterfeit buried regions, the edge of described counterfeit buried regions and described active area is separated by a lateral separation.
Step 3, insert in described shallow trench silica formed shallow groove field oxygen.
Step 4, in described active area, carry out N-type ion implantation form collector region, the described collector region degree of depth be greater than the degree of depth bottom described shallow groove field oxygen and the horizontal expansion of described collector region enter described active area week side described shallow groove field oxygen bottom and formed with described counterfeit buried regions and contact.
Step 5, described silicon substrate front deposit one deck polysilicon and etching formed polysilicon field plate, described polysilicon field plate is positioned at described shallow groove field oxygen upper of described active area week side, and the region that described polysilicon field plate covers comprises the part extending to part bottom described shallow groove field oxygen and described counterfeit buried regions of described collector region.
Step 6, form base in described active region, described base is formed after being etched by a P-type silicon epitaxial germanium layer, and described base contacts with the formation of described collector region.
Step 7, above described base, form emitter region, described emitter region is formed after being etched by N-type polycrystalline silicon; The size of described emitter region is less than the size of described base, and described emitter region is positioned at the top of the middle section of described base; Described emitter region is formed with described base and contacts; Be intrinsic base region with the described base that described emitter region contacts, outside described intrinsic base region is outer base area.
Step 8, employing ion implantation technology mix p type impurity in described outer base area.
Step 9, in the shallow groove field oxygen at described counterfeit buried regions top, form deep hole contact draw described collector electrode; Form Metal Contact at the top of described polysilicon field plate and this Metal Contact is connected with described collector electrode; Form Metal Contact at top, described emitter region and draw emitter; Form Metal Contact at the top of described outer base area and draw base stage.
Further improvement is, the N-type ion implantation technology condition of counterfeit buried regions described in step 2 is: implanted dopant is phosphorus, implantation dosage 1e14cm-2~ 1e16cm-2, Implantation Energy is 2KeV ~ 50KeV.
Further improvement is, the N-type ion implantation technology condition of collector region described in step 4 is: implanted dopant is phosphorus or arsenic, implantation dosage 2e12cm-2~ 5e14cm-2, Implantation Energy is 30KeV ~ 350KeV.
Further improvement is, the step forming base window is also comprised before forming described base in step 6, first deposit first medium layer on described silicon substrate, etch described first medium layer again and form described base window, described base window is positioned at the top of described active area and the size of described base window is more than or equal to the size of described active area, and described base window definition goes out the contact area of described collector region and described base.
Further improvement is, also comprises the step forming emitter window in step 7 before forming described emitter region, first deposition of second dielectric layer on described silicon substrate, and described second dielectric layer and described germanium silicon epitaxial layer contact; Etch described second dielectric layer and form emitter window, described emitter window to be positioned at directly over described base and less than the size of described base; Described emitter window defines the contact area of described base and described emitter region.
The present invention has following beneficial effect:
1, the bottom of the shallow groove field oxygen by collector region being extended to active area week side of the present invention, can be that the depleted region of the knot of collector region and base is changed to two dimension by one dimension, i.e. longitudinal broadening of depletion region and oriented substrate bottom direction, the horizontal broadening of the oriented bottom direction along shallow groove field oxygen again, the depleted region structure of the collector region of two dimension and the knot of base can make collector region and base junction breakdown voltage improve, thus improves the puncture voltage of whole device.
2, the present invention by arranging a polysilicon field plate above shallow groove field oxygen, and the transverse area of collector region covers by this polysilicon field plate, and the Electric Field Distribution of collector region can be made to improve, thus further improve the puncture voltage of device.
3, the present invention is that counterfeit buried regions bottom shallow groove field oxygen by being formed at active area week side to be connected with collector region and to draw collector electrode by a deep hole contact, relative to be connected in the active area adjacent with collector region by a buried regions in prior art and to form the structure that Metal Contact draws collector electrode in adjacent active area, the present invention can greatly reduce device size and area.
4, the present invention draws the collector region of the deep hole contact distance device of collector electrode very closely, can reduce the parasitic capacitance of collector resistance and collector electrode, thus can improve the frequency characteristic of device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of embodiment of the present invention SiGe heterojunction bipolar transistor;
Fig. 2 A-Fig. 2 E is the device architecture schematic diagram in each step of the manufacture method of embodiment of the present invention SiGe heterojunction bipolar transistor.
Embodiment
As shown in Figure 1, be the structural representation of embodiment of the present invention SiGe heterojunction bipolar transistor.Embodiment of the present invention SiGe heterojunction bipolar transistor is formed in P-type silicon substrate 101, and active area is isolated by shallow groove field oxygen 201, and SiGe heterojunction bipolar transistor comprises:
Collector region 202, be made up of the N-type ion implanted region be formed in described active area, described collector region 202 degree of depth is greater than the degree of depth bottom described shallow groove field oxygen 201 and described collector region 202 horizontal expansion enters bottom the shallow groove field oxygen 201 of described active area week side.
Counterfeit buried regions 107, by be formed at described active area week side shallow groove field oxygen 201 bottom N-type ion implanted region form, the edge of described counterfeit buried regions 107 and described active area be separated by a segment distance and and the extension of described collector region 202 touch at described shallow groove field oxygen 201 bottom connection, in the described shallow groove field oxygen 201 at described counterfeit buried regions 107 top, be formed with deep hole contact 601, this deep hole contact 601 draws collector electrode.
Polysilicon field plate 301, be formed at described shallow groove field oxygen 201 upper of described active area week side, the region that described polysilicon field plate 301 covers comprises the part extending to part bottom described shallow groove field oxygen 201 and described counterfeit buried regions 107 of described collector region 202; Above described polysilicon field plate 301, be formed with Metal Contact 602, this Metal Contact 602 is connected with described collector electrode.Described polysilicon field plate 301 can be identical with the polysilicon gate process condition in CMOS technology, and the two can integrate and be formed simultaneously.
Base 403, is made up of the P type germanium silicon epitaxial layer be formed on described active area, and described base 403 contacts on the surface of described active area and described collector region 202.
Emitter region 402, be made up of the N-type polycrystalline silicon being formed at top, described base 403, described emitter region 402 and described base 403 contact, and the size of described emitter region 402 is less than the size of described base 403.The contact area of described emitter region 402 and described base 403 etches the rear emitter window formed by second dielectric layer 401 and defines.Second dielectric layer 401 described in the embodiment of the present invention is a silicon dioxide layer.Be formed with Metal Contact 602 at the top of described emitter region 402, this Metal Contact 602 contacts with described emitter region 402 and draws emitter.
The described base 403 contacted with described emitter region 402 is intrinsic base region, and the described base 403 outside described intrinsic base region is outer base area, and the doping content of described outer base area is greater than the doping content of described intrinsic base region; Be formed with Metal Contact 602 at the top of described outer base area, this Metal Contact 602 contacts with described outer base area and draws base stage.In the side of described emitter region 402, the side of the side of described base 403 and described polysilicon field plate 301 is all formed with side wall 501,502 and 503.Be formed with metal level 603 at the top layer of device, this metal level 603 realizes the interconnection of device.
As shown in Fig. 2 A to Fig. 2 E, it is the device architecture schematic diagram in each step of the manufacture method of embodiment of the present invention SiGe heterojunction bipolar transistor.The manufacture method of embodiment of the present invention SiGe heterojunction bipolar transistor comprises the steps:
Step one, as shown in Figure 2 A, adopts lithographic etch process to form shallow trench and active area on silicon substrate 101.During etching, described active region hard mask layers is protected, and described hard mask layers comprises oxide layer 102, nitration case 103 and oxide layer 104.
As shown in Figure 2 A, after forming described shallow trench, deposit one deck oxide also etches, and form oxide side walls 105 at the medial surface of described shallow trench, the lower surface of described shallow trench also retains one deck oxide 106.
Step 2, as shown in Figure 2 A, in described active area week, the N-type ion implantation of carrying out of bottom of described shallow trench of side forms counterfeit buried regions 107, and the edge of described counterfeit buried regions 107 and described active area is separated by a lateral separation.Described counterfeit buried regions 107 injection zone is defined by photoresist.The N-type ion implantation technology condition of described counterfeit buried regions 107 is: implanted dopant is phosphorus, implantation dosage 1e14cm-2~ 1e16cm-2, Implantation Energy is 2KeV ~ 50KeV.
Step 3, as shown in Figure 2 B, inserts silica and forms shallow groove field oxygen 201 in described shallow trench.
Step 4, as shown in Figure 2 C, in described active area, carry out N-type ion implantation form collector region 202, described collector region 202 degree of depth be greater than the degree of depth bottom described shallow groove field oxygen 201 and described collector region 202 horizontal expansion enter described active area week side described shallow groove field oxygen 201 bottom and formed with described counterfeit buried regions 107 and contact.The N-type ion implantation technology condition of described collector region 202 is: implanted dopant is phosphorus or arsenic, implantation dosage 2e12cm-2~ 5e14cm-2, Implantation Energy is 30KeV ~ 350KeV.
Step 5, as shown in Figure 2 C, at described silicon substrate 101 front deposit one deck polysilicon also etching formation polysilicon field plate 301, described polysilicon field plate 301 is positioned at described shallow groove field oxygen 201 upper of described active area week side, and the region that described polysilicon field plate 301 covers comprises the part extending to part bottom described shallow groove field oxygen 201 and described counterfeit buried regions 107 of described collector region 202.Described polysilicon field plate 301 can be identical with the polysilicon gate process condition in CMOS technology, and the two can integrate and be formed simultaneously.
Step 6, as shown in Figure 2 D, first deposit first medium layer on described silicon substrate 101, etch described first medium layer again and form described base window, described base window is positioned at the top of described active area and the size of described base window is more than or equal to the size of described active area, and described base window definition goes out the contact area of described collector region 202 and described base 403.
Form a P-type silicon epitaxial germanium layer in the described front stating silicon substrate 101, etch described silicon germanium extension layer and form base 403.Described base 403 is positioned at described active region and is formed with described collector region 202 in the region of described base window definition and contacts.
Step 7, as shown in Figure 2 D, deposition of second dielectric layer 401 on described silicon substrate 101, described second dielectric layer 401 is monoxide dielectric layer.Described second dielectric layer 401 and described germanium silicon epitaxial layer contact; Etch described second dielectric layer 401 and form emitter window, described emitter window to be positioned at directly over described base 403 and less than the size of described base 403; Described emitter window defines the contact area of described base 403 and described emitter region 402.
In front deposit one deck N-type polycrystalline silicon of described silicon substrate 101, in the region of described emitter window, described N-type polycrystalline silicon and described base 403 contact.Adopt ion implantation technology adulterate to described N-type polycrystalline silicon and adopt thermal anneal process to activate, the process conditions of the ion implantation of described N-type polycrystalline silicon are: implanted dopant is phosphorus or arsenic, and implantation dosage is greater than 2e15cm-2, Implantation Energy is determined by the thickness of described N-type polycrystalline silicon, can not penetrate described N-type polycrystalline silicon.
As shown in Figure 2 D, lithography process glue at quarter is adopted to define the forming region of emitter region, with described photoresist for the described N-type polycrystalline silicon 402 of the region exterior of described emitter region and described second dielectric layer 401 are all removed by mask, finally form emitter region 402 as shown in Figure 2 D.The size of described emitter region 402 is less than the size of described base 403, and described emitter region 402 is positioned at the top of the middle section of described base 403; Described emitter region 402 is formed with described base 403 and contacts; The described base 403 contacted with described emitter region 402 is intrinsic base region, and outside described intrinsic base region is outer base area.
Step 8, as shown in Figure 2 D, adopts ion implantation technology to mix p type impurity in described outer base area.
As shown in Figure 2 E, first at front deposit one deck medium of oxides layer of described silicon substrate 101, comprehensive etching technics is adopted to etch this medium of oxides layer, the medium of oxides layer at the plane place above described silicon substrate 101 is all removed, and in the side of described emitter region 402, the side of the side of described base 403 and described polysilicon field plate 301 is all formed with side wall 501,502 and 503.
Step 9, as shown in Figure 1, in the shallow groove field oxygen 201 at described counterfeit buried regions 107 top, form deep hole contact 601 draw described collector electrode; Form Metal Contact 602 at the top of described polysilicon field plate 301 and this Metal Contact 602 is connected with described collector electrode; Form Metal Contact 602 at top, described emitter region 402 and draw emitter; Form Metal Contact 602 at the top of described outer base area and draw base stage.The interconnection that metal level 603 realizes device is formed at the top layer of device.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.