This application claims the U.S. Provisional Application S/N61/544 submitted on October 6th, 2011, the U.S. Provisional Application S/N61/544 that on October 6th, 044 and 2011 submits to, the rights and interests of 058, the full content of these applications is for institute is intentional and object is incorporated herein by reference.
Embodiment
Provide following description can implement to make those of ordinary skill in the art under the background of application-specific and demand thereof and the present invention provided is provided.But General Principle as defined herein clearly, and will can be applied to other embodiment to those of ordinary skill in the art by the multiple amendment of preferred embodiment.Therefore, the present invention is not intended to be limited to the specific embodiment illustrating and describe herein, and should be given the widest scope consistent with principle disclosed herein and novel feature.
In the battery charger of routine, adapter is provided for the power of battery charger and system load.When system load increases, charging current reduces, and makes adapter electric current be no more than its restriction.Once charging current is reduced to 0, any additional system load can cause adapter to exceed its restriction.
Some configuration allows system load to draw the power more much bigger than the maximum rated power of adapter.This sustainable a period of time (such as, some seconds), until exceed rated temperature or until finish the work.As an example, " turbine (turbo) " pattern is introduced itself SandyBridge and IvyBridge CPU (CPU) by Intel company, this allows CPU temporarily to exceed the rated power of adapter, and this situation is sustainable until CPU is overheated or complete its task.
The situation exceeding the rated power of adapter causes safety concerns.In order to avoid being subject to the yoke of adapter overcurrent situations, battery charge modulator as herein described backward operation in a boost mode, with from battery to system load release current.When system load is increased on adapter power restriction, battery discharge current increases to prevent adapter from exceeding the restriction of its maximum current.When detection is boosted and how to be controlled transducer is theme of the present disclosure.In addition, provide battery discharge current to limit, this restriction is the function of charging current restriction.
Fig. 1 is the simplified block diagram of the electronic equipment 109 comprising battery charge modulator 111 according to embodiment of the present invention realization.AC line voltage shown in 101 places is supplied to the input of AC adapter 103, AC voltage transitions is become DC adaptor voltages VADP by this AC adapter 103.Illustrate that VADP is provided to suitable connector 105, this connector 105 mates with the compatible connector 107 being set to electronic equipment 109.In this way, VADP is provided to the input of battery charge modulator 111, and output voltage VO UT is supplied to system load 113 by this battery charge modulator 111.Cell voltage VBAT is supplied to another input of battery charge modulator 111 by rechargeable battery 119, forms VOUT for when adapter 103 is unavailable.Battery 119 and system load 113 are illustrated as over the ground (GND) and carry out reference, wherein should understand GND and generally represent any suitable plus or minus voltage level and/or multiple earthing type, such as power ground connection, signal ground, analogue ground, chassis earth etc.
Electronic equipment 109 can be the electronic equipment of any type, comprise mobile, portable or handheld device, the personal digital assistant (PDA), personal computer (PC), pocket computer, laptop computer etc. of such as any type, cell phone, personal media device etc.The major function of electronic equipment 109 is performed by system load 113, and this load can comprise one or more different system load original paper.In an illustrated embodiment, system load 113 comprises processor, such as microprocessor or controller etc., and this processor is coupled to the combination in any of any type of memory being generally used for electronic equipment, such as various types of RAM and ROM etc.
Fig. 2 is the more detailed block diagram of the battery charge modulator 111 according to one embodiment of the invention realization.Battery charge modulator 111 comprises controller 200 and power stage 204, and this power stage 204 comprises or is otherwise coupled to battery 119, and this battery 119 can be removable.Power stage 204 comprises the transducer formed by electronic switch Q1 and Q2 and inductor L, it charges to battery 119 in order to the VADP be used for from adapter 103 under can being operated in " step-down " pattern, with under " boosting " pattern to raise the voltage of battery 119, thus battery 119 is discharged to system load 113.
VADP is supplied to one end of sense resistor RSA, the node CSIP of the input being configured to controller 200 is coupled in this one end of this sense resistor RSA.In one embodiment, controller 200 realizes on integrated circuit (IC), and wherein I/O (I/O) node (illustrating with square symbols) is implemented as the pin of IC, but also can conceive different implementations.Unless otherwise indicated herein, otherwise with identical title reference node and pin.The other end of RSA is coupled to the node CSIN of another pin as controller 200.Although not shown, can exist be coupled with CSIN and CSIP pin serial connection filter element (such as, resistance, electric capacity or its combine).
Node CSIN is also used as the output node of (or being otherwise coupled to) battery charge modulator 111, forms the output voltage VO UT being supplied to system load 113.Node CSIN is coupled to the drain electrode of electronic switch Q1, and its source electrode is coupled to the drain electrode of electronic switch Q2 at phase (PHASE) node.The source-coupled of Q2 is to GND.PHASE Joint Enterprise is the pin of controller 200, and it is coupled to one end of inductor L, and the other end of this inductor L is coupled to node CSOP, and this node CSOP is coupled to one end of another sense resistor RSB.The other end of RSB is coupled to node CSON, and this node CSON is coupled to the plus end of battery 119 further, and its negative terminal is coupled to GND.CSOP and CSON is configured to the pin of controller 200, and CSOP forms cell voltage VBAT.Although not shown, can exist be coupled with CSON and CSOP pin serial connection filter element (such as, resistance, electric capacity or its combine).The switching devices such as such as transistor device can be coupling between VBAT and VOUT, the power of battery is supplied to system load 113 when adapter 103 disconnects.
In an illustrated embodiment, electronic switch Q1 and Q2 can be embodied as n channel metal oxide semiconductor field effect transistor known to those skilled in the art (MOSFET) separately.The electronic switching device of other type can be used, comprise the transistor of FET of other type etc. and other type, such as bipolar junction transistor (BJT) or igbt (IGBT) etc.
Transducer (switch Q1 and Q2 and inductor L) and sense resistor RSB jointly realize the power stage 204 of battery charge modulator 111.The operation of power stage 204 is controlled by controller 200, as further described herein.When adapter 103 connects, adapter electric current I ADP flows through sense resistor RSA.Charging current ICHG flows through sense resistor RSB, is indicated to the charging current of battery 119.As described further below, when battery 119 also provides power (electric discharge), when being in boost mode, ICHG also indicates discharging current.Load current ILD is illustrated as flowing out power stage 204, load current is supplied to system load 113.
In one embodiment, the voltage VBAT of battery 119 is between the scope of about 9 to 13 volts (V), and adaptor voltages VADP is about 19V.CSIN node is coupled to " system bus " node, forms the VOUT of about 19V.In an illustrated embodiment, when to charge to battery 119 and ICHG is timing power stage 204 is operated in step-down controller pattern (or decompression mode), and when battery 119 discharges and ICHG is operated in boost converter pattern (or boost mode) so that cell voltage is boosted to adaptor voltages level for power stage 204 time negative.Negative ICHG (-ICHG) also can be called as positive discharging current IDCHG.
CSIP and CSIN node/pin is supplied to respectively the noninverting of the current sense amplifier 201 in controller 200 or just (+) and anti-phase or negative (-) input, for sensing adapter electric current I ADP.The output of sensing amplifier 201 forms adapter current feedback (ACFB) voltage, and this voltage is provided to the upper end input of cross induction coils (CROSSMUX) 203.Adapter current reference (ACREF) voltage is provided to the lower end input of CROSSMUX203, CROSSMUX203 reception control signal BOOST (boosting).The upper right of CROSSMUX203 exports the negative input being provided to adapter current error amplifier 205, and the bottom right of CROSSMUX203 exports the positive input being provided to error amplifier 205.The output of error amplifier 205 is provided to the input that minimum current selects MUX (IMINMUX) 207.
CSOP and CSON node is supplied to the top and bottom input of another CROSSMUX209 controlled by signal BOOST.The top and bottom of CROSSMUX209 export the positive input and negative input that are supplied to charging sensing amplifier 211, for sensing charging current ICHG.The output of sensing amplifier 211 forms charging current feedback (CCFB) voltage, and this voltage is provided to the negative input of battery charging current error amplifier 215.Charging current reference voltage CCREF is provided to the upper end input of another CROSSMUX213, and discharging current reference voltage DCREF is provided to the lower end input of CROSSMUX213.The upper end of CROSSMUX213 exports the positive input being provided to error amplifier 215.The output of error amplifier 215 is provided to another input of IMINMUX207.Node ICOMP is coupled in the output of IMINMUX207, and this node ICOMP is coupled to compensation condenser C1 further, and this compensation condenser C1 is coupling between ICOMP and GND.In an illustrated embodiment, C1 is arranged on the outside of controller 200, to allow as required to regulate the compensation compensating and/or allow other appropriate format.
Error amplifier 205,215,217 is mutual conductance (gm) amplifiers providing current signal at its output.Minimum or " more negative " current level (larger current sink) of IMINMUX207 Select Error amplifier 205 and 215, and provide electric current I MIN_SEL to charge to capacitor C1, to form ICOMP voltage on ICOMP node.If two electric currents are just, then reduced-current is selected as IMIN_SEL; If electric current is just and another is negative, then negative current is selected as IMIN_SEL; If two electric currents are negative, then the electric current (more negative) had by a relatively large margin is selected as IMIN_SEL.
CSON node sensing cell voltage VBAT is also provided in controller 200 resistor divider comprising resistor R1 and R2 be coupled in series between node CSON and GND.The intermediate node of resistor R1 and R2 forms charging voltage feedback voltage CVFB, and this charging voltage feedback voltage CVFB is provided to the negative input of charging voltage error amplifier 217.Charging voltage reference voltage CVREF is provided to the positive input of error amplifier 217.Node VCOMP is coupled in the output of error amplifier 217, and this node VCOMP is coupled to the compensating circuit comprising and be coupled in series in capacitor C2 between VCOMP and GND and resistor R3 further.In an illustrated embodiment, C2 and R3 is arranged on the outside of controller 200, compensates to allow to regulate.
ICOMP and VCOMP node is provided to the corresponding input of VMIN buffer 219, VMIN buffer 219 select lower in ICOMP and VCOMP voltage level one at its output as COMP voltage.The top and bottom of CROSSMUX209 export the positive and negative input being also provided to amplifier 221 respectively, and this amplifier 221 at one end receives COMP and provides control voltage VCTRL at the other end.If the gain of amplifier 221 is G, then amplifier 221 is for generating VCTRL=COMP-G (CSOP-CSON).The gain G of amplifier 221 be relatively low gain to realize low gain inner current loops, as further described herein.
VCTRL is provided to the positive input of pulse-width modulation (PWM) comparator 223, and pulse-width modulation (PWM) comparator 223 receives RAMP voltage in its another input and exports at it and forms pwm signal.There is provided RAMP by ramp generator 226, wherein RAMP shows for triangular ramp etc. (but can contemplate the slope configuration of replacement).In one embodiment, RAMP vibrates with predetermined clock frequency.In one embodiment, the frequency of RAMP is roughly 400 kilo hertzs (KHz).By comparator 223, RAMP and VCTRL is compared to form PWM.PWM is provided to the upper end input of CROSSMUX225 and the input of synchronous grid controller 229.Synchronous grid controller 229 is coupled to PHASE and GND node (being coupled to power stage 204) and will exports the lower end input being supplied to CROSSMUX225.In one embodiment, synchronous grid controller 229 also can be coupled to CSIN node for sensing the drain source voltage (VDS) of Q1, for realizing diode emulation as required under boost mode.The upper end of CROSSMUX225 exports is coupled to node UGATE, and this node UGATE is provided to the grid of Q1, and node LGATE is coupled in the output of the lower end of CROSSMUX225, and this node LGATE is provided to the grid of Q2.
VCTRL is also provided to the positive input keeping comparator 227, and this maintenance comparator 227 receives in its negative input and keeps threshold voltage HOLDTH.HOLDTH is set to the voltage of the minimum levels lower than RAMP voltage, and this RAMP voltage tiltedly becomes between minimum ramp voltage RAMPVALLEY and peak value ramp voltage RAMPPEAK.HOLDTH is set to the voltage lower than RAMPVALLEY scheduled volume, and this scheduled volume is generally selected as being equal to or greater than the expected offset voltage sum of comparator 223 and 227 to guarantee that comparator 227 switches with the threshold voltage lower than comparator 223.The output of comparator 227 is kept signal HOLD to be supplied to the HOLD input of latch 231.Boosting comparator 233 receives ACFB and ACREF at its positive and negative input respectively, and has output, signal MODE is supplied to the IN input of latch 231.BOOST signal is provided at the Q output of latch 231.
Ramp generator 226, comparator 223, synchronous grid controller 229 and CROSSMUX225 form modulator jointly, and this modulator drives UGATE and LGATE, to control the convenor section of power stage 204 based on control voltage VCTRL.In decompression mode, modulator part drives transducer for charging to battery 119 according to reduced pressure operation.In boost mode, the output of modulator is reversed by CROSSMUX225, thus drives transducer to be used for discharging to battery 119 according to boost operations.Note, selective modulator and modulator type can be used for providing boost function.
Quick mode changes circuit 235 and comprises current sense amplifier 237 and 243, comparator 239 and 245 and delay block 241 and 247.CSIP and CSIN node is coupled to positive and negative input each in sensing amplifier 237 and 243 respectively.The output of sensing amplifier 237 is provided to the positive input of comparator 239, and this comparator 239 receives ACREF at its negative input end, and to the input of delay block 241 provide OVER (on) signal.The output of delay block 241 is provided to set (S) input of latch 231.The output of sensing amplifier 243 is provided to the negative input of comparator 245, and this comparator 245 receives ACREF at its positive input terminal, and to the input of delay block 247 provide UNDER (under) signal.The output of delay block 247 is provided to replacement (R) input of latch 231.
Each CROSSMUX (203,209,213,225) operates in the identical mode controlled by BOOST (boosting).In normal or " step-down " pattern, BOOST is low and each CROSSMUX input and is directly sent to it and exports, and upper end is inputted be coupled to upper end to export and lower end input is coupled to lower end output.In boost mode, when BOOST is asserted to high, input by cross-couplings to output, make upper end input instead be coupled to lower end export and lower end input be instead coupled to upper end export.Note, each CROSSMUX (203,209,213,225) can be positioned at other position in corresponding signal path to reverse corresponding signal.
The voltage of (between CSIP and CSIN node) across sense resistor RSA of indication adapter electric current I ADP obtains gain (such as gain is 20) by sensing amplifier 201 and relative to GND level shift to provide ACFB voltage.When BOOST is low, ACFB and ACREF (adapter current reference) directly passes error amplifier 205 to form the first control current signal.In a similar manner, the voltage of (between CSOP and CSON node) across sense resistor RSB of pilot cell charging current ICHG obtains gain (such as gain is 20) by sensing amplifier 211 and relative to GND level shift to provide CCFB voltage.When BOOST is low, CCFB and CCREF (charging current reference) is provided to error amplifier 215 to form the second control current signal.More negative current level (as previously mentioned) is selected, as the IMIN_SEL being compensated (via capacitor C1) by ICOMP node by IMINMUX207.In this way, the amplifier of less electric current is asked to be selected as possible control operation.
The cell voltage VBAT that CSON is formed is provided to resitstance voltage divider R1 and R2.Cell voltage feeds back compared with CVREF (charging voltage reference) by error amplifier 217, and the output of error amplifier 217 drives VCOMP node.
CSOP-CSON measures charging current export, and the output of this charging current arranges low gain inner current loops to reduce the Q value (de-Q) of power stage 204.As shown, when BOOST is low, CSOP and CSON is provided to amplifier 221 to regulate VCTRL signal with COMP.In one embodiment, amplifier 221 has relatively low gain (such as, gain is 5).VMIN buffer 219 selects low voltage in ICOMP and VCOMP as the COMP of feeding inner current loops, wherein to deduct the multiple (such as, 5) of charging current magnitude of voltage to form VCTRL from COMP.
VCTRL and RAMP is compared generate PWM to control the switching of Q1 and Q2 of power stage 204.In decompression mode, when BOOST is low, PWM control UGATE, with the switching of control Q1, and synchronous grid controller 229 control LGATE, with the switching of control Q2.In decompression mode, power stage 204 operates, because the voltage of VBAT is lower than VADP as buck converter.At decompression mode device, when PWM uprises, UGATE is driven to height, and with conducting Q1, and when PWM step-down, UGATE is driven to low to disconnect Q1.Delay bounds (deadtimecontrol) can be realized, make Q1 and Q2 can not simultaneously conducting.In decompression mode, in each PWM cycle period, conducting Q2 after Q1 disconnects.
Switch Q1 and Q2 not driven by PWM is called as " synchronously " switch.When at decompression mode during non-boost mode, Q1 is main switch and Q2 is synchro switch.In one embodiment, synchro switch is actuated to dummy diode (diode emulation).Particularly, when reaching about 0 through the electric current of inductor L after cycle period PWM step-down in buck mode, the remainder Q2 for this circulation disconnects.Thisly to determine to make, the voltage of PHASE and GND are compared the drain source voltage (VDS) determining Q2 by synchronous grid controller 229, and disconnect Q2 time (can relative to predetermined offset voltage) when they are roughly equal.If necessary, CSIN can be supplied to synchronous grid controller 229 to monitor the VDS of Q1, be operated in diode emulation to make Q1 during boost mode.
When boost mode, pwm signal instead drives LGATE with the switching of control Q2 (for main switch in boost mode) and Q1 is synchro switch.In boost mode, battery 119 is discharged by RSB, and power stage 204 is as boosting type converter work.When discharging current is higher than continuous current mode (CCM)/discontinuous current pattern (DCM) threshold value, Q1 is operated in synchronous mode, and is generally switched to the state contrary with Q2.Therefore, when Q2 conducting, each PWM cycle period Q1 higher than CCM/DCM threshold value disconnect and vice versa (but according to delay bounds operation, both can different time conducting).But when under boost mode, discharging current is lower than CCM/DCM threshold value, Q1 remains open, wherein its body diode becomes and can operate.As understood by those skilled in the art, other technology for control synchronization switch is also had.
CCM/DCM threshold value can be determined based on the inductance L of input voltage VADP (at CSIP place), output voltage VO UT, inductor L and frequency of operation (i.e. the frequency of RAMP).In one embodiment, VADP with RAMP frequency is relative fixing, and CCM/DCM threshold value is changed according to VOUT.In another embodiment, CCM/DCM threshold value is predetermined based on the average level of VOUT.The threshold value can selecting except CCM/DCM border according to specific implementation or operating parameter.
One of error amplifier 205,215 and 217 controls the operation selected by IMINMUX207 and VMIN buffer 219.In essence, any one equipment is operated for requiring that less curtage is to reduce the duty ratio of PWM control loop operation.In decompression mode, when BOOST is low, while VCTRL is kept above HOLDTH voltage level, keep comparator 227 to be asserted as by HOLD signal high to make the HOLD of latch 231 input remain height, thus it is low that BOOST is latched as.If VCTRL drops to lower than HOLDTH, then pwm pulse is decreased to zero and keeps comparator 227 to be asserted as by HOLD and lowly to input with the HOLD discharging latch 231.Then when MODE is asserted as height higher than comparator during ACREF 233 by ACFB, this causes BOOST to uprise.When BOOST uprises, each switching state in CROSSMUX203,209,213 and 225 is to enter boost operations pattern.
When under boost mode, BOOST is asserted to high, the input reversion of error amplifier 205, this causes ICOMP, COMP and VCNTRL to raise.Once VCTRL generates pwm pulse again higher than HOLDTH, switch unless changed circuit 235 by quick mode, otherwise the state of BOOST is latched and it can not change until VCTRL is again lower than HOLDTH, below will be described further this.Under boost mode, when system load reduce make ACFB just lower than ACREF set point time, ACFB lower than ACREF and VCTRL driven decline and MODE is low.When VCTRL becomes lower than HOLDTH, keep comparator 227 to be dragged down by HOLD, this drags down the HOLD input of latch 231, makes BOOST step-down to be switched to decompression mode.
In a word, in buck mode, when BOOST is low, each in CROSSMUX203,209,213 and 225 is inputted to be directly coupled to it and to export, and power stage 204 is operating as normal decompression mode modulator.In this case, COMP and VCTRL drives as higher by one of ACFB<ACREF or CCFB<CCREF, and pwm signal drives UGATE and inner current loops is configured to negative feedback.When BOOST uprises for boost mode, each in CROSSMUX203,209,213 and 225 is inputted cross-couplings to its output, causes power stage 204 to operate in a boost mode, with the voltage level making cell voltage be elevated to VADP.In this case, COMP drives as lower by ACFB<ACREF and CCFB<CCREF and CVFB<CVREF, and pwm signal drives LGATE, and inner current loops is redeployed as negative feedback.
When adapter is in its current limit, at steady state, adapter control loop generally regulates ACFB=ACREF, until battery reaches the restriction of its discharging current, as described in this article.But when relating to the system load step that boost mode changes, this may be comparatively slow, because ICOMP or VCOMP needs electric discharge so that VCTRL is pulled to HOLDTH, to switch between modes.Quick mode changes circuit 235 and contributes to carrying out comparatively faster switching between step-down and boost mode.
The low scheduled volume of gain of the ratio of gains current sense amplifier 201 of current sense amplifier 237, and the output of amplifier 237 and ACREF compare by comparator 239.When decompression mode, if adapter electric current I ADP increases fast in response to load increases step, make ACFB higher than ACREF respective amount, then comparator 239 switches and OVER is asserted as height.If at least remain height at the duration OVER of delay block 241, then delay block 241 triggers and arranges latch 235 to draw high BOOST to be switched to the state of boost mode and no matter IN or HOLD.
In one embodiment, the gain (such as, gain is 18) of the ratio of gains current sense amplifier 201 of current sense amplifier 237 is low by about 10%, makes when ACFB in delay period is than ACREF height about 10%, and operation is switched to boost mode.In one embodiment, the delay of delay block 241 in the scope of about 100-200 microsecond (μ s) to realize comparatively faster response not in response to glitch generation saltus step.Can in arrangement, this delay can be amount suitable arbitrarily.
Similarly, the gain height scheduled volume of the ratio of gains current sense amplifier 201 of current sense amplifier 243, and the output of amplifier 243 and ACREF compare by comparator 245.When boost mode, if adapter electric current I ADP reduces to reduce fast in response to load, make ACFB lower than ACREF respective amount, then comparator 245 switches and UNDER is asserted as height.If at least remain height at the duration UNDER of delay block 247, then delay block 247 triggers and resets latch 235 to drag down BOOST to switch back the state of decompression mode and no matter IN or HOLD.
In one embodiment, the gain of the ratio of gains current sense amplifier 201 of current sense amplifier 243 (such as, gain is 22) height about 10%, make when ACFB in delay period lower than ACREF about 10% time, operate and be switched to decompression mode from boost mode.In one embodiment, the delay of delay block 247 is about 100 μ s to realize comparatively faster response not in response to glitch generation saltus step.
Quick mode changes the very fast transformation that circuit 235 realizes between step-down and boost operations pattern in response to load transient faster.Delay block 241 and 247 inserts enough delay, to avoid, in response to the moment crest or load transition without the enough duration verifying switch mode, switching between step-down and boost mode.The delay of delay block 241 and 247 is enough short in realize the switching faster between pattern than adapter and battery control loop.
Reference value A CREF, CCREF, DCREF and CVREF can be fixed on predetermined level.Or one or more in reference value can be programmable.In programmable configuration, it is one or more that one or more inside or external programmable device (not shown) provide in programmable reference value.
Usually the rechargeable battery of such as battery 119 and so on is rated as and has discharging currents different compared with charging current.Such as, battery 119 can be rated as discharging current large compared with its charging current.In decompression mode, CROSSMUX213 selects CCREF to be supplied to error amplifier 215, for adjustment maximum charging current level.In boost mode, CROSSMUX213 selects DCREF to be supplied to error amplifier 215, for adjustment maximum discharge current level.If maximum charge is identical with discharging current or roughly the same, then can use single charge reference, and it is directly supplied to error amplifier 215, for adjustment maximum charge and discharging current level.
Fig. 3 draws load current ILD, adapter electric current (IADP), battery discharge current (-ICHG or IDCHG), compensatory control voltage VCTRL and BOOST signal relative to the simplification curve chart of time, and the operation of the battery charge modulator 111 according to an embodiment is shown.ILD be relative to zero (0 ampere or " 0A ") draw and tiltedly to become with constant rate of speed from 0A and rise to unlimited current level, IADP is indicated by ACFB and draws relative to ACREF,-ICHG is indicated by the CCFB drawn relative to 0A between DCREF and CCREF, COMP draws relative to HOLDTH, and BOOST is binary system or digital value, for decompression mode, it is asserted to low (or logical zero) and it is asserted to height (or logical one) for boost operations pattern.
The operation of error amplifier 217 is left in the basket or not shown, wherein supposes that battery 119 is not in its maximal voltage level.Note, when battery 119 is completely charged, amplifier 217 prevents boost mode (or only allowing minimum boost operations), to prevent the further charging of battery 119.But when load attempts to extract the more electric current of the electric current that can provide than adapter, can use boost mode, battery 119 discharges with compensating load electric current in this case.When battery 119 is not completely charged, loop controls between error amplifier 205 and 215.Graph plots is supplied to the load current ILD of system load 113, the adapter electric current I ADP indicated relative to ACREF and by ACFB, the negative charge current-ICHG by battery 119, the COMP voltage relative to HOLDTH voltage level and BOOST signal relative to CCREF (decompression mode) and DCREF (boost mode).Negative charge current-ICHG also can be called as discharging current (IDCHG).Illustrate that load current ILD is increased to high level to illustrate control operation with linear velocity from 0.Suppose that the change of ILD in this time is enough slow and not shown or ignore quick mode and change the operation of circuit 235.
At very first time t0, operation is in decompression mode, and wherein load current ILD is low or 0 ampere (A), makes the ACFB of indication adapter electric current I ADP relatively low.Because ILD is 0 or close to 0, substantially whole adapter electric currents flows through RSB to charge to battery 119.Suppose that battery 119 is not completely charged, and its voltage is fully low and absorb whole charging currents.Therefore, CCFB (charging current feedback) reaches or attempts more than CCREF (charging current reference), and error amplifier 215 control COMP is to be limited in its maximum level determined by CCREF by battery charge.After time until time t1 subsequently, when ILD increases, ACFB and ILD raises pro rata and keeps below ACREF simultaneously, and error amplifier 215 retentive control is to be limited in the maximum level determined by CCREF by charging current.Period between time t0 and t1 is the charging current restriction period.
Be elevated to ACREF (adapter current feedback) at time t1, ILD reach or begin to exceed the point of ACREF (adapter current reference).ACREF indicates maximum adaptation device current level, and make error amplifier 205 start to attempt to reduce current level, ILD continues to raise after timet simultaneously.At whenabouts t1 place, error amplifier 205 bear control with by adapter current limit at the maximum level determined by ACREF.Along with ILD continues to raise, error amplifier 205 limit adaptation device current level, makes the charging current through battery 119 start to reduce.In this way, charging current starts to reduce (or-ICHG increases), makes more electric current can be used for being supplied to the ILD of system load 113.Period after timet starts the adapter current limit period.
After timet, when ILD continues to increase, IADP keeps constant based on ACREF, and-ICHG continues to increase (charging current reduction).The level of VCTRL is reduced to the level making IADP keep the constant whole ILD level simultaneously providing system load 113 to ask.Between time t0 and time t2 subsequently, ILD remains lower than maximum adaptation device electric current, and the remaining sum of electric current is provided to battery 119 as charging current.
Maximum adaptation device electric current is reached and charging current becomes the voltage that 0VCTRL is reduced to about HOLDTH at time t2 subsequently, ILD.Along with ILD continues to raise, comparator 227 is kept to be switched to by HOLD low, to discharge the HOLD input of latch 231.ACFB higher than ACREF and latch 231 switch to assert that BOOST is for height is to initiate boost operations pattern.
Under boost operations pattern, after the time t 2, power stage 204 is switched to boost mode and battery 119 discharges that electric current is supplied to ILD.Along with ILD raise, error amplifier 205 retentive control with by adapter current limit at the maximum level determined by ACREF.Along with ILD continues to raise, error amplifier 205 regulates COMP to be operated in boost mode to control power stage 204 to increase the discharging current level of battery 119.Therefore, when IADP remains on its maximum level, VCTRL raises along with ILD and raises to increase discharging current-ICHG, thus balance of current is supplied to ILD.Adapter current limit period from time t2 to time t3 is subsequently effective, so that adapter electric current is maintained its greatest hope level.
At time t3 subsequently, the discharging current of battery 119 reaches the maximum discharge current level determined by DCREF.The maximum current level of adapter 103 and the discharging current level sum of battery 119 is reached at time t3, ILD current level.The level of ILD should not attempted to exceed this maximum current level and reach the obvious period.But if ILD increases as shown in figure after time t 3, error amplifier 215 recovers to control to prevent the discharging current from battery 119 from exceeding its maximum level indicated by DCREF.After time t 3, operation enters the discharging current restriction period, and wherein the discharging current level of battery 119 maintains the level of its maximum permission.In this way, protect battery 119 in order to avoid exceed its maximum rated discharging current level, to protect battery and/or to make fail safe optimization.
If ILD continues to increase as shown in figure after time t 3, the discharging current level of battery 119 is limited, and the electric current added is provided by adapter 103.Therefore, adapter 103 exceedes its maximum current level.Depend on the configuration of adapter 103, the system bus voltages level of VOUT can start to decline.This situation can be allowed to continue finite time, reach obvious time quantum or VOUT can not to decline significantly amount as long as adapter 103 is no more than its maximum current level.In one embodiment, ILD can be allowed to be elevated to more than adapter 103 and the maximum current level both battery 119 and to reach finite time section.If ILD continues the maximum current level higher than adapter 103 and battery 119, then fault or error condition can be detected by (not shown) such as the protective circuits of adding, and electronic equipment 109 can cut out to prevent error situation, damage or catastrophe failure.
When ILD reduces, operation is substantially similar on oppositely.The extra load electric current that battery 119 complementary adapter does not provide, and when load current reduces, discharging current reduces.When ACFB drops to lower than ACREF and VCTRL drops to lower than HOLDTH, operation switches back decompression mode.As previously mentioned, under synchronous grid controller 229 makes Q2 be operated in diode simulation model, wherein when by monitoring that the determined inductor current of VDS of Q2 drops to about 0, Q2 disconnects.In one embodiment, during decompression mode, synchronous grid controller 229 realizes minimum Q2 ON time, even if also to provide relatively little boost current level during decompression mode.This boost function is used for preventing from being too early switched to boost mode in buck mode, and minimizes or reduce the switching vibration at buck/boost switching point place.In one embodiment, CSIN can be supplied to synchronous grid controller 229 to monitor the VDS of Q1, with during boost mode according to diode simulation operations Q1.
Fig. 4 describes (and/or normalization) adapter electric current I ADP, battery charge (ICHG), VCTRL and BOOST signal relatively, in the curve chart of the relation of time, the transient response of the battery charge modulator 111 according to an embodiment to be shown.In this case, system load (such as, ILD) is increased to 5A from 3A, and ACREF is about 4A.When ILD increases, adapter electric current keeps relative constancy, and make to drop to HOLDTH in response to VCTRL, charging current is reduced to 0.BOOST signal uprises to be switched to boost mode, and continues to increase along with ILD, and VCTRL increases to increase discharging current, bears lower than indicated by 0 as ICHG becomes further.
Although described in detail the present invention with reference to some preferred version of the present invention, the version possible it is conceivable that other and modification.Those of ordinary skill in the art are to be understood that, they easily can utilize disclosed concept to design with based on specific embodiment or revise other structure to realize identical object of the present invention, and this does not deviate from the spirit and scope of the present invention be defined by the following claims.