技术领域technical field
本发明涉及通信领域，尤其涉及一种用于低频信号检测及传输系统的模拟前端装置。The invention relates to the communication field, in particular to an analog front-end device used in a low-frequency signal detection and transmission system.
背景技术Background technique
如今，已经出现了在手机中的SIM(Subscriber Identity Module，用户识别模块)卡上增加射频功能(称为射频SIM卡)或者在手机主板上增加近距离通信模块来实现手机近距离通信的方法，这种方法的出现使得手机成为一个可以充值、消费、交易及身份认证的超级智能终端，极大地满足市场的迫切需求。Nowadays, there has been a method of adding a radio frequency function (called a radio frequency SIM card) on the SIM (Subscriber Identity Module, Subscriber Identity Module) card in the mobile phone or adding a short-range communication module on the main board of the mobile phone to realize the short-distance communication of the mobile phone. The emergence of this method makes the mobile phone a super intelligent terminal that can recharge, consume, trade and authenticate, which greatly meets the urgent needs of the market.
其中，基于射频SIM的手机近距离解决方案以其简单、无需更改手机等优势得到广泛的关注，在该方案中，射频SIM采用UHF(Ultra HighFrequency，超高频)等技术使得射频SIM卡嵌入在手机内部时射频信号仍然可以从手机中透射出来，从而实现不必对现有的手机进行任何结构改变就可使得手机具备近距离通信功能。但是，不同手机由于内部结构不同造成射频信号透射效果存在很大的差异，透射强的手机其射频SIM卡射频通信距离可能达到几米远的距离，透射弱的手机其射频SIM卡通信距离也可以达到几十厘米。在移动支付应用中，如公交地铁刷卡，通常都会对于交易距离有严格的要求以确保交易的安全，例如交易距离要求限制在10cm以下，以防止用户在不知情的情况下误刷，造成损失；另一方面，还要求在规定距离以下保证通信的可靠性，以提高交易的效率。因此，基于射频SIM的手机在增加近距离通信功能的同时，还必须能够有效控制其交易的距离范围。Among them, the mobile phone short-distance solution based on radio frequency SIM has attracted wide attention due to its simplicity and the advantages of not needing to change the mobile phone. When the mobile phone is inside, the radio frequency signal can still be transmitted from the mobile phone, so that the mobile phone can be provided with the short-distance communication function without making any structural changes to the existing mobile phone. However, due to the different internal structures of different mobile phones, there are great differences in the radio frequency signal transmission effect. The radio frequency communication distance of the radio frequency SIM card of the mobile phone with strong transmission may reach a distance of several meters, and the communication distance of the radio frequency SIM card of the mobile phone with weak transmission can also reach tens of centimeters. In mobile payment applications, such as swiping cards in buses and subways, there are usually strict requirements on the transaction distance to ensure the security of the transaction. For example, the transaction distance is limited to less than 10cm to prevent users from swiping by mistake without knowing it and causing losses; On the other hand, it is also required to ensure the reliability of communication below the specified distance to improve the efficiency of transactions. Therefore, the mobile phone based on radio frequency SIM must be able to effectively control the distance range of its transactions while increasing the short-range communication function.
因此又提出了一种低频交变磁场近距离通讯结合RF高频通讯的系统和方法，解决了上述问题。该系统利用低频交变磁场实现距离检测和控制，并实现读卡器和卡的单向通讯，利用RF通道结合低频通讯实现终端的可靠绑定，同时利用RF通道实现读卡器和卡之间高速的数据通讯。但是，该方案中，低频信号检测及传输系统(处于卡的一方)中所接收到的低频信号夹杂着电路噪声和环境噪声，影响了距离检测和控制的精度，因此，如何有效地减小电路噪声和环境噪声对低频信号的干扰成为目前亟待解决的问题之一。Therefore, a system and method for low-frequency alternating magnetic field short-distance communication combined with RF high-frequency communication is proposed to solve the above-mentioned problems. The system uses low-frequency alternating magnetic field to realize distance detection and control, and realizes one-way communication between card reader and card, uses RF channel combined with low-frequency communication to realize reliable binding of terminals, and uses RF channel to realize communication between card reader and card High-speed data communication. However, in this scheme, the low-frequency signal received in the low-frequency signal detection and transmission system (on the side of the card) is mixed with circuit noise and environmental noise, which affects the accuracy of distance detection and control. Therefore, how to effectively reduce the circuit The interference of noise and environmental noise to low-frequency signals has become one of the problems to be solved urgently.
发明内容Contents of the invention
本发明所要解决的技术问题是提供一种用于低频信号检测及传输系统的模拟前端装置，减小电路噪声和环境噪声对低频信号检测及传输系统中所接收到的低频信号的干扰，提高低频交变磁场距离检测和控制的精度。The technical problem to be solved by the present invention is to provide an analog front-end device for low-frequency signal detection and transmission system, reduce the interference of circuit noise and environmental noise to the low-frequency signal received in the low-frequency signal detection and transmission system, and improve the low-frequency Alternating magnetic field distance detection and control accuracy.
为解决上述技术问题，本发明提出了一种用于低频信号检测及传输系统的模拟前端装置，应用于近距离通信系统，包括至少一个磁感应模块、至少一个低通滤波模块、至少一个放大器、至少一个数字/模拟转换器和至少一个比较器，所述磁感应模块、低通滤波模块、放大器顺次相连，所述放大器的输出端与所述比较器的正向输入端相连，所述数字/模拟转换器的输出端与所述比较器的反向输入端相连，所述放大器为双端输入单端输出放大器。In order to solve the above technical problems, the present invention proposes an analog front-end device for low-frequency signal detection and transmission systems, which is applied to short-distance communication systems, including at least one magnetic induction module, at least one low-pass filter module, at least one amplifier, at least A digital/analog converter and at least one comparator, the magnetic induction module, the low-pass filter module, and the amplifier are connected in sequence, the output terminal of the amplifier is connected with the positive input terminal of the comparator, and the digital/analog The output end of the converter is connected with the inverting input end of the comparator, and the amplifier is a double-end input single-end output amplifier.
进一步地，上述装置还可具有以下特点，包括一个磁感应模块、一个低通滤波模块、一个放大器、两个数字/模拟转换器和两个比较器，所述磁感应模块、低通滤波模块、放大器顺次相连，所述放大器的输出端分别与所述两个比较器的正向输入端相连，所述两个数字/模拟转换器与所述两个比较器组成两路，每一路中数字/模拟转换器的输出端与比较器的反向输入端相连，每上下两路组成一对，共一对。Further, the above-mentioned device may also have the following characteristics, including a magnetic induction module, a low-pass filter module, an amplifier, two digital/analog converters and two comparators, the magnetic induction module, the low-pass filter module, the amplifier and The output terminals of the amplifier are respectively connected to the positive input terminals of the two comparators, and the two digital/analog converters form two paths with the two comparators, and the digital/analog The output terminal of the converter is connected with the inverting input terminal of the comparator, and each upper and lower circuit forms a pair, a total of one pair.
进一步地，上述装置还可具有以下特点，包括一个磁感应模块、一个低通滤波模块、一个放大器、六个数字/模拟转换器和六个比较器，所述放大器的输出端分别与所述六个比较器的正向输入端相连，所述六个数字/模拟转换器与所述六个比较器组成六路，每一路中数字/模拟转换器的输出端与比较器的反向输入端相连，每上下两路组成一对，共三对。Further, the above-mentioned device may also have the following characteristics, including a magnetic induction module, a low-pass filter module, an amplifier, six digital/analog converters and six comparators, and the output terminals of the amplifier are respectively connected to the six The positive input terminals of the comparators are connected, and the six digital/analog converters form six circuits with the six comparators, and the output terminals of the digital/analog converters in each circuit are connected with the inverting input terminals of the comparators, and each The upper and lower sides form a pair, a total of three pairs.
进一步地，上述装置还可具有以下特点，所述磁感应模块为磁感应线圈、霍尔器件或巨磁阻器件。Further, the above-mentioned device may also have the following characteristics, the magnetic induction module is a magnetic induction coil, a Hall device or a giant magnetoresistance device.
进一步地，上述装置还可具有以下特点，所述磁感应模块为磁感应线圈，所述磁感应线圈的两输出端直接与所述低通滤波模块的两输入端相连。Furthermore, the above-mentioned device may also have the following features, the magnetic induction module is a magnetic induction coil, and the two output terminals of the magnetic induction coil are directly connected to the two input terminals of the low-pass filter module.
进一步地，上述装置还可具有以下特点，所述磁感应模块为霍尔器件，所述霍尔器件的两个输出端通过隔直电容与所述低通滤波模块两个输入端相连；或者所述霍尔器件一个输出端通过隔直电容与所述低通滤波模块一个输入端相连，而所述霍尔器件的另一个输出端直接与低通滤波模块另一个输入端相连；或者所述霍尔器件的两个输出端直接与所述低通滤波模块的两个输入端相连。Further, the above-mentioned device can also have the following features, the magnetic induction module is a Hall device, and the two output terminals of the Hall device are connected to the two input terminals of the low-pass filter module through a DC blocking capacitor; or the One output terminal of the Hall device is connected to one input terminal of the low-pass filter module through a DC blocking capacitor, and the other output terminal of the Hall device is directly connected to the other input terminal of the low-pass filter module; or the Hall device The two output terminals of the device are directly connected with the two input terminals of the low-pass filtering module.
进一步地，上述装置还可具有以下特点，所述磁感应模块为巨磁阻器件，所述巨磁阻器件的两个输出端通过隔直电容与所述低通滤波模块的两个输入端相连；或者所述巨磁阻器件的一个输出端通过隔直电容与所述低通滤波模块的一个输入端相连，而所述巨磁阻器件的另一个输出端直接与所述低通滤波模块的另一个输入端相连；或者所述巨磁阻器件的两个输出端直接与所述低通滤波模块的两个输入端相连。Further, the above-mentioned device may also have the following features, the magnetic induction module is a giant magnetoresistance device, and the two output terminals of the giant magnetoresistance device are connected to the two input terminals of the low-pass filter module through a DC blocking capacitor; Or an output end of the giant magnetoresistance device is connected to an input end of the low-pass filter module through a DC blocking capacitor, and the other output end of the giant magnetoresistance device is directly connected to another input end of the low-pass filter module. One input terminal is connected; or the two output terminals of the giant magnetoresistive device are directly connected with the two input terminals of the low-pass filter module.
进一步地，上述装置还可具有以下特点，所述放大器为接成电阻负反馈网络的单级放大器或多级级联放大器。Furthermore, the above-mentioned device may also have the following characteristics, the amplifier is a single-stage amplifier or a multi-stage cascaded amplifier connected into a resistor negative feedback network.
进一步地，上述装置还可具有以下特点，所述放大器为四级级联放大器，该四级级联放大器的组成为：Further, the above-mentioned device can also have the following characteristics, the amplifier is a four-stage cascaded amplifier, and the composition of the four-stage cascaded amplifier is:
第一级包括第一双端输入单端输出放大器、电阻Ra1和电阻Rb1；电阻Ra1的一端接信号输入端口IN，另一端接所述第一双端输入单端输出放大器的反向输入端，电阻Rb1接在所述第一双端输入单端输出放大器的反向输入端和输出端之间，所述第一双端输入单端输出放大器的同向输入端接共模电压VCM；The first stage includes a first double-ended input single-ended output amplifier, a resistor Ra1 and a resistor Rb1 ; one end of the resistor Ra1 is connected to the signal input port IN, and the other end is connected to the reverse direction of the first double-ended input single-ended output amplifier. The input terminal, the resistance Rb1 is connected between the inverting input terminal and the output terminal of the first double-ended input single-ended output amplifier, and the same direction input terminal of the first double-ended input single-ended output amplifier is connected to the common mode voltage VCM;
第二级包括第二双端输入单端输出放大器、电阻Ra2、电阻Rb2、电阻Rc1、电阻Rc2、电容C1和电容C2；电阻Ra2和电阻Rb2顺次串联在共模电压VCM和所述第二双端输入单端输出放大器的输出端之间，电阻Ra2和电阻Rb2的接点接所述第二双端输入单端输出放大器的反向输入端，电阻Rc1和电容C1顺次串联在所述第一双端输入单端输出放大器的输出端和地GND之间，电容C2和电阻Rc2顺次串联在电阻Rc1和电容C1的接点与共模电压VCM之间，电容C2和电阻Rc2的接点接所述第二双端输入单端输出放大器的同向输入端；The second stage includes a second double-ended input single-ended output amplifier, resistor Ra2 , resistor Rb2 , resistor Rc1 , resistor Rc2 , capacitor C1 and capacitor C2 ; resistor Ra2 and resistor Rb2 are serially connected in series Between the analog voltage VCM and the output terminal of the second double-ended input single-ended output amplifier, the junction of the resistor Ra2 and the resistor Rb2 is connected to the reverse input terminal of the second double-ended input single-ended output amplifier, and the resistor Rc1 and capacitorC1 are serially connected between the output terminal of the first double-ended input and single-ended output amplifier and ground GND, and capacitorC2 and resistorRc2 are serially connected between the junction of resistorRc1 and capacitorC1 and the common Between the mold voltage VCM, the contact of the capacitorC2 and the resistorRc2 is connected to the same input terminal of the second double-ended input single-ended output amplifier;
第三级包括第三双端输入单端输出放大器、电阻Ra3、电阻Rb3、电阻Rc3、电阻Rc4、电容C3和电容C4；电阻Ra3和电阻Rb3顺次串联在共模电压VCM和所述第三双端输入单端输出放大器的输出端之间，电阻Ra3和电阻Rb3的接点接所述第三双端输入单端输出放大器的反向输入端，电阻Rc3和电容C3顺次串联在所述第二双端输入单端输出放大器的输出端和地GND之间，电容C4和电阻Rc4顺次串联在电阻Rc3和电容C3的接点与共模电压VCM之间，电容C4和电阻Rc4的接点接所述第三双端输入单端输出放大器的同向输入端；The third stage includes a third double-ended input single-ended output amplifier, resistor Ra3 , resistor Rb3 , resistor Rc3 , resistor Rc4 , capacitor C3 and capacitor C4 ; resistor Ra3 and resistor Rb3 are serially connected in series Between the analog voltage VCM and the output terminal of the third double-ended input single-ended output amplifier, the junction of the resistor Ra3 and the resistor Rb3 is connected to the reverse input terminal of the third double-ended input single-ended output amplifier, and the resistor Rc3 and capacitor C3 are serially connected between the output terminalof the second double-ended input and single-ended output amplifier and ground GND, and capacitorC4 and resistorRc4 are serially connected between the junctionof resistorRc3 and capacitor C3 and the common Between the mold voltage VCM, the contact of the capacitorC4 and the resistorRc4 is connected to the same input terminal of the third double-ended input single-ended output amplifier;
第四级包括第四放大器、电容C5和电阻Rc5；电容C5和电阻Rc5顺次串联在所述第三双端输入单端输出放大器的输出端和共模电压VCM之间，电容C5和电阻Rc5的接点接所述第四放大器的同向输入端，所述第四放大器的反向输入端和输出端相连。The fourth stage includes a fourth amplifier, a capacitorC5 and a resistorRc5 ; the capacitorC5 and the resistorRc5 are serially connected in series between the output terminal of the third double-ended input single-ended output amplifier and the common mode voltage VCM, and the capacitor The junction ofC5 and resistorRc5 is connected to the non-inverting input end of the fourth amplifier, and the inverting input end of the fourth amplifier is connected to the output end.
进一步地，上述装置还可具有以下特点，所述放大器为四级级联放大器，该四级级联放大器的组成为：Further, the above-mentioned device can also have the following characteristics, the amplifier is a four-stage cascaded amplifier, and the composition of the four-stage cascaded amplifier is:
第一级包括第一双端输入单端输出放大器、电阻Ra1、电阻Rb1和电容C1；电阻Ra1接在信号输入端IN和所述第一双端输入单端输出放大器的反向输入端之间，电阻Rb1和电容C1并联在所述第一双端输入单端输出放大器的反向输入端和输出端之间，所述第一双端输入单端输出放大器的同向输入端接共模电压VCM；The first stage includes a first double-ended input single-ended output amplifier, a resistor Ra1 , a resistor Rb1 and a capacitor C1 ; the resistor Ra1 is connected to the signal input terminal IN and the opposite direction of the first double-ended input single-ended output amplifier Between the input terminals, resistance Rb1 and capacitorC1 are connected in parallel between the inverting input terminal and the output terminal of the first double-ended input single-ended output amplifier, and the same direction of the first double-ended input single-ended output amplifier The input terminal is connected to the common mode voltage VCM;
第二级包括第二双端输入单端输出放大器、电阻Ra2、电阻Rb2、电阻Rc2、电容C2和电容C3；电阻Ra2接在共模电压VCM和所述第二双端输入单端输出放大器的反向输入端之间，电阻Rb2和电容C3并联在所述第二双端输入单端输出放大器的反向输入端和输出端之间，电容C2和电阻Rc2顺次串联在所述第一双端输入单端输出放大器的输出端和共模电压VCM之间，电容C2和电阻Rc2的接点接所述第二双端输入单端输出放大器的同向输入端；The second stage includes a second double-ended input single-ended output amplifier, resistor Ra2 , resistor Rb2 , resistor Rc2 , capacitor C2 and capacitor C3 ; resistor Ra2 is connected to the common-mode voltage VCM and the second double-ended Between the inverting input terminal of the input single-ended output amplifier, resistor Rb2 and capacitor C3 are connected in parallel between the inverting input terminal and the output terminal of the second double-ended input single-ended output amplifier, capacitor C2 and resistor Rc2 is serially connected in series between the output terminal of the first double-ended input single-ended output amplifier and the common mode voltage VCM, and the junction of the capacitorC2 and the resistor Rc2 is connected to the same point of the second double-ended input single-ended output amplifier. to the input;
第三级包括第三双端输入单端输出放大器、电阻Ra3、电阻Rb3、电阻Rc4和电容C4；电阻Ra3和电阻Rb32顺次串联在共模电压VCM和所述第三双端输入单端输出放大器的输出端之间，电阻Ra3和电阻Rb32的接点接所述第三双端输入单端输出放大器的反向输入端，电容C4和电阻Rc4顺次串联在所述第二双端输入单端输出放大器的输出端和共模电压VCM之间，电容C4和电阻Rc4的接点接所述第三双端输入单端输出放大器的同向输入端；The third stage includes a third double-ended input single-ended output amplifier, a resistor Ra3 , a resistor Rb3 , a resistor Rc4 and a capacitor C4 ; the resistor Ra3 and the resistor Rb32 are connected in series between the common mode voltage VCM and the third Between the output ends of the double-ended input single-ended output amplifier, the contact of the resistor Ra3 and the resistor Rb32 is connected to the reverse input end of the third double-ended input single-ended output amplifier, and the capacitorC4 and the resistorRc4 are connected in series Between the output terminal of the second double-ended input and single-ended output amplifier and the common mode voltage VCM, the contact of the capacitorC4 and the resistorRc4 is connected to the same input terminal of the third double-ended input and single-ended output amplifier;
第四级包括第四放大器、电阻Rc5和电容C5；电容C5和电阻Rc5顺次串联在所述第三双端输入单端输出放大器的输出端和共模电压VCM之间，电容C5和电阻Rc5的接点接所述第四放大器的同向输入端，所述第四放大器的反向输入端和输出端相连。The fourth stage includes a fourth amplifier, a resistorRc5 and a capacitorC5 ; the capacitorC5 and the resistorRc5 are serially connected in series between the output terminal of the third double-ended input single-ended output amplifier and the common mode voltage VCM, and the capacitor The junction ofC5 and resistorRc5 is connected to the non-inverting input end of the fourth amplifier, and the inverting input end of the fourth amplifier is connected to the output end.
进一步地，上述装置还可具有以下特点，所述放大器为四级级联放大器，该四级级联放大器的组成为：Further, the above-mentioned device can also have the following characteristics, the amplifier is a four-stage cascaded amplifier, and the composition of the four-stage cascaded amplifier is:
第一级包括第一放大器、电阻Ra1、电阻Rb1、电阻Ra11和电阻Rb11；电阻Ra1和电阻Rb1顺次串联在正向信号输入端INP和所述第一放大器的输出端之间，电阻Ra1和电阻Rb1的接点接所述第一放大器的反向输入端，电阻Ra11和电阻Rb11顺次串联在反向信号输入端INN和地GND之间，电阻Ra11和电阻Rb11的接点接所述第一放大器的同向输入端；The first stage includes a first amplifier, a resistor Ra1 , a resistor Rb1 , a resistor Ra11 and a resistor Rb11 ; the resistor Ra1 and the resistor Rb1 are serially connected in series at the forward signal input terminal INP and the output terminal of the first amplifier Between, the junction of resistor Ra1 and resistor Rb1 is connected to the reverse input terminal of the first amplifier, resistor Ra11 and resistor Rb11 are serially connected in series between the reverse signal input terminal INN and ground GND, resistor Ra11 The junction of the resistor Rb11 is connected to the same input terminal of the first amplifier;
第二级包括第二双端输入单端输出放大器、电阻Ra2、电阻Rb2、电阻Rc1、电阻Rc2、电容C1和电容C2；电阻Ra2、电阻Rb2顺次串联在共模电压VCM和所述第二双端输入单端输出放大器的输出端之间，电阻Ra2、电阻Rb2的接点接所述第二双端输入单端输出放大器的反向输入端，电阻Rc1、电容C1顺次串联在所述第一放大器的输出端和地GND之间，电容C2和电阻Rc2顺次串联在电阻Rc1、电容C1的接点与共模电压VCM之间，电容C2和电阻Rc2的接点接所述第二双端输入单端输出放大器的同向输入端；The second stage includes a second double-ended input and single-ended output amplifier, resistor Ra2 , resistor Rb2 , resistor Rc1 , resistor Rc2 , capacitor C1 and capacitor C2 ; resistor Ra2 and resistor Rb2 are serially connected in series Between the analog voltage VCM and the output end of the second double-ended input single-ended output amplifier, the junction of the resistor Ra2 and the resistor Rb2 is connected to the reverse input end of the second double-ended input single-ended output amplifier, and the resistor Rc1 and capacitorC1 are sequentially connected in series between the output terminal of the first amplifier and ground GND, and capacitorC2 and resistorRc2 are sequentially connected in series between the junction of resistorRc1 and capacitorC1 and the common-mode voltage VCM, The junction of the capacitorC2 and the resistorRc2 is connected to the same input terminal of the second double-ended input and single-ended output amplifier;
第三级包括第三双端输入单端输出放大器、电阻Ra3、电阻Rb3、电阻Rc3、电阻Rc4、电容C3和电容C4；电阻Ra3和电阻Rb3顺次串联在共模电压VCM和所述第三双端输入单端输出放大器的输出端之间，电阻Ra3和电阻接点接所述第三双端输入单端输出放大器的反向输入端，电阻Rc3和电容C3顺次串联在所述第二双端输入单端输出放大器的输出端和地GND之间，电容C4和电阻Rc4顺次串联在电阻Rc3和电容C3的接点与共模电压VCM之间，电容C4和电阻Rc4的接点接所述第三双端输入单端输出放大器的同向输入端；The third stage includes a third double-ended input single-ended output amplifier, resistor Ra3 , resistor Rb3 , resistor Rc3 , resistor Rc4 , capacitor C3 and capacitor C4 ; resistor Ra3 and resistor Rb3 are serially connected in series Between the analog voltage VCM and the output terminal of the third double-ended input single-ended output amplifier, the resistor Ra3 and the resistance contact are connected to the reverse input terminal of the third double-ended input single-ended output amplifier, and the resistor Rc3 and the capacitor C3 is serially connected between the output terminal of the second double-ended input single-ended output amplifier and ground GND, and capacitor C4 and resistor Rc4 are serially connected between the junction of resistor Rc3 and capacitor C3 and the common mode voltage VCM Between, the junction of capacitorC4 and resistorRc4 is connected to the same input terminal of the third double-ended input and single-ended output amplifier;
第四级包括第四放大器、电阻Rc5和电容C5；电容C5和电阻Rc5顺次串联在所述第三双端输入单端输出放大器的输出端和共模电压VCM之间，电容C5和电阻Rc5的接点接所述第四放大器的同向输入端，所述第四放大器的反向输入端和输出端相连。The fourth stage includes a fourth amplifier, a resistorRc5 and a capacitorC5 ; the capacitorC5 and the resistorRc5 are serially connected in series between the output terminal of the third double-ended input single-ended output amplifier and the common mode voltage VCM, and the capacitor The junction ofC5 and resistorRc5 is connected to the non-inverting input end of the fourth amplifier, and the inverting input end of the fourth amplifier is connected to the output end.
进一步地，上述装置还可具有以下特点，所述数字/模拟转换器为电流模式R2R结构，所述数字/模拟转换器的输出范围最大为二分之一电源地电压。Further, the above-mentioned device may also have the following features, the digital/analog converter is a current mode R2R structure, and the output range of the digital/analog converter is at most half the voltage of the power supply ground.
进一步地，上述装置还可具有以下特点，所述数字/模拟转换器为电流模式R2R结构，所述数字/模拟转换器的输出范围不局限于二分之一电源地电压，并且共模电平可调节。Further, the above-mentioned device can also have the following features, the digital/analog converter is a current mode R2R structure, the output range of the digital/analog converter is not limited to half the power supply ground voltage, and the common mode level adjustable.
进一步地，上述装置还可具有以下特点，所述数字/模拟转换器为电压模式R2R结构，所述数字/模拟转换器的输出范围不局限于二分之一电源地电压。Further, the above-mentioned device may also have the following features, the digital/analog converter is a voltage mode R2R structure, and the output range of the digital/analog converter is not limited to half the power supply ground voltage.
进一步地，上述装置还可具有以下特点，所述数字/模拟转换器为R2R网络结构，所述数字/模拟转换器的输出范围大至电源地电压。Further, the above-mentioned device may also have the following features, the digital/analog converter has an R2R network structure, and the output range of the digital/analog converter is as large as the power supply ground voltage.
进一步地，上述装置还可具有以下特点，用于比较高电平的比较器包括三个NMOS管Mn0、Mn1、Mn2和两个PMOS管Mp1、Mp2，以及一个反向器，PMOS管Mp1和PMOS管Mp2的栅极相连，源极均接电源Vcc，PMOS管Mp1的漏极接NMOS管Mn1的漏极，NMOS管Mn 1和NMOS管Mn2的源极均接NMOS管Mn0的漏极，NMOS管Mn2的漏极接PMOS管Mp2的漏极，NMOS管Mn0的源极接地GND，栅极接偏置电压Vbn，反向器的输入端接PMOS管Mp2的漏极，NMOS管Mn2的栅极为比较器的正向输入端Vin+，NMOS管Mn1的栅极为比较器的反向输入端Vin-，反向器的输出端为比较器的输出端Vo。Further, the above-mentioned device can also have the following characteristics, the comparator for comparing high levels includes three NMOS transistors Mn0, Mn1, Mn2 and two PMOS transistors Mp1, Mp2, and an inverter, PMOS transistor Mp1 and PMOS transistor Mp1 The gate of the tube Mp2 is connected, the source is connected to the power supply Vcc, the drain of the PMOS tube Mp1 is connected to the drain of the NMOS tube Mn1, the sources of the NMOS tube Mn1 and the NMOS tube Mn2 are connected to the drain of the NMOS tube Mn0, and the NMOS tube The drain of Mn2 is connected to the drain of PMOS transistor Mp2, the source of NMOS transistor Mn0 is grounded to GND, the gate is connected to bias voltage Vbn, the input terminal of the inverter is connected to the drain of PMOS transistor Mp2, and the gate of NMOS transistor Mn2 is a comparison The positive input terminal Vin+ of the comparator, the gate of the NMOS transistor Mn1 is the negative input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal Vo of the comparator.
进一步地，上述装置还可具有以下特点，用于比较低电平的比较器包括三个PMOS管Mp0、Mp3、Mp4和两个NMOS管Mn3、Mn4以及一个反向器，PMOS管Mp0的源极接电源Vcc，栅极接偏置电压Vbp，漏极接PMOS管Mp3和PMOS管Mp4的源极，PMOS管Mp3的漏极接NMOS管Mn3的漏极和栅极，NMOS管Mn3和NMOS管Mn4的源极接地GND，NMOS管Mn4的漏极接PMOS管Mp4的漏极，反向器的输入端接NMOS管Mn4的漏极，PMOS管Mp4的栅极为比较器的正向输入端Vin+，PMOS管Mp3的栅极为比较器的反向输入端Vin-，反向器的输出端为比较器的输出端Vo。Further, the above-mentioned device can also have the following characteristics, the comparator for comparing the low level includes three PMOS transistors Mp0, Mp3, Mp4 and two NMOS transistors Mn3, Mn4 and an inverter, the source of the PMOS transistor Mp0 Connect to power supply Vcc, gate to bias voltage Vbp, drain to source of PMOS transistor Mp3 and PMOS transistor Mp4, drain of PMOS transistor Mp3 to drain and gate of NMOS transistor Mn3, NMOS transistor Mn3 and NMOS transistor Mn4 The source of the NMOS transistor Mn4 is connected to the drain of the PMOS transistor Mp4, the input terminal of the inverter is connected to the drain of the NMOS transistor Mn4, and the gate of the PMOS transistor Mp4 is the positive input terminal Vin+ of the comparator. The gate of the tube Mp3 is the inverting input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal Vo of the comparator.
进一步地，上述装置还可具有以下特点，所述放大器的偏置电压产生电路包括2级低压差线性稳压器。Furthermore, the above-mentioned device may also have the following features, the bias voltage generating circuit of the amplifier includes a two-stage low-dropout linear regulator.
为解决上述技术问题，本发明还提出了一种低频信号检测方法，基于上述的用于低频信号检测及传输系统的模拟前端装置，包括：In order to solve the above-mentioned technical problems, the present invention also proposes a low-frequency signal detection method based on the above-mentioned analog front-end device for low-frequency signal detection and transmission system, including:
步骤a，通过实验，测量磁感应模块与发送低频磁场的读卡器在不同距离点的感应电压经放大器放大后的电压幅值，确定该电压幅值与距离的对应关系，并建立电压幅值与距离的对应表；Step a, through experiments, measure the voltage amplitude of the induced voltage of the magnetic induction module and the card reader sending the low-frequency magnetic field at different distance points after being amplified by the amplifier, determine the corresponding relationship between the voltage amplitude and the distance, and establish the relationship between the voltage amplitude and the distance Correspondence table of distance;
步骤b，根据解码低频信号传输数据及控制刷卡距离的需要，结合信噪比要求，通过一对或多对数模转换器输出的双电平门限形成迟滞判决电压门限对模拟信号进行判决，得到低频磁场所传输的码流信息，或者通过一个或多个数模转换器输出的单电平门限形成判决电压门限对模拟信号进行判决，得到低频磁场所传输的码流信息；通过一对或多对数模转换器输出的双电平门限形成非迟滞判决电压门限对模拟信号进行判决，得到低频磁场所传递的距离特征信息，或者通过一个或多个数模转换器输出的单电平门限形成非迟滞判决电压门限对模拟信号进行判决，得到低频磁场所传递的距离特征信息；Step b, according to the needs of decoding low-frequency signal transmission data and controlling the distance of swiping cards, combined with the requirements of signal-to-noise ratio, the analog signal is judged by forming a hysteresis judgment voltage threshold through the dual-level thresholds output by one or more pairs of digital-to-analog converters, and the result is The code stream information transmitted by the low-frequency magnetic field, or through the single-level threshold output by one or more digital-to-analog converters to form a decision voltage threshold to judge the analog signal, and obtain the code stream information transmitted by the low-frequency magnetic field; The non-hysteretic judgment voltage threshold is formed by the double-level threshold output by the digital-to-analog converter, and the analog signal is judged to obtain the distance characteristic information transmitted by the low-frequency magnetic field, or formed by the single-level threshold output by one or more digital-to-analog converters. The non-hysteretic judgment voltage threshold judges the analog signal and obtains the distance characteristic information transmitted by the low-frequency magnetic field;
步骤c，对非迟滞判决条件判决后信号进行采样，得到0、1码流序列，设置1信号比例门限，在设定的时间窗长度内对该码流序列进行统计，当1信号所占码流序列比例达到预设比例门限时，则认为进入预设距离范围，否则认为未进入该距离范围；对迟滞判决条件判决后的信号序列进行解码，提取低频磁场的码流信息，完成低频磁场信号单向通信。Step c: Sampling the signal after the judgment of the non-delay judgment condition to obtain the 0 and 1 code stream sequence, set the ratio threshold of the 1 signal, and make statistics on the code stream sequence within the set time window length, when the code stream sequence occupied by the 1 signal When the flow sequence ratio reaches the preset ratio threshold, it is considered to have entered the preset distance range, otherwise it is considered not to have entered the distance range; the signal sequence after the judgment of the hysteresis judgment condition is decoded, the code stream information of the low-frequency magnetic field is extracted, and the low-frequency magnetic field signal is completed. One-way communication.
进一步地，上述方法还可具有以下特点，所述步骤b中，根据步骤a中所述电压幅值与距离的对应表，结合解码距离、距离控制的要求、设置1信号的比例门限设置数模转换器输出给比较器的电平。Further, the above method can also have the following characteristics, in the step b, according to the correspondence table between the voltage amplitude and the distance described in the step a, combined with the decoding distance, the distance control requirements, and the ratio threshold of setting 1 signal, the digital-analog Converter output level to the comparator.
进一步地，上述方法还可具有以下特点，所述成对数模转换器输出给比较器的电平为非迟滞判决条件，其设置方法为：设期望控制的距离为D1，查找电压幅值与距离的对应表，得到距离D1对应的信号变化幅度为+A1到-A1，设置1信号的比例门限为R1，根据A1及R1，设置输出给比较器的电平L1、L2，满足在一个周期内，模拟前端装置输出信号幅度大于L1或小于L2的时间百分比等于R1，即大于R1则进入要求控制的距离D1范围内，否则没有进入要求控制距离D1的范围内。Further, the above method can also have the following characteristics, the level output from the paired digital-to-analog converter to the comparator is a non-hysteretic decision condition, and the setting method is as follows: set the distance of the desired control as D1, and search for the voltage amplitude and According to the distance correspondence table, the range of signal change corresponding to the distance D1 is +A1 to -A1, and the proportional threshold of the 1 signal is set to R1. According to A1 and R1, set the output levels L1 and L2 to the comparator to meet the requirements in one cycle Within, the percentage of time when the output signal amplitude of the analog front-end device is greater than L1 or less than L2 is equal to R1, that is, if it is greater than R1, it will enter the range of the required control distance D1, otherwise it will not enter the range of the required control distance D1.
进一步地，上述方法还可具有以下特点，所述成对数模转换器输出给比较器的电平为迟滞判决条件，其设置方法为：设期望进行解码的距离为D2，查找电压幅值与距离的对应表，得到距离D2对应信号的变化幅度为+A2到-A2，测得大多数噪声产生的幅度为A3，设置输出给比较器的电平L3、L4，使得L3大于+A3且小于+A2；L4小于-A3且大于-A2，即当距离小于D2时则允许解码，否则不允许解码。Further, the above method can also have the following characteristics, the level output by the paired digital-to-analog converter to the comparator is a hysteresis decision condition, and the setting method is: set the desired decoding distance as D2, and search for the voltage amplitude and According to the corresponding table of distances, the change range of the signal corresponding to the distance D2 is +A2 to -A2, and the measured range of most noises is A3, and the levels L3 and L4 output to the comparator are set so that L3 is greater than +A3 and less than +A2; L4 is less than -A3 and greater than -A2, that is, when the distance is less than D2, decoding is allowed, otherwise decoding is not allowed.
进一步地，上述方法还可具有以下特点，所述步骤b中，对输入为非迟滞判决条件比较电平的两个比较器输出信号进行逻辑或处理，得到用于提取距离信息的数字信号。Furthermore, the above method may also have the following features, in the step b, the logical OR processing is performed on the output signals of the two comparators whose input is the comparison level of the non-hysteretic decision condition, to obtain a digital signal for extracting the distance information.
进一步地，上述方法还可具有以下特点，所述步骤b中，对输入为迟滞判决条件比较电平的两个比较器输出进行迟滞处理，得到用于提取磁场码流信息的数字信号。Further, the above method may also have the following features, in the step b, perform hysteresis processing on the outputs of the two comparators whose input is the comparison level of the hysteresis decision condition, to obtain a digital signal for extracting magnetic field code stream information.
进一步地，上述方法还可具有以下特点，所述步骤c中，设置数字毛刺滤波器对输入的数字信号进行毛刺滤除，从滤除毛刺的信号中解码出低频磁场数据流。Further, the above-mentioned method may also have the following features, in the step c, a digital glitch filter is set to filter the input digital signal, and the low-frequency magnetic field data stream is decoded from the glitch-filtered signal.
进一步地，上述方法还可具有以下特点，所述步骤b中，使用单个数模转换器输出单比较电平提取磁场距离信息和码流信息。Furthermore, the above-mentioned method may also have the following characteristics, in the step b, a single digital-to-analog converter is used to output a single comparison level to extract the magnetic field distance information and the code stream information.
进一步地，上述方法还可具有以下特点，使用单个比较器输出比较电平提取磁场码流信息，数模转换器输出给比较器的电平设置为放大器输入参考电平。Further, the above method may also have the following features, using a single comparator output comparison level to extract the magnetic field code stream information, and the level output from the digital-to-analog converter to the comparator is set as the input reference level of the amplifier.
进一步地，上述方法还可具有以下特点，使用单个比较器或成对比较器输出的数字信号进行解码。Furthermore, the above-mentioned method may also have the following feature, using the digital signal output by a single comparator or a pair of comparators for decoding.
进一步地，上述方法还可具有以下特点，使用单比较器或成对比较器输出的数字信号进行单个距离的判断；使用多个单比较器输出的数字信号进行多个距离的判断，或者使用多个成对比较器进行多个距离、多个距离区间的判断；使用多个单比较器输出的数字信号进行多个距离的判断，或者使用多个成对比较器进行多个距离、多个距离区间的判断。Further, the above-mentioned method can also have the following features, use the digital signal output by a single comparator or a pair of comparators to judge a single distance; use the digital signal output by multiple single comparators to judge multiple distances, or use multiple A pair of comparators to judge multiple distances and multiple distance intervals; use multiple single comparator output digital signals to judge multiple distances, or use multiple paired comparators to judge multiple distances and multiple distances Interval judgment.
进一步地，上述方法还可具有以下特点，混合使用多个单比较器和成对比较器输出的数字信号进行多个距离、多个距离区间的判断。Furthermore, the above-mentioned method may also have the following characteristics: the digital signals output by multiple single comparators and paired comparators are used in combination to judge multiple distances and multiple distance intervals.
本发明能够减小电路噪声和环境噪声对低频信号检测及传输系统中所接收到的低频信号的干扰，从而提高低频交变磁场距离检测和控制的精度。The invention can reduce the interference of circuit noise and environmental noise to the low frequency signal received in the low frequency signal detection and transmission system, thereby improving the precision of low frequency alternating magnetic field distance detection and control.
附图说明Description of drawings
图1为本发明实施例用于低频信号检测及传输系统的模拟前端装置的一种结构图；FIG. 1 is a structural diagram of an analog front-end device used in a low-frequency signal detection and transmission system according to an embodiment of the present invention;
图2为本发明实施例用于低频信号检测及传输系统的模拟前端装置的另一种结构图；FIG. 2 is another structural diagram of an analog front-end device used in a low-frequency signal detection and transmission system according to an embodiment of the present invention;
图3为本发明实施例用于低频信号检测及传输系统的模拟前端装置的再一种结构图；3 is another structural diagram of an analog front-end device used in a low-frequency signal detection and transmission system according to an embodiment of the present invention;
图4为本发明实施例中一种可编程增益放大器的结构图；FIG. 4 is a structural diagram of a programmable gain amplifier in an embodiment of the present invention;
图5为本发明实施例中另一种可编程增益放大器的结构图；FIG. 5 is a structural diagram of another programmable gain amplifier in an embodiment of the present invention;
图6为本发明实施例中再一种可编程增益放大器的结构图；FIG. 6 is a structural diagram of another programmable gain amplifier in an embodiment of the present invention;
图7.1为本发明实施例中一种数字/模拟转换器的结构图；Figure 7.1 is a structural diagram of a digital/analog converter in an embodiment of the present invention;
图7.2为本发明实施例中另一种数字/模拟转换器的结构图；Figure 7.2 is a structural diagram of another digital/analog converter in the embodiment of the present invention;
图7.3为本发明实施例中再一种数字/模拟转换器的结构图；Figure 7.3 is a structural diagram of another digital/analog converter in the embodiment of the present invention;
图7.4为本发明实施例中又一种数字/模拟转换器的结构图；Figure 7.4 is a structural diagram of another digital/analog converter in the embodiment of the present invention;
图8为本发明实施例中一种比较器的结构图；FIG. 8 is a structural diagram of a comparator in an embodiment of the present invention;
图9为本发明实施例中另一种比较器的结构图；FIG. 9 is a structural diagram of another comparator in an embodiment of the present invention;
图10为本发明实施例中可编程增益放大器的一种偏置电压产生电路结构图；10 is a structural diagram of a bias voltage generating circuit of a programmable gain amplifier in an embodiment of the present invention;
图11.1为本发明实施例中第一种磁感应模块的结构图；Figure 11.1 is a structural diagram of the first magnetic induction module in the embodiment of the present invention;
图11.2为本发明实施例中第二种磁感应模块的结构图；Figure 11.2 is a structural diagram of the second magnetic induction module in the embodiment of the present invention;
图11.3为本发明实施例中第三种磁感应模块的结构图；Figure 11.3 is a structural diagram of the third magnetic induction module in the embodiment of the present invention;
图11.4为本发明实施例中第四种磁感应模块的结构图；Figure 11.4 is a structural diagram of the fourth magnetic induction module in the embodiment of the present invention;
图11.5为本发明实施例中第五种磁感应模块的结构图；Figure 11.5 is a structural diagram of the fifth magnetic induction module in the embodiment of the present invention;
图11.6为本发明实施例中第六种磁感应模块的结构图；Figure 11.6 is a structural diagram of the sixth magnetic induction module in the embodiment of the present invention;
图11.7为本发明实施例中第七种磁感应模块的结构图；Figure 11.7 is a structural diagram of the seventh magnetic induction module in the embodiment of the present invention;
图12为本发明实施例中低频信号检测方法的流程图；FIG. 12 is a flow chart of a low-frequency signal detection method in an embodiment of the present invention;
图13为本发明实施例中通过实验测得的将磁感应模块置入不同移动通信终端，距离与低频感应信号幅度值的对应关系示意图；Fig. 13 is a schematic diagram of the corresponding relationship between the distance and the amplitude value of the low-frequency induction signal when the magnetic induction module is placed in different mobile communication terminals measured through experiments in the embodiment of the present invention;
图14为本发明实施例中使用成对的比较器采用磁场数据低频信号检测方法进行解码处理的示意图；14 is a schematic diagram of decoding processing using a paired comparator using a magnetic field data low-frequency signal detection method in an embodiment of the present invention;
图15为本发明实施例中使用成对的比较器采用低频信号检测方法进行距离控制处理的示意图；15 is a schematic diagram of distance control processing using a paired comparator and a low-frequency signal detection method in an embodiment of the present invention;
图16为本发明实施例中使用单个比较器采用磁场数据低频信号检测方法进行解码处理的示意图；16 is a schematic diagram of decoding processing using a single comparator and a low-frequency signal detection method for magnetic field data in an embodiment of the present invention;
图17为本发明实施例中使用单个比较器采用低频信号检测方法进行距离控制处理的示意图。FIG. 17 is a schematic diagram of distance control processing using a single comparator and using a low-frequency signal detection method in an embodiment of the present invention.
具体实施方式Detailed ways
本发明的主要构思是，在低频信号检测及传输系统中增加一个模拟前端装置，来减少电路噪声和环境噪声对低频信号的干扰，从而提高低频交变磁场距离检测和控制的精度。The main concept of the present invention is to add an analog front-end device to the low-frequency signal detection and transmission system to reduce the interference of circuit noise and environmental noise to the low-frequency signal, thereby improving the accuracy of low-frequency alternating magnetic field distance detection and control.
以下结合附图和实施例对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。The principles and features of the present invention will be described below in conjunction with the accompanying drawings and embodiments, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.
图1为本发明实施例用于低频信号检测及传输系统的模拟前端装置的一种结构图。如图1所示，本发明的低频信号检测及传输系统的模拟前端装置，包括磁感应模块100、低通滤波模块104、放大器101、数字/模拟转换器102和比较器103，磁感应模块100、低通滤波模块104、放大器101顺次相连，放大器101的输出端与比较器103的正向输入端相连，数字/模拟转换器102的输出端与比较器103的反向输入端相连。本发明中，放大器101为双端输入单端输出放大器。放大器101对输入的微弱信号进行预放大，数字/模拟转换器102将由数字控制器输出的数字信号转换为模拟信号，然后利用比较器103对两个信号进行比较，得到需要的数字信号，传输到数字控制器中进行处理。这里所提到的数字控制器属于低频检测及传输系统，但不属于模拟前端，其作用是根据比较器输出进行比较器和数字/模拟转换器打开/关断模式的控制。FIG. 1 is a structural diagram of an analog front-end device used in a low-frequency signal detection and transmission system according to an embodiment of the present invention. As shown in Figure 1, the analog front-end device of the low-frequency signal detection and transmission system of the present invention includes a magnetic induction module 100, a low-pass filter module 104, an amplifier 101, a digital/analog converter 102 and a comparator 103, a magnetic induction module 100, a low-pass filter module 104, and a The filtering module 104 and the amplifier 101 are connected in sequence, the output terminal of the amplifier 101 is connected with the positive input terminal of the comparator 103 , the output terminal of the digital/analog converter 102 is connected with the negative input terminal of the comparator 103 . In the present invention, the amplifier 101 is an amplifier with double-ended input and single-ended output. The amplifier 101 pre-amplifies the input weak signal, the digital/analog converter 102 converts the digital signal output by the digital controller into an analog signal, and then uses the comparator 103 to compare the two signals to obtain the required digital signal, which is transmitted to processed in the digital controller. The digital controller mentioned here belongs to the low-frequency detection and transmission system, but it does not belong to the analog front end. Its function is to control the on/off mode of the comparator and the digital/analog converter according to the output of the comparator.
图2为本发明实施例中用于低频信号检测及传输系统的模拟前端装置的另一种结构图。如图2所示，本实施例中，低频信号检测及传输系统的模拟前端装置，包括一个磁感应模块100、一个低通滤波模块104、一个放大器101、数字/模拟转换器102、数字/模拟转换器105和比较器103、比较器106，磁感应模块100、低通滤波模块104、放大器101顺次相连，放大器101的输出端分别与比较器103、比较器106的正向输入端相连，数字/模拟转换器102、数字/模拟转换器105与比较器103、比较器106组成两路，每一路中数字/模拟转换器的输出端与比较器的反向输入端相连，每上下两路组成一对，共一对。FIG. 2 is another structural diagram of an analog front-end device used in a low-frequency signal detection and transmission system in an embodiment of the present invention. As shown in Figure 2, in this embodiment, the analog front-end device of the low-frequency signal detection and transmission system includes a magnetic induction module 100, a low-pass filter module 104, an amplifier 101, a digital/analog converter 102, a digital/analog conversion Device 105 is connected with comparator 103, comparator 106, magnetic induction module 100, low-pass filter module 104, amplifier 101 in sequence, and the output end of amplifier 101 is connected with the forward input end of comparator 103, comparator 106 respectively, digital/ Analog converter 102, digital/analog converter 105, comparator 103, comparator 106 form two roads, the output end of digital/analog converter in each road is connected with the inverting input end of comparator, every upper and lower two roads form a Yes, a pair.
图3为本发明实施例中用于低频信号检测及传输系统的模拟前端装置的再一种结构图。如图3所示，本实施例中，低频信号检测及传输系统的模拟前端装置，包括一个磁感应模块100、一个低通滤波模块104、一个放大器201、六个数字/模拟转换器202、203、204和六个比较器205、206、207，放大器201的输出端分别与六个比较器205、206、207的正向输入端相连，六个数字/模拟转换器202、203、204与六个比较205、206、207器组成六路，每一路中数字/模拟转换器的输出端与比较器的反向输入端相连，每上下两路组成一对，共三对。FIG. 3 is another structural diagram of an analog front-end device used in a low-frequency signal detection and transmission system in an embodiment of the present invention. As shown in Figure 3, in this embodiment, the analog front-end device of the low-frequency signal detection and transmission system includes a magnetic induction module 100, a low-pass filter module 104, an amplifier 201, six digital/analog converters 202, 203, 204 and six comparators 205, 206, 207, the output terminal of the amplifier 201 is connected with the positive input terminals of the six comparators 205, 206, 207 respectively, and the six digital/analog converters 202, 203, 204 are connected with six Comparators 205, 206, and 207 form six circuits, and the output terminal of the digital/analog converter in each circuit is connected with the inverting input terminal of the comparator. Each upper and lower circuit forms a pair, and there are three pairs in total.
本发明中，放大器可以为接成电阻负反馈网络的单级放大器或多级级联放大器。这里，我们给出几种级联放大器的实例。In the present invention, the amplifier can be a single-stage amplifier or a multi-stage cascaded amplifier connected into a resistor negative feedback network. Here, we give several examples of cascaded amplifiers.
图4为本发明实施例中一种可编程增益放大器的结构图。如图4所示，本发明实施例中，放大器为四级级联放大器，该四级级联放大器的组成为：第一级包括第一双端输入单端输出放大器301、电阻Ra1和电阻Rb1；电阻Ra1的一端接信号输入端口IN，另一端接第一双端输入单端输出放大器301的反向输入端，电阻Rb1接在第一双端输入单端输出放大器301的反向输入端和输出端之间，第一双端输入单端输出放大器301的同向输入端接共模电压VCM；第二级包括第二双端输入单端输出放大器302、电阻Ra2、电阻Rb2、电阻Rc1、电阻Rc2、电容C1和电容C2；电阻Ra2和电阻Rb2顺次串联在共模电压VCM和第二双端输入单端输出放大器302的输出端之间，电阻Ra2和电阻Rb2的接点接第二双端输入单端输出放大器302的反向输入端，电阻Rc1和电容C1顺次串联在第一双端输入单端输出放大器301的输出端和地GND之间，电容C2和电阻Rc2顺次串联在电阻Rc1和电容C1的接点与共模电压VCM之间，电容C2和电阻Rc2的接点接第二双端输入单端输出放大器302的同向输入端；第三级包括第三双端输入单端输出放大器303、电阻Ra3、电阻Rb3、电阻Rc3、电阻Rc4、电容C3和电容C4；电阻Ra3和电阻Rb3顺次串联在共模电压VCM和第三双端输入单端输出放大器303的输出端之间，电阻Ra3和电阻Rb3的接点接第三双端输入单端输出放大器303的反向输入端，电阻Rc3和电容C3顺次串联在第二双端输入单端输出放大器302的输出端和地GND之间，电容C4和电阻Rc4顺次串联在电阻Rc3和电容C3的接点与共模电压VCM之间，电容C4和电阻Rc4的接点接第三双端输入单端输出放大器303的同向输入端；第四级包括第四放大器304、电容C5和电阻Rc5；电容C5和电阻Rc5顺次串联在第三双端输入单端输出放大器303的输出端和共模电压VCM之间，电容C5和电阻Rc5的接点接第四放大器304的同向输入端，第四放大器304的反向输入端和输出端相连。FIG. 4 is a structural diagram of a programmable gain amplifier in an embodiment of the present invention. As shown in Figure 4, in the embodiment of the present invention, the amplifier is a four-stagecascaded amplifier. Rb1 ; one end of the resistance Ra1 is connected to the signal input port IN, the other end is connected to the reverse input end of the first double-ended input single-ended output amplifier 301, and the resistance Rb1 is connected to the reverse input end of the first double-ended input single-ended output amplifier 301 Between the input terminal and the output terminal, the same input terminal of the first double-ended input and single-ended output amplifier 301 is connected to the common-mode voltage VCM; the second stage includes a second double-ended input and single-ended output amplifier 302, a resistor Ra2 , and a resistor Rb2 , resistor Rc1 , resistor Rc2 , capacitor C1 and capacitor C2 ; resistor Ra2 and resistor Rb2 are serially connected in series between the common-mode voltage VCM and the output terminal of the second double-ended input and single-ended output amplifier 302 , the junction of resistor Ra2 and resistor Rb2 is connected to the inverting input end of the second double-ended input and single-ended output amplifier 302, and the resistor Rc1 and capacitorC1 are serially connected in series at the output of the first double-ended input and single-ended output amplifier 301 Between terminal and ground GND, capacitor C2 and resistor Rc2 are serially connected between the junction of resistor Rc1 and capacitor C1 and the common mode voltage VCM, and the junction of capacitor C2 and resistor Rc2 is connected to the second double-ended input single The same direction input end of terminal output amplifier 302; The third stage includes the third double-ended input single-ended output amplifier 303, resistor Ra3 , resistor Rb3 , resistor Rc3 , resistor Rc4 , capacitor C3 and capacitor C4 ; Ra3 and resistor Rb3 are serially connected in series between the common-mode voltage VCM and the output of the third double-ended input single-ended output amplifier 303, and the junction of resistor Ra3 and resistor Rb3 is connected to the third double-ended input single-ended output amplifier The inverting input terminal of 303, the resistorRc3 and the capacitor C3 are serially connected in series between the output terminalof the second double-ended input single-ended output amplifier 302 and the ground GND, and the capacitorC4 and the resistorRc4 are serially connected in series with the resistor R Between the junction ofc3 and capacitor C3 and the common- mode voltage VCM, the junction of capacitorC4 and resistorRc4 is connected to the same input end of the third double-ended input and single-ended output amplifier 303; the fourth stage includes a fourth amplifier 304, a capacitor C5 and resistor Rc5 ; capacitor C5 and resistor Rc5 are serially connected in series between the output terminal of the third double-ended input and single-ended output amplifier 303 and the common mode voltage VCM, and the junction of capacitor C5 and resistor Rc5 is connected to the first The non-inverting input end of the four amplifiers 304 and the inverting input end of the fourth amplifier 304 are connected to the output end.
图4所示的放大器是一种可编程增益放大器，其具有低通和高通滤波的功能，共分为4级，每个方框内的电路为一级，IN为信号输入端口、VCM为共模电压输入端口、Vout信号输出端口。运算放大器301(即第一双端输入单端输出放大器)接成电阻负反馈结构，其闭环增益由Rb1和Ra1的比值确定，Rb1和Ra1的比值可调。Rc1，C1，C2，RC2构成一阶低通和高通滤波器；C2具有隔直的作用，隔断第一级电路的失调电压传到第二级；运算放大器302(即第二双端输入单端输出放大器)接成电阻负反馈结构，其闭环增益由Rb2和Ra2的比值确定，Rb2和Ra2的比值可调。Rc3、C3、C4、RC4构成一阶低通和高通滤波器；C4具有隔直的作用，隔断第二级的电路的失调电压传到第三级；运算放大器303(即第三双端输入单端输出放大器)接成电阻负反馈结构，其闭环增益由Rb3和Ra3的比值确定，Rb3和Ra3的比值可调。C5、RC5构成一阶高通滤波器；同时隔断前面电路的失调电压传到最后一级；运算放大器304(即第四放大器)接成单位增益的缓冲器结构。整个PGA的失调电压只有接成单位增益缓冲器结构运算放大器304的失调电压。该可编程增益放大器的低频截止频率由Rc1和C1、Rc3和C3共同确定，高频截止频率由C2和RC2、C4和RC4、C5和RC5共同确定。The amplifier shown in Figure 4 is a programmable gain amplifier, which has the function of low-pass and high-pass filtering. It is divided into 4 stages, and the circuit in each box is a stage. Analog voltage input port, Vout signal output port. The operational amplifier 301 (that is, the first double-ended input and single-ended output amplifier) is connected into a resistor negative feedback structure, and its closed-loop gain is determined by the ratio of Rb1 to Ra1 , and the ratio of Rb1 to Ra1 is adjustable. Rc1 , C1 , C2 , and RC2 form a first-order low-pass and high-pass filter; C2 has the function of blocking direct current, and blocks the offset voltage of the first-stage circuit from being transmitted to the second stage; the operational amplifier 302 (that is, the second Double-ended input and single-ended output amplifier) are connected into a resistor negative feedback structure, and its closed-loop gain is determined by the ratio of Rb2 and Ra2 , and the ratio of Rb2 and Ra2 is adjustable. Rc3 , C3 , C4 , and RC4 form a first-order low-pass and high-pass filter; C4 has the function of blocking direct current, and blocks the offset voltage of the circuit of the second stage from being transmitted to the third stage; the operational amplifier 303 (that is, the first stage Three double-ended input single-ended output amplifiers) are connected into a resistor negative feedback structure, and its closed-loop gain is determined by the ratio of Rb3 and Ra3 , and the ratio of Rb3 and Ra3 is adjustable. C5 and RC5 form a first-order high-pass filter; at the same time, the offset voltage of the previous circuit is cut off from being transmitted to the last stage; the operational amplifier 304 (ie, the fourth amplifier) is connected to form a unity-gain buffer structure. The offset voltage of the entire PGA is only the offset voltage of the operational amplifier 304 connected to a unity gain buffer structure. The low-frequency cut-off frequency of the programmable gain amplifier is jointly determined by Rc1 and C1 , Rc3 and C3 , and the high-frequency cut-off frequency is jointly determined by C2 and RC2 , C4 and RC4 , and C5 and RC5 .
本实施例如果两级放大可以满足要求可以去掉第三级，构成三级结构，为保证频响构成低通的Rc1和C1、Rc3和C3可以保留或部分保留，构成高通的C2和RC2、C4和RC4、C5和RC5可以保留或部分保留。如果一级放大可以满足要求可以去掉第二级和第三级，构成两级结构，为保证频响构成低通的Rc1和C1、Rc3和C3可以保留或部分保留，构成高通的C2和RC2、C4和RC4、C5和RC5可以保留或部分保留。In this embodiment, if the two-stage amplification can meet the requirements, the third stage can be removed to form a three-stage structure. In order to ensure the frequency response, the low-pass Rc1 and C1 , Rc3 and C3 can be reserved or partially reserved to form the high-pass C2 and RC2 , C4 and RC4 , C5 and RC5 may be retained or partially retained. If the first-stage amplification can meet the requirements, the second and third stages can be removed to form a two-stage structure. In order to ensure the frequency response, the low-pass Rc1 and C1 , Rc3 and C3 can be reserved or partially reserved to form a high-pass C2 and RC2 , C4 and RC4 , C5 and RC5 may be retained or partially retained.
图5为本发明实施例中另一种可编程增益放大器的结构图。如图5所示，本发明实施例中，放大器为四级级联放大器，该四级级联放大器的组成为：第一级包括第一双端输入单端输出放大器301、电阻Ra1、电阻Rb1和电容C1；电阻Ra1接在信号输入端I N和第一双端输入单端输出放大器301的反向输入端之间，电阻Rb1和电容C1并联在第一双端输入单端输出放大器301的反向输入端和输出端之间，第一双端输入单端输出放大器301的同向输入端接共模电压VCM；第二级包括第二双端输入单端输出放大器302、电阻Ra2、电阻Rb2、电阻Rc2、电容C2和电容C3；电阻Ra2接在共模电压VCM和第二双端输入单端输出放大器302的反向输入端之间，电阻Rb2和电容C3并联在第二双端输入单端输出放大器302的反向输入端和输出端之间，电容C2和电阻Rc2顺次串联在第一双端输入单端输出放大器301的输出端和共模电压VCM之间，电容C2和电阻Rc2的接点接第二双端输入单端输出放大器302的同向输入端；第三级包括第三双端输入单端输出放大器303、电阻Ra3、电阻Rb3、电阻Rc4和电容C4；电阻Ra3和电阻Rb32顺次串联在共模电压VCM和第三双端输入单端输出放大器303的输出端之间，电阻Ra3和电阻Rb32的接点接第三双端输入单端输出放大器303的反向输入端，电容C4和电阻Rc4顺次串联在第二双端输入单端输出放大器302的输出端和共模电压VCM之间，电容C4和电阻Rc4的接点接第三双端输入单端输出放大器303的同向输入端；第四级包括第四放大器304、电阻Rc5和电容C5；电容C5和电阻Rc5顺次串联在第三双端输入单端输出放大器303的输出端和共模电压VCM之间，电容C5和电阻Rc5的接点接第四放大器304的同向输入端，第四放大器304的反向输入端和输出端相连。FIG. 5 is a structural diagram of another programmable gain amplifier in an embodiment of the present invention. As shown in Figure 5, in the embodiment of the present invention, the amplifier is a four-stagecascaded amplifier. Rb1 and capacitor C1 ; resistor Ra1 is connected between the signal input terminal I N and the reverse input terminal of the first double-ended input single-ended output amplifier 301, and resistor Rb1 and capacitor C1 are connected in parallel at the first double-ended input single-ended output amplifier. Between the inverting input terminal and the output terminal of the terminal output amplifier 301, the same direction input terminal of the first double-ended input single-ended output amplifier 301 is connected to the common mode voltage VCM; the second stage includes a second double-ended input single-ended output amplifier 302 , resistor Ra2 , resistor Rb2 , resistor Rc2 , capacitor C2 and capacitor C3 ; resistor Ra2 is connected between the common-mode voltage VCM and the inverting input of the second double-ended input and single-ended output amplifier 302, and the resistor Rb2 and capacitor C3 are connected in parallel between the inverting input terminal and the output terminal of the second double-ended input single-ended output amplifier 302, and capacitor C2 and resistor Rc2 are connected in series in series in the first double-ended input single-ended output amplifier 301 Between the output end of the output port and the common-mode voltage VCM, the junction of the capacitorC2 and the resistor Rc2 is connected to the same-inverting input end of the second double-ended input single-ended output amplifier 302; the third stage includes a third double-ended input single-ended output amplifier 303, the resistor Ra3 , the resistor Rb3 , the resistor Rc4 and the capacitor C4 ; the resistor Ra3 and the resistor Rb32 are sequentially connected in series between the common-mode voltage VCM and the output terminal of the third double-ended input and single-ended output amplifier 303, The junction of the resistor Ra3 and the resistor Rb32 is connected to the reverse input end of the third double-ended input single-ended output amplifier 303, and the capacitorC4 and the resistor Rc4 are serially connected to the output end of the second double-ended input single-ended output amplifier 302 and the common-mode voltage VCM, the junction of capacitorC4 and resistorRc4 is connected to the same input terminal of the third double-ended input and single-ended output amplifier 303; the fourth stage includes a fourth amplifier 304, resistorRc5 and capacitorC5 CapacitorC5 and resistorRc5 are serially connected in series between the output terminal of the third double-ended input and single-ended output amplifier 303 and the common mode voltage VCM, and the junction of capacitorC5 and resistorRc5 is connected to the same direction of the fourth amplifier 304 The input terminal, the inverting input terminal of the fourth amplifier 304 is connected to the output terminal.
图5所示的放大器也是一种可编程增益放大器，其与图4中结构的唯一区别为低通截止频率由Rb1和C1、Rb2和C2共同确定。The amplifier shown in Figure 5 is also a programmable gain amplifier, and its only difference from the structure in Figure 4 is that the low-pass cutoff frequency is jointly determined by Rb1 and C1 , Rb2 and C2 .
图6为本发明实施例中再一种可编程增益放大器的结构图。如图6所示，本发明实施例中，放大器为四级级联放大器，该四级级联放大器的组成为：第一级包括第一放大器301、电阻Ra1、电阻Rb1、电阻Ra11和电阻Rb11；电阻Ra1和电阻Rb1顺次串联在正向信号输入端INP和第一放大器301的输出端之间，电阻Ra1和电阻Rb1的接点接第一放大器301的反向输入端，电阻Ra11和电阻Rb11顺次串联在反向信号输入端INN和地GND之间，电阻Ra11和电阻Rb11的接点接第一放大器301的同向输入端；第二级包括第二双端输入单端输出放大器302、电阻Ra2、电阻Rb2、电阻Rc1、电阻Rc2、电容C1和电容C2；电阻Ra2、电阻Rb2顺次串联在共模电压VCM和第二双端输入单端输出放大器302的输出端之间，电阻Ra2、电阻Rb2的接点接第二双端输入单端输出放大器302的反向输入端，电阻Rc1、电容C1顺次串联在第一放大器301的输出端和地GND之间，电容C2和电阻Rc2顺次串联在电阻Rc1、电容C1的接点与共模电压VCM之间，电容C2和电阻Rc2的接点接第二双端输入单端输出放大器302的同向输入端；第三级包括第三双端输入单端输出放大器303、电阻Ra3、电阻Rb3、电阻Rc3、电阻Rc4、电容C3和电容C4；电阻Ra3和电阻Rb3顺次串联在共模电压VCM和第三双端输入单端输出放大器303的输出端之间，电阻Ra3和电阻接点接第三双端输入单端输出放大器303的反向输入端，电阻Rc3和电容C3顺次串联在第二双端输入单端输出放大器302的输出端和地GND之间，电容C4和电阻Rc4顺次串联在电阻Rc3和电容C3的接点与共模电压VCM之间，电容C4和电阻Rc4的接点接第三双端输入单端输出放大器303的同向输入端；第四级包括第四放大器304、电阻Rc5和电容C5；电容C5和电阻Rc5顺次串联在第三双端输入单端输出放大器303的输出端和共模电压VCM之间，电容C5和电阻Rc5的接点接第四放大器304的同向输入端，第四放大器304的反向输入端和输出端相连。FIG. 6 is a structural diagram of another programmable gain amplifier in an embodiment of the present invention. As shown in Figure 6, in the embodiment of the present invention, the amplifier is a four-stagecascadedamplifier. and resistance Rb11 ; resistance Ra1 and resistance Rb1 are serially connected in series between the forward signal input terminal INP and the output end of the first amplifier 301, and the junction of resistance Ra1 and resistance Rb1 is connected to the reverse direction of the first amplifier 301 At the input terminal, the resistor Ra11 and the resistor Rb11 are serially connected in series between the reverse signal input terminal INN and the ground GND, and the contact of the resistor Ra11 and the resistor Rb11 is connected to the same input terminal of the first amplifier 301; the second stage includes The second double-ended input single-ended output amplifier 302, resistor Ra2 , resistor Rb2 , resistor Rc1 , resistor Rc2 , capacitor C1 and capacitor C2 ; resistor Ra2 and resistor Rb2 are connected in series at the common mode voltage VCM Between the output end of the second double-ended input and single-ended output amplifier 302, the contact point of the resistor Ra2 and the resistor Rb2 is connected to the inverting input end of the second double-ended input and single-ended output amplifier 302, the resistor Rc1 and the capacitor C1 serially connected in series between the output terminal of the first amplifier 301 and the ground GND, the capacitorC2 and the resistorRc2 serially connected in series between the resistorRc1 , the junction of the capacitorC1 and the common mode voltage VCM, the capacitorC2 and the resistor R The contact ofc2 is connected to the same input terminal of the second double-ended input single-ended output amplifier 302; the third stage includes the third double-ended input single-ended output amplifier 303, resistor Ra3 , resistor Rb3 , resistor Rc3 , and resistor Rc4 , capacitor C3 and capacitor C4 ; resistor Ra3 and resistor Rb3 are serially connected in series between the common-mode voltage VCM and the output of the third double-ended input and single-ended output amplifier 303, and the resistor Ra3 and the resistor contact are connected to the third The inverting input terminal of the double-ended input single-ended output amplifier 303, the resistorRc3 and the capacitor C3 are serially connected between the output terminal of the second double-ended input single-ended output amplifier 302 and the ground GND, the capacitorC4 and the resistor Rc4 is connected in series between the joint of resistorRc3 and capacitor C3 and the common mode voltage VCM, and the joint of capacitorC4 and resistor Rc4 is connected to the same input end of the third double-ended input and single-ended output amplifier 303; the fourth stage Comprising a fourth amplifier 304, a resistorRc5 and a capacitorC5 ; the capacitorC5 and the resistorRc5 are serially connected in series between the output of the third double-ended input and single-ended output amplifier 303 and the common mode voltage VCM, and the capacitorC5 and The junction of the resistor Rc5 is connected to the non-inverting input terminal of the fourth amplifier 304 , and the inverting input terminal of the fourth amplifier 304 is connected to the output terminal.
图6所示的放大器也是一种可编程增益放大器，其与图4中结构的唯一区别是需要输入差分信号。其中Ra11＝Ra1，Rb11＝Rb1，第一级的增益为Rb1和Ra1的比值，且增益可调。The amplifier shown in Figure 6 is also a programmable gain amplifier, the only difference between it and the structure in Figure 4 is that it needs to input a differential signal. Where Ra11 =Ra1 , Rb11 =Rb1 , the gain of the first stage is the ratio of Rb1 to Ra1 , and the gain is adjustable.
这里，我们再给出数字/模拟转换器的几种实例。Here, we give several examples of digital/analog converters.
图7.1为本发明实施例中一种数字/模拟转换器的结构图。如图7.1所示，本实施例中，数字/模拟转换器采用电流模式R2R DAC实现数字到模拟的转换，并且输出范围最大为二分之一电源地电压。依照本发明参考电平需求，可使用相应连接方式产生对应的高低电位的参考电平。Fig. 7.1 is a structural diagram of a digital/analog converter in an embodiment of the present invention. As shown in Figure 7.1, in this embodiment, the digital/analog converter adopts the current mode R2R DAC to realize digital-to-analog conversion, and the output range is at most half the power supply ground voltage. According to the requirements of the reference level of the present invention, corresponding connection methods can be used to generate corresponding high and low potential reference levels.
图7.2为本发明实施例中另一种数字/模拟转换器的结构图。如图7.2所示，本实施例中，数字/模拟转换器采用电流模式R2R DAC实现数字到模拟的转换，与图7.1所示DAC的区别在于其输出范围不局限于二分之一电源地电压，并且共模电平可调节，由Vcom电压值确定。依照本发明采用该种DAC可以减少参考电平产生电路的设计复杂度。Fig. 7.2 is a structural diagram of another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.2, in this embodiment, the digital/analog converter uses a current mode R2R DAC to realize digital-to-analog conversion. The difference from the DAC shown in Figure 7.1 is that its output range is not limited to half the power supply ground voltage , and the common-mode level is adjustable, determined by the Vcom voltage value. Adopting this kind of DAC according to the present invention can reduce the design complexity of the reference level generation circuit.
图7.3为本发明实施例中再一种数字/模拟转换器的结构图。图7.3所示，本实施例中，数字/模拟转换器采用电压模式R2R DAC实现数字到模拟的转换，其输出范围不局限于二分之一电源地电压。依照本发明采用该种DAC可以减少参考电平产生电路的设计复杂度。Fig. 7.3 is a structural diagram of another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.3, in this embodiment, the digital/analog converter uses a voltage mode R2R DAC to realize digital-to-analog conversion, and its output range is not limited to half the power supply ground voltage. Adopting this kind of DAC according to the present invention can reduce the design complexity of the reference level generation circuit.
图7.4为本发明实施例中又一种数字/模拟转换器的结构图。图7.4所示，本实施例中，数字/模拟转换器采用R2R网络实现数字到模拟的转换，其输出范围为2倍Vref，最大可为电源地电压。依照本发明采用该种电路，由于减少一个放大器，可以减少参考电平产生电路的设计复杂度以及功耗。Fig. 7.4 is a structural diagram of another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.4, in this embodiment, the digital/analog converter uses the R2R network to realize digital-to-analog conversion, and its output range is 2 times Vref, and the maximum can be the power supply ground voltage. According to the present invention, the design complexity and power consumption of the reference level generation circuit can be reduced due to the reduction of one amplifier.
这里，我们还给出几种比较器的实例。Here, we also give examples of several comparators.
图8为本发明实施例中一种比较器的结构图。如图8所示，本实施例中，比较器包括三个NMOS管Mn0、Mn1、Mn2和两个PMOS管Mp1、Mp2，以及一个反向器，PMOS管Mp1和PMOS管Mp2的栅极相连，源极均接电源Vcc，PMOS管Mp1的漏极接NMOS管Mn1的漏极，NMOS管Mn 1和NMOS管Mn2的源极均接NMOS管Mn0的漏极，NMOS管Mn2的漏极接PMOS管Mp2的漏极，NMOS管Mn0的源极接地GND，栅极接偏置电压Vbn，反向器的输入端接PMOS管Mp2的漏极，NMOS管Mn2的栅极为比较器的正向输入端Vin+，NMOS管Mn1的栅极为比较器的反向输入端Vin-，反向器的输出端为比较器的输出端Vo。图8所示的比较器用于图2中三对比较器中高电平的比较，即VG1+，VG2+和VM+的比较。由于NMOS作为输入管，可以很好的实现高电平比较功能。FIG. 8 is a structural diagram of a comparator in an embodiment of the present invention. As shown in Figure 8, in this embodiment, the comparator includes three NMOS transistors Mn0, Mn1, Mn2 and two PMOS transistors Mp1, Mp2, and an inverter, the gates of the PMOS transistor Mp1 and the PMOS transistor Mp2 are connected, The source is connected to the power supply Vcc, the drain of the PMOS transistor Mp1 is connected to the drain of the NMOS transistor Mn1, the sources of the NMOS transistor Mn1 and the NMOS transistor Mn2 are connected to the drain of the NMOS transistor Mn0, and the drain of the NMOS transistor Mn2 is connected to the PMOS transistor The drain of Mp2, the source of the NMOS transistor Mn0 are grounded to GND, the gate is connected to the bias voltage Vbn, the input terminal of the inverter is connected to the drain of the PMOS transistor Mp2, and the gate of the NMOS transistor Mn2 is the positive input terminal Vin+ of the comparator , the gate of the NMOS transistor Mn1 is the inverting input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal Vo of the comparator. The comparator shown in Figure 8 is used for the comparison of high levels among the three pairs of comparators in Figure 2, that is, the comparison of VG1+, VG2+ and VM+. Since the NMOS is used as the input tube, it can realize the high-level comparison function very well.
图9为本发明实施例中另一种比较器的结构图。如图9所示，本实施例中，比较器包括三个PMOS管Mp0、Mp3、Mp4和两个NMOS管Mn3、Mn4以及一个反向器，PMOS管Mp0的源极接电源Vcc，栅极接偏置电压Vbp，漏极接PMOS管Mp3和PMOS管Mp4的源极，PMOS管Mp3的漏极接NMOS管Mn3的漏极和栅极，NMOS管Mn3和NMOS管Mn4的源极接地GND，NMOS管Mn4的漏极接PMOS管Mp4的漏极，反向器的输入端接NMOS管Mn4的漏极，PMOS管Mp4的栅极为比较器的正向输入端Vin+，PMOS管Mp3的栅极为比较器的反向输入端Vin-，反向器的输出端为比较器的输出端Vo。图9所示的比较器用于图2中三对比较器中低电平的比较，即VG1-，VG2-和VM-的比较。由于PMOS作为输入管，可以很好的实现低电平比较功能。FIG. 9 is a structural diagram of another comparator in an embodiment of the present invention. As shown in Figure 9, in this embodiment, the comparator includes three PMOS transistors Mp0, Mp3, Mp4, two NMOS transistors Mn3, Mn4 and an inverter, the source of the PMOS transistor Mp0 is connected to the power supply Vcc, and the gate is connected to The bias voltage Vbp, the drain is connected to the source of PMOS transistor Mp3 and PMOS transistor Mp4, the drain of PMOS transistor Mp3 is connected to the drain and gate of NMOS transistor Mn3, the source of NMOS transistor Mn3 and NMOS transistor Mn4 is grounded to GND, the NMOS The drain of the tube Mn4 is connected to the drain of the PMOS tube Mp4, the input terminal of the inverter is connected to the drain of the NMOS tube Mn4, the gate of the PMOS tube Mp4 is the positive input terminal Vin+ of the comparator, and the gate of the PMOS tube Mp3 is the comparator The inverting input terminal Vin- of the inverter is the output terminal Vo of the comparator. The comparator shown in FIG. 9 is used for the comparison of low levels among the three pairs of comparators in FIG. 2 , that is, the comparison of VG1-, VG2- and VM-. Since the PMOS is used as the input tube, the low-level comparison function can be well realized.
图10为本发明实施例中可编程增益放大器的一种偏置电压产生电路结构图。如图10所示，电源电压VIN经过2级LDO(Low Dropout regulator，低压差线性稳压器)901和902产生可编程增益放大器的偏置电压VCM(也即前述的共模电压)，可以极大的提高可编程增益放大器的偏置电压的电源抑制比。FIG. 10 is a structural diagram of a bias voltage generating circuit of a programmable gain amplifier in an embodiment of the present invention. As shown in Figure 10, the power supply voltage VIN passes through two stages of LDO (Low Dropout regulator, low dropout linear regulator) 901 and 902 to generate the bias voltage VCM (that is, the aforementioned common mode voltage) of the programmable gain amplifier, which can be extremely A large power supply rejection ratio improves the bias voltage of the programmable gain amplifier.
图11.1为本发明实施例中第一种磁感应模块的结构图。图11.1中，磁感应模块为磁感应线圈。磁感应线圈的两输出端可以直接与低通滤波模块的两输入端相连。Figure 11.1 is a structural diagram of the first magnetic induction module in the embodiment of the present invention. In Figure 11.1, the magnetic induction module is a magnetic induction coil. The two output terminals of the magnetic induction coil can be directly connected with the two input terminals of the low-pass filter module.
图11.2为本发明实施例中第二种磁感应模块的结构图。图11.2中，磁感应模块为霍尔器件，且该霍尔器件的两个输出端都通过隔直电容与低通滤波模块两个输入端相连。Figure 11.2 is a structural diagram of the second magnetic induction module in the embodiment of the present invention. In Figure 11.2, the magnetic induction module is a Hall device, and the two output terminals of the Hall device are connected to the two input terminals of the low-pass filter module through a DC blocking capacitor.
图11.3为本发明实施例中第三种磁感应模块的结构图。图11.3中，磁感应模块为霍尔器件，该霍尔器件一个输出端通过隔直电容与低通滤波模块一个输入端相连，该霍尔器件的另一个输出端直接与低通滤波模块另一个输入端相连。Figure 11.3 is a structural diagram of the third magnetic induction module in the embodiment of the present invention. In Figure 11.3, the magnetic induction module is a Hall device. One output terminal of the Hall device is connected to an input terminal of the low-pass filter module through a DC blocking capacitor, and the other output terminal of the Hall device is directly connected to the other input terminal of the low-pass filter module. end connected.
图11.4为本发明实施例中第四种磁感应模块的结构图。图11.4中，磁感应模块为霍尔器件，该霍尔器件的两个输出端直接与低通滤波模块的两个输入端相连。Figure 11.4 is a structural diagram of the fourth magnetic induction module in the embodiment of the present invention. In Figure 11.4, the magnetic induction module is a Hall device, and the two output terminals of the Hall device are directly connected to the two input terminals of the low-pass filter module.
图11.5为本发明实施例中第五种磁感应模块的结构图。图11.5中，磁感应模块为巨磁阻器件，该巨磁阻器件的两个输出端都通过隔直电容与低通滤波模块的两个输入端相连。Figure 11.5 is a structural diagram of the fifth magnetic induction module in the embodiment of the present invention. In Figure 11.5, the magnetic induction module is a giant magnetoresistance device, and the two output terminals of the giant magnetoresistance device are connected to the two input terminals of the low-pass filter module through DC blocking capacitors.
图11.6为本发明实施例中第六种磁感应模块的结构图。图11.6中，磁感应模块为巨磁阻器件，该巨磁阻器件的一个输出端通过隔直电容与低通滤波模块的一个输入端相连，该巨磁阻器件的另一个输出端直接与低通滤波模块的另一个输入端相连。Figure 11.6 is a structural diagram of the sixth magnetic induction module in the embodiment of the present invention. In Figure 11.6, the magnetic induction module is a giant magnetoresistance device, one output terminal of the giant magnetoresistance device is connected to one input terminal of the low-pass filter module through a DC blocking capacitor, and the other output terminal of the giant magnetoresistance device is directly connected to the low-pass filter module. The other input terminal of the filter module is connected.
图11.7为本发明实施例中第七种磁感应模块的结构图。图11.7中，磁感应模块为巨磁阻器件，该巨磁阻器件的两个输出端直接与低通滤波模块的两个输入端相连。Figure 11.7 is a structural diagram of the seventh magnetic induction module in the embodiment of the present invention. In Figure 11.7, the magnetic induction module is a giant magnetoresistance device, and the two output terminals of the giant magnetoresistance device are directly connected to the two input terminals of the low-pass filter module.
本发明提供的用于低频信号检测及传输系统的模拟前端装置，能够减小电路噪声和环境噪声对低频信号检测及传输系统中所接收到的低频信号的干扰，从而提高低频交变磁场距离检测和控制的精度。The analog front-end device used in the low-frequency signal detection and transmission system provided by the present invention can reduce the interference of circuit noise and environmental noise to the low-frequency signal received in the low-frequency signal detection and transmission system, thereby improving the distance detection of low-frequency alternating magnetic field and control accuracy.
基于前述的用于低频信号检测及传输系统的模拟前端装置，本发明还提出了一种低频信号检测方法。图12为本发明实施例中低频信号检测方法的流程图，如图12所示，本实施例中，低频信号检测方法包括如下步骤：Based on the aforementioned analog front-end device for low-frequency signal detection and transmission system, the present invention also proposes a low-frequency signal detection method. Fig. 12 is a flowchart of a method for detecting a low-frequency signal in an embodiment of the present invention. As shown in Fig. 12, in this embodiment, the method for detecting a low-frequency signal includes the following steps:
步骤1201，在不同距离测量放大后感应电压的幅度值；Step 1201, measuring the magnitude of the amplified induced voltage at different distances;
通过实验手段，在不同手机终端上测量磁感应模块与发送磁场的读卡器在不同距离点的感应电压经放大器放大后的幅度值，并做相应的记录。图13为本发明实施例中通过实验测得的将磁感应模块置入不同移动通信终端，距离与低频感应信号幅度值的对应关系示意图。By means of experiments, the amplitude values of the induced voltages amplified by amplifiers at different distance points between the magnetic induction module and the card reader sending the magnetic field are measured on different mobile phone terminals, and corresponding records are made. 13 is a schematic diagram of the corresponding relationship between the distance and the amplitude value of the low-frequency induction signal when the magnetic induction module is placed in different mobile communication terminals measured through experiments in the embodiment of the present invention.
步骤1202，建立电压幅值与距离的对应表；Step 1202, establishing a correspondence table between voltage amplitude and distance;
将多个终端的测量数据进行处理，得到电压幅值与距离的对应表，如表1所示。The measurement data of multiple terminals are processed to obtain the corresponding table of voltage amplitude and distance, as shown in Table 1.
表1低频感应信号幅度值与距离的对应关系表Table 1 Corresponding relationship between the amplitude value of the low-frequency induction signal and the distance
步骤1203，进入低频磁场数据解码流程；Step 1203, enter the low-frequency magnetic field data decoding process;
步骤1205，设置数模转换器输出电平；Step 1205, setting the digital-to-analog converter output level;
若期望进行解码的距离为D2，查找幅度值与距离的对应表，得到D2对应信号的变化幅度为+A2到-A2，测得大多数噪声产生的幅度为A3，设置输出给比较器的电平L3、L4，使得L3应大于+A3，并小于+A2；L4小于-A3，并大于-A2，即当距离小于D2则允许解码，否则不允许解码。If the desired decoding distance is D2, look up the corresponding table of amplitude value and distance, and get the change range of the signal corresponding to D2 from +A2 to -A2, and the measured amplitude of most noise is A3, set the voltage output to the comparator Level L3 and L4, so that L3 should be greater than +A3 and less than +A2; L4 should be less than -A3 and greater than -A2, that is, when the distance is less than D2, decoding is allowed, otherwise decoding is not allowed.
步骤1207，比较器输出信号迟滞处理；Step 1207, comparator output signal hysteresis processing;
步骤1209，对处理后信号进行解码；Step 1209, decoding the processed signal;
解码器按照编码格式将逻辑处理后的信号进行解码，得到低频磁场数据流信息。解码器设置数字毛刺滤波器可对输入的数字信号进行毛刺滤除。The decoder decodes the logically processed signal according to the encoding format to obtain the low-frequency magnetic field data flow information. The digital burr filter set in the decoder can perform burr filtering on the input digital signal.
步骤1211，完成低频磁场信号的单向通信；Step 1211, complete the one-way communication of the low-frequency magnetic field signal;
将解码后数据进行相关的应用，完成低频磁场信号的单向通信功能。Apply the decoded data to related applications to complete the one-way communication function of low-frequency magnetic field signals.
步骤1204，进入距离控制流程；Step 1204, enter the distance control process;
步骤1206，设置数模转换器输出电平；Step 1206, setting the digital-to-analog converter output level;
若期望控制的距离为D1，查找幅度值与距离的对应表，得到D1对应的信号变化幅度为+A1到-A1，设置1信号的比例门限为R1，根据A1及R1，设置输出给比较器的电平L1、L2，满足在一个周期内，前端装置输出信号幅度大于L1或加上小于L2的时间百分比等于R1，即大于R1则进入所述要求控制的距离D1范围内，否则没有进入所述要求控制距离D1的范围内。If the desired control distance is D1, look up the corresponding table of amplitude value and distance, and get the corresponding signal change range of D1 from +A1 to -A1, set the proportional threshold of 1 signal to R1, and set the output to the comparator according to A1 and R1 Levels L1 and L2, satisfying that within a cycle, the output signal amplitude of the front-end device is greater than L1 or the percentage of time less than L2 is equal to R1, that is, if it is greater than R1, it will enter the range of the required control distance D1, otherwise it will not enter the range of the required control. The above requirements are within the range of the control distance D1.
步骤1208，比较器输出信号逻辑或处理；Step 1208, logic or processing of the output signal of the comparator;
当使用成对比较器得到用于进行读卡器和卡之间距离判断的数字信号时，则将该成对的数字信号进行如下操作：将输入高比较电平比较器的输出信号与低比较电平比较器的输出信号取反后信号进行或操作，得到用于距离判断的数字信号。When the paired comparator is used to obtain the digital signal used to judge the distance between the card reader and the card, the paired digital signal is operated as follows: compare the output signal of the input high comparison level comparator with the low After the output signal of the level comparator is reversed, the signal is ORed to obtain a digital signal for distance judgment.
步骤1210，对逻辑处理后信号进行采样得到0、1数据流；Step 1210, sampling the logically processed signal to obtain a 0, 1 data stream;
步骤1212，使用预设时间窗对0、1数据进行统计；Step 1212, use the preset time window to count 0 and 1 data;
预设时间窗长度，并对该时间窗内的0、1数据进行统计，计算出1所占比例。The length of the time window is preset, and the 0 and 1 data in the time window are counted to calculate the proportion of 1.
步骤1214、步骤1216，将统计结果与所设1信号比例门限进行比较，完成距离判断，实现距离控制。In steps 1214 and 1216, the statistical results are compared with the set 1-signal ratio threshold to complete distance judgment and realize distance control.
图14为本发明实施例中使用成对的比较器采用磁场数据低频信号检测方法进行解码处理的示意图。如图14所示，A0为放大器的输出信号。输入比较器的高比较电平VG+、低比较电平VG-根据解码距离并通过查找幅度值与距离的对应表进行设置。DO2为输入高比较电平的比较器的输出信号，DO3为输入低比较电平的比较器的输出取反后信号。迟滞处理后数字信号为对比较器的输出信号DO2、DO3进行迟滞逻辑处理后的信号。可设置数字毛刺滤波器可对该输入信号进行毛刺滤除。按照编码格式将迟滞处理后的信号进行解码，就可以得到低频磁场数据流信息。FIG. 14 is a schematic diagram of decoding processing using a paired comparator and using a magnetic field data low-frequency signal detection method in an embodiment of the present invention. As shown in Figure 14, A0 is the output signal of the amplifier. The high comparison level VG+ and the low comparison level VG- of the input comparator are set according to the decoding distance and by looking up the correspondence table between the amplitude value and the distance. DO2 is an output signal of a comparator inputting a high comparison level, and DO3 is an inverted signal of an output of a comparator inputting a low comparison level. The digital signal after hysteresis processing is a signal obtained by performing hysteresis logic processing on the output signals DO2 and DO3 of the comparator. A digital glitch filter can be set to filter the input signal. The low-frequency magnetic field data stream information can be obtained by decoding the hysteresis-processed signal according to the encoding format.
图15为本发明实施例中使用成对的比较器采用低频信号检测方法进行距离控制处理的示意图。如图14所示，A0为放大器的输出信号。其幅度变化范围从-A1到+A1，其对应的距离为L。假设需要对距离L进行控制，则首先查找幅度值与距离的对应表，得到在该距离上的信号幅度值。再设置1信号的比例门限为R1。根据R1，则高比较电平VG+、低比较电平VG-的设置满足在一个周期内，前端装置输出信号幅度大于VG+或小于VG-的时间百分比等于R1。对成对比较器的输出信号DO2、DO3进行或处理后得到信号DO4，对该信号进行采样，得到采样后的0、1数据流。图中0、1数据流上虚线框代表预设的时间窗，设置时间窗长度等于一个信号周期，对时间窗内的0、1信号进行统计，得到1信号所占比例，将该比例与1信号的比例门限进行比较，若大于比例门限，则认为感应模块进入距离L以内；否则认为未进入该距离。FIG. 15 is a schematic diagram of a distance control process using a pair of comparators and a low-frequency signal detection method in an embodiment of the present invention. As shown in Figure 14, A0 is the output signal of the amplifier. Its amplitude ranges from -A1 to +A1, and its corresponding distance is L. Assuming that the distance L needs to be controlled, first look up the correspondence table between the amplitude value and the distance to obtain the signal amplitude value at the distance. Then set the proportional threshold of the 1 signal to R1. According to R1, the setting of the high comparison level VG+ and the low comparison level VG- satisfies that within one cycle, the percentage of time that the output signal amplitude of the front-end device is greater than VG+ or less than VG- is equal to R1. Signal DO4 is obtained after OR processing is performed on the output signals DO2 and DO3 of the paired comparators, and the signal is sampled to obtain a sampled 0, 1 data stream. The dotted box on the 0 and 1 data streams in the figure represents the preset time window. Set the length of the time window to be equal to one signal period, and make statistics on the 0 and 1 signals in the time window to obtain the proportion of the 1 signal, and compare the proportion with 1 The proportional threshold of the signal is compared, if it is greater than the proportional threshold, it is considered that the sensing module has entered the distance L; otherwise, it is considered that the sensing module has not entered the distance.
图16为本发明实施例中使用单个比较器采用磁场数据低频信号检测方法进行解码处理的示意图。如图15所示，A0为放大器的输出信号。输入比较器的比较电平VG设置为放大器输入参考电平。比较器的输出信号直接用做被解码信号。可设置数字毛刺滤波器可对该输入信号进行毛刺滤除。按照编码格式将信号进行解码，得到低频磁场数据流信息。FIG. 16 is a schematic diagram of decoding processing using a single comparator and a low-frequency signal detection method of magnetic field data in an embodiment of the present invention. As shown in Figure 15, A0 is the output signal of the amplifier. The comparison level VG of the input comparator is set as the amplifier input reference level. The output signal of the comparator is directly used as the decoded signal. A digital glitch filter can be set to filter the input signal. The signal is decoded according to the encoding format to obtain the low-frequency magnetic field data flow information.
图17为本发明实施例中使用单个比较器采用低频信号检测方法进行距离控制处理的示意图。如图16所示，A0为放大器的输出信号。其幅度变化范围从-A1到+A1，其对应的距离为L。假设需要对距离L进行控制，则首先查找幅度值与距离的对应表，得到在该距离上的信号幅度值。再设置1信号的比例门限为R1。根据R1，比较电平VG的设置满足在一个周期内，前端装置输出信号幅度大于VG的时间百分比等于R1。对比较器的输出信号进行采样，得到采样后的0、1数据流。图中0、1数据流上虚线框代表预设的时间窗，设置时间窗长度等于一个信号周期，对时间窗内的0、1信号进行统计，得到1信号所占比例，将该比例与1信号的比例门限进行比较，若大于比例门限，则认为感应模块进入距离L以内；否则认为未进入该距离。FIG. 17 is a schematic diagram of distance control processing using a single comparator and using a low-frequency signal detection method in an embodiment of the present invention. As shown in Figure 16, A0 is the output signal of the amplifier. Its amplitude ranges from -A1 to +A1, and its corresponding distance is L. Assuming that the distance L needs to be controlled, first look up the correspondence table between the amplitude value and the distance to obtain the signal amplitude value at the distance. Then set the proportional threshold of the 1 signal to R1. According to R1, the setting of the comparison level VG satisfies that within one cycle, the percentage of time when the output signal amplitude of the front-end device is greater than VG is equal to R1. The output signal of the comparator is sampled to obtain the sampled 0, 1 data stream. The dotted box on the 0 and 1 data streams in the figure represents the preset time window. Set the length of the time window to be equal to one signal period, and make statistics on the 0 and 1 signals in the time window to obtain the proportion of the 1 signal, and compare the proportion with 1 The proportional threshold of the signal is compared, if it is greater than the proportional threshold, it is considered that the sensing module has entered the distance L; otherwise, it is considered that the sensing module has not entered the distance.
图3中的6个比较器可以配置成3对进行使用，同时进行解码、多个距离、距离区间的判断、控制。也可独立作为6个单独的比较器使用，同时进行进行解码、多个距离、距离区间的判断、控制。也可将其中部分比较器成对地使用，进行解码或距离、距离区间的判断、控制；将其中部分比较器独立地使用，进行解码或距离、距离区间的判断、控制。The 6 comparators in Figure 3 can be configured into 3 pairs for use, and simultaneously perform decoding, judgment and control of multiple distances and distance intervals. It can also be used independently as 6 separate comparators to simultaneously perform decoding, judgment and control of multiple distances and distance intervals. Some of the comparators can also be used in pairs for decoding or judgment and control of distances and distance intervals; some of the comparators can be used independently for decoding or judgment and control of distances and distance intervals.
实际上，前端装置可以根据需要配置一个至多个比较器，用于多个距离、多个距离区间的距离判断和控制、低频磁场信号解码。In fact, the front-end device can be configured with one or more comparators as required, for distance judgment and control of multiple distances and multiple distance intervals, and decoding of low-frequency magnetic field signals.
本发明提供的低频信号检测方法，能够减小电路噪声和环境噪声对低频信号检测及传输系统中所接收到的低频信号的干扰，从而提高低频交变磁场距离检测和控制的精度。The low-frequency signal detection method provided by the invention can reduce the interference of circuit noise and environmental noise to the low-frequency signal detection and low-frequency signal received in the transmission system, thereby improving the accuracy of low-frequency alternating magnetic field distance detection and control.
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.
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| CN201010166186.XACN103023584B (en) | 2010-05-10 | 2010-05-10 | A kind ofly to detect and the analog front-end device of transmission system for low frequency signal |
| PCT/CN2010/073717WO2011140730A1 (en) | 2010-05-10 | 2010-06-09 | Analog front end device for low frequency signal detection and transmission system |
| Application Number | Priority Date | Filing Date | Title |
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| CN201010166186.XACN103023584B (en) | 2010-05-10 | 2010-05-10 | A kind ofly to detect and the analog front-end device of transmission system for low frequency signal |
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| CN201010166186.XAActiveCN103023584B (en) | 2010-05-10 | 2010-05-10 | A kind ofly to detect and the analog front-end device of transmission system for low frequency signal |
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