技术领域technical field
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.
背景技术Background technique
随着TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)显示技术的不断发展，越来越多的新技术不断地被提出和应用。基于ADS(ADvanced Super Dimension Switch，AD-SDS，简称ADS，高级超维场转换技术)模式的TFT-LCD凭借其低功耗、宽视角等特点，得到了越来越多人们的关注。With the continuous development of TFT-LCD (Thin Film Transistor Liquid Crystal Display, Thin Film Transistor Liquid Crystal Display) display technology, more and more new technologies are constantly being proposed and applied. TFT-LCD based on ADS (ADvanced Super Dimension Switch, AD-SDS, referred to as ADS, advanced super-dimensional field switching technology) mode has attracted more and more people's attention due to its low power consumption and wide viewing angle.
ADS技术主要是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。采用ADS技术的TFT-LCD产品不仅在画面品质上有所提高，且具有高分辨率、高透过率、宽视角、高开口率、低色差、无挤压水波纹等优点。ADS technology mainly forms a multi-dimensional electric field through the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all aligned liquid crystal molecules between the slit electrodes and directly above the electrodes in the liquid crystal cell Both can generate rotation, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency. TFT-LCD products using ADS technology not only improve the picture quality, but also have the advantages of high resolution, high transmittance, wide viewing angle, high aperture ratio, low color difference, and no extrusion water ripple.
对于ADS型TFT-LCD而言，公共电极需要制作在阵列基板上，这就在ADS型TFT-LCD的阵列基板制作过程中需要额外增加一次形成公共电极的构图工艺。因此在现有技术中通常需要通过7次构图工艺制造ADS型TFT-LCD阵列基板，而每一次构图工艺中又分别包括成膜、曝光、显影、刻蚀和剥离等工艺。构图工艺的次数过多将直接导致显示装置产品的成本上升，因此如何能够进一步减少构图工艺的次数也就成为了人们日益关注的问题。For the ADS type TFT-LCD, the common electrode needs to be fabricated on the array substrate, which requires an additional patterning process for forming the common electrode during the fabrication process of the array substrate of the ADS type TFT-LCD. Therefore, in the prior art, seven patterning processes are usually required to manufacture the ADS type TFT-LCD array substrate, and each patterning process includes film formation, exposure, development, etching and stripping processes. Too many times of the patterning process will directly lead to an increase in the cost of the display device product, so how to further reduce the number of the patterning process has become a problem that people pay more and more attention to.
发明内容Contents of the invention
本发明的实施例提供一种阵列基板及其制造方法、显示装置，可以减少在阵列基板的制造过程中构图工艺的次数，有效降低产品的生产成本。Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can reduce the number of patterning processes in the manufacturing process of the array substrate and effectively reduce the production cost of the product.
为达到上述目的，本发明的实施例采用如下技术方案：In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:
本发明实施例的一方面，提供一种阵列基板制造方法，包括在透明基板上形成薄膜晶体管TFT和第一透明电极的步骤，形成所述第一透明电极的步骤包括：An aspect of the embodiments of the present invention provides a method for manufacturing an array substrate, including the step of forming a thin film transistor TFT and a first transparent electrode on a transparent substrate, and the step of forming the first transparent electrode includes:
形成金属氧化物薄膜和刻蚀阻挡层薄膜；Forming a metal oxide film and an etching barrier film;
通过一次构图工艺形成所述金属氧化物薄膜和所述刻蚀阻挡层的图形；forming the pattern of the metal oxide film and the etching barrier layer through a patterning process;
在所述金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。Metallization is performed on the pattern area of the metal oxide film to form a first transparent electrode.
本发明实施例的另一方面，提供一种阵列基板，包括薄膜晶体管TFT和第一透明电极，还包括：Another aspect of the embodiments of the present invention provides an array substrate, including a thin film transistor TFT and a first transparent electrode, and further includes:
依次形成于阵列基板表面的金属氧化物薄膜和刻蚀阻挡层薄膜；A metal oxide film and an etching stopper film are sequentially formed on the surface of the array substrate;
所述金属氧化物薄膜的图形和所述刻蚀阻挡层的图形通过一次构图工艺形成；The pattern of the metal oxide film and the pattern of the etching barrier layer are formed by a patterning process;
通过金属化处理的所述金属氧化物薄膜的图形区域包括所述第一透明电极。The pattern area of the metal oxide thin film processed by metallization includes the first transparent electrode.
本发明实施例的又一方面，提供一种显示装置，所述显示装置包括如上所述的阵列基板。Still another aspect of the embodiments of the present invention provides a display device, the display device comprising the above-mentioned array substrate.
本发明实施例提供的阵列基板以及制造方法、显示装置，采用一次构图工艺形成金属氧化物薄膜的图形和刻蚀阻挡层的图形，并在金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。这样一来，可以在一次构图工艺中分别形成金属氧化物薄膜的图形、刻蚀阻挡层的图形以及第一透明电极，与现有技术相比，可以将阵列基板制作过程中的构图工艺使用次数减少到5次，从而简化了产品的生产步骤，显著降低了产品的生产成本。The array substrate, the manufacturing method, and the display device provided by the embodiments of the present invention adopt a patterning process to form the pattern of the metal oxide film and the pattern of the etching barrier layer, and perform metallization treatment on the pattern area of the metal oxide film to form the first a transparent electrode. In this way, the pattern of the metal oxide film, the pattern of the etching barrier layer, and the first transparent electrode can be formed respectively in one patterning process. Reduced to 5 times, thereby simplifying the production steps of the product and significantly reducing the production cost of the product.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明实施例提供的一种阵列基板制造方法的流程示意图；FIG. 1 is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the present invention;
图2为本发明实施例提供的另一阵列基板制造方法的流程示意图；FIG. 2 is a schematic flowchart of another method for manufacturing an array substrate provided by an embodiment of the present invention;
图3为透明基板上形成栅金属层的结构示意图；3 is a schematic structural view of forming a gate metal layer on a transparent substrate;
图4为图3所示的阵列基板上形成金属氧化物薄膜和刻蚀阻挡层薄膜的结构示意图；4 is a schematic structural view of forming a metal oxide film and an etching barrier film on the array substrate shown in FIG. 3;
图5为图4所示的阵列基板形成有光刻胶的示意图；FIG. 5 is a schematic diagram of photoresist formed on the array substrate shown in FIG. 4;
图6为图5所示的阵列基板进行刻蚀后的结构示意图；FIG. 6 is a schematic structural view of the array substrate shown in FIG. 5 after etching;
图7为图6所示的阵列基板进行灰化后的结构示意图；FIG. 7 is a schematic structural view of the array substrate shown in FIG. 6 after ashing;
图8为图7所示的阵列基板进行金属化处理后的结构示意图；FIG. 8 is a schematic structural view of the array substrate shown in FIG. 7 after metallization treatment;
图9为图8所示的阵列基板上形成源漏金属层的结构示意图；FIG. 9 is a schematic structural diagram of forming a source-drain metal layer on the array substrate shown in FIG. 8;
图10为本发明实施例提供的一种阵列基板的结构示意图。FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明实施例提供的阵列基板制造方法，包括在透明基板上形成薄膜晶体管TFT和第一透明电极的步骤，如图1所示，形成第一透明电极的步骤包括：The method for manufacturing an array substrate provided by an embodiment of the present invention includes the step of forming a thin film transistor TFT and a first transparent electrode on a transparent substrate. As shown in FIG. 1 , the step of forming the first transparent electrode includes:
S101、形成金属氧化物薄膜和刻蚀阻挡层薄膜。S101, forming a metal oxide thin film and an etching stopper thin film.
其中，金属氧化物薄膜可以采用呈半导体特性的透明金属氧化物材料制作而成，例如，金属氧化物薄膜可以包括：InGaZnO、InGaO、ITZO、AlZnO中的至少一种。Wherein, the metal oxide thin film can be made of transparent metal oxide material with semiconductor characteristics, for example, the metal oxide thin film can include at least one of InGaZnO, InGaO, ITZO, and AlZnO.
S102、通过一次构图工艺形成金属氧化物薄膜的图形和刻蚀阻挡层的图形。S102, forming the pattern of the metal oxide film and the pattern of the etching stopper layer through one patterning process.
具体的，在依次形成有金属氧化物薄膜和刻蚀阻挡层薄膜的基板上可以通过一次构图工艺形成该金属氧化物薄膜和刻蚀阻挡层的图形，该刻蚀阻挡层的图形位于金属氧化物薄膜图形表面，且覆盖TFT的沟道区域。Specifically, the pattern of the metal oxide film and the etching barrier layer can be formed by a patterning process on the substrate sequentially formed with the metal oxide film and the etching barrier film, and the pattern of the etching barrier layer is located on the metal oxide layer. The surface of the thin film pattern covers the channel area of the TFT.
S103、在该金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。S103, performing metallization on the patterned area of the metal oxide film to form a first transparent electrode.
具体的，可以对外露的金属氧化物薄膜进行金属化处理，形成具有导体特性的金属氧化物薄膜，刻蚀阻挡层下未进行金属化处理的部分金属氧化物薄膜形成半导体有源层。Specifically, metallization may be performed on the exposed metal oxide film to form a metal oxide film with conductive properties, and a part of the metal oxide film under the barrier layer that has not been metallized is etched to form a semiconductor active layer.
其中，经过金属化处理的金属氧化物薄膜包括用于与TFT的源极电连接的源连接电极、用于与TFT的漏极电连接的漏连接电极以及第一透明电极，该漏连接电极与第一透明电极为一体结构。Wherein, the metal oxide thin film after metallization includes a source connection electrode for being electrically connected to the source of the TFT, a drain connection electrode for being electrically connected to the drain of the TFT, and a first transparent electrode, and the drain connection electrode is connected to the TFT. The first transparent electrode has an integrated structure.
本发明实施例提供的阵列基板制造方法，采用一次构图工艺形成金属氧化物薄膜的图形和刻蚀阻挡层的图形，并在金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。这样一来，可以在一次构图工艺中分别形成金属氧化物薄膜的图形、刻蚀阻挡层的图形以及第一透明电极，与现有技术相比，可以将阵列基板制作过程中的构图工艺使用次数减少到5次，从而简化了产品的生产步骤，显著降低了产品的生产成本。In the manufacturing method of the array substrate provided by the embodiment of the present invention, a patterning process is used to form the pattern of the metal oxide film and the pattern of the etching barrier layer, and metallization is performed on the pattern area of the metal oxide film to form the first transparent electrode. In this way, the pattern of the metal oxide film, the pattern of the etching barrier layer, and the first transparent electrode can be formed respectively in one patterning process. Reduced to 5 times, thereby simplifying the production steps of the product and significantly reducing the production cost of the product.
进一步地，本发明实施例提供的阵列基板制造方法，如图2所示，具体包括：Further, the method for manufacturing an array substrate provided by an embodiment of the present invention, as shown in FIG. 2 , specifically includes:
S201、在透明基板上形成栅线、栅电极以及公共电极线。S201 , forming gate lines, gate electrodes and common electrode lines on a transparent substrate.
在阵列基板的实际生产过程当中，透明基板具体可以是采用玻璃或透明树脂等具有一定坚固性的透明材料制成。在透明基板上需要采用一次构图工艺以形成栅线、栅电极以及公共电极线等结构的图形。In the actual production process of the array substrate, the transparent substrate may be made of a transparent material with certain firmness, such as glass or transparent resin. A patterning process is required on the transparent substrate to form patterns of structures such as gate lines, gate electrodes, and common electrode lines.
例如，可以采用等离子增强化学气相沉积(PECVD)、磁控溅射、热蒸发或其它成膜方法，在透明基板上形成金属层。其中，该金属层可以是钼、铝、铝铷合金、钨、铬、铜等金属形成的单层薄膜，也可以是以上金属多层形成的多层薄膜。在该金属层的表面形成有光刻胶，通过具有特定图案的掩膜板进行曝光显影以使光刻胶产生图案，剥离掉未覆盖光刻胶处的金属层，如图3所示，最终在透明基板10的表面形成栅线(图3中未示出)、栅电极111以及公共电极线112的图案。For example, the metal layer can be formed on the transparent substrate by using plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods. Wherein, the metal layer may be a single-layer film formed of metals such as molybdenum, aluminum, aluminum-rubidium alloy, tungsten, chromium, copper, etc., or a multi-layer film formed by multiple layers of the above metals. A photoresist is formed on the surface of the metal layer, which is exposed and developed through a mask with a specific pattern so that the photoresist produces a pattern, and the metal layer not covered by the photoresist is peeled off, as shown in Figure 3, finally Patterns of gate lines (not shown in FIG. 3 ), gate electrodes 111 and common electrode lines 112 are formed on the surface of the transparent substrate 10 .
S202、在透明基板、栅线、栅电极以及公共电极线上形成栅绝缘层。S202, forming a gate insulating layer on the transparent substrate, the gate lines, the gate electrodes and the common electrode lines.
如图4所示，图4为TFT区域的层级结构示意图，可见，在该区域内，在形成有栅电极111的透明基板10上形成有厚度均一的栅绝缘层12。As shown in FIG. 4 , which is a schematic diagram of the hierarchical structure of the TFT region, it can be seen that in this region, a gate insulating layer 12 with a uniform thickness is formed on the transparent substrate 10 on which the gate electrode 111 is formed.
S203、在依次形成有金属氧化物薄膜和刻蚀阻挡层薄膜的基板上通过一次构图工艺形成该金属氧化物薄膜和该刻蚀阻挡层的图形，该刻蚀阻挡层的图形位于金属氧化物薄膜图形表面，且覆盖TFT的沟道区域。S203. Form the pattern of the metal oxide film and the etching barrier layer on the substrate sequentially formed with the metal oxide film and the etching barrier film through a patterning process, the pattern of the etching barrier layer is located on the metal oxide film pattern surface, and cover the channel region of the TFT.
具体的，同样如图4所示，在形成有栅绝缘层12的基板上还依次形成有金属氧化物薄膜13和刻蚀阻挡层薄膜14。其中，金属氧化物薄膜可以采用呈半导体特性的透明金属氧化物材料制作而成，例如，金属氧化物薄膜可以包括：InGaZnO、InGaO、ITZO、AlZnO中的至少一种。刻蚀阻挡层薄膜14可以是致密的氮化硅、氧化硅、氮氧化硅等材料。Specifically, as also shown in FIG. 4 , a metal oxide film 13 and an etching stopper film 14 are sequentially formed on the substrate on which the gate insulating layer 12 is formed. Wherein, the metal oxide thin film can be made of transparent metal oxide material with semiconductor characteristics, for example, the metal oxide thin film can include at least one of InGaZnO, InGaO, ITZO, and AlZnO. The etch barrier film 14 can be dense silicon nitride, silicon oxide, silicon oxynitride and other materials.
对这样一种结构的基板采用构图工艺进行处理，首先，如图5所示，在刻蚀阻挡层薄膜14的表面形成有光刻胶50，通过曝光显影得到如图5所示的光刻胶形状。其中，该光刻胶50在TFT沟道对应区域处的厚度大于其余区域，这样一来可以保证在一次构图之后TFT沟道区域具有仍然刻蚀阻挡层，防止电极之间产生短路。此外，光刻胶50覆盖刻蚀阻挡层薄膜14的部分区域，该区域即为TFT的源漏极以及第一透明电极所在区域。The substrate of such a structure is processed by a patterning process. First, as shown in FIG. 5, a photoresist 50 is formed on the surface of the etching barrier film 14, and the photoresist as shown in FIG. 5 is obtained by exposure and development. shape. Wherein, the thickness of the photoresist 50 in the region corresponding to the TFT channel is greater than that in other regions, so as to ensure that the TFT channel region still has an etching barrier layer after one patterning, and prevent short circuits between electrodes. In addition, the photoresist 50 covers a part of the etching barrier film 14 , which is where the source and drain electrodes of the TFT and the first transparent electrode are located.
对形成有光刻胶50的基板进行刻蚀，如图6所示，通过刻蚀工艺可以刻蚀掉金属氧化物薄膜13和刻蚀阻挡层薄膜14，直至暴露出栅绝缘层12，仅保留光刻胶50覆盖区域的部分金属氧化物薄膜13和刻蚀阻挡层薄膜14。The substrate formed with the photoresist 50 is etched, as shown in FIG. 6, the metal oxide film 13 and the etching barrier film 14 can be etched away through the etching process until the gate insulating layer 12 is exposed, leaving only The photoresist 50 covers part of the metal oxide film 13 and the etching barrier film 14 in the area.
进一步地，采用灰化工艺处理上述基板。通过灰化工艺的处理，光刻胶50的厚度将整体降低，将外露的刻蚀阻挡层薄膜14刻蚀掉，最终形成如图7所示的基板，外露出金属氧化物薄膜13，可见，通过灰化处理掉了大部分光刻胶，仅保留了原厚度较大部分的光刻胶，即覆盖TFT沟道区域的光刻胶。Further, the above-mentioned substrate is treated by an ashing process. Through the ashing process, the thickness of the photoresist 50 will be reduced as a whole, and the exposed etching barrier film 14 will be etched away, finally forming the substrate as shown in FIG. 7, with the exposed metal oxide film 13. It can be seen that Most of the photoresist is removed by ashing, and only the photoresist with a larger original thickness remains, that is, the photoresist covering the channel region of the TFT.
S204、对外露的金属氧化物薄膜进行金属化处理，形成具有导体特性的金属氧化物薄膜，刻蚀阻挡层下未进行金属化处理的部分金属氧化物薄膜形成半导体有源层。S204 , performing metallization on the exposed metal oxide film to form a metal oxide film with conductive properties, and etching a part of the metal oxide film under the barrier layer that has not been metallized to form a semiconductor active layer.
具体的，如图8所示，可以通过等离子工艺或退火工艺等对外露的金属氧化物薄膜13进行金属化处理。该步骤可以通过以下三种方式实现。Specifically, as shown in FIG. 8 , the exposed metal oxide film 13 may be metallized through a plasma process or an annealing process. This step can be achieved in the following three ways.
方式一：将具有图7所示结构的基板置于真空腔室中加热到一定温度，并保持一定时间后在空气中冷却。优选的，该一定温度值可以为200～300℃，保持的一定时间可以为20～40分钟。Method 1: heat the substrate with the structure shown in FIG. 7 in a vacuum chamber to a certain temperature, keep it for a certain period of time, and then cool it in the air. Preferably, the certain temperature value may be 200-300° C., and the certain time of keeping may be 20-40 minutes.
方式二：将具有图7所示结构的基板置于还原性气氛中在200～400℃进行热处理。Method 2: heat-treat the substrate with the structure shown in FIG. 7 in a reducing atmosphere at 200-400° C.
方式三：将具有图7所示结构的基板置于真空腔室中，采用等离子体处理的方法，一般功率为1500～2500W，压力为1000～2000mtorr，有氢气(H2)等离子体和氧气(O2)等离子体处理两种方法，使用氢气等离子体或氧气等离子体处理时，氢气或氧气的气体流量一般为5000～15000sccm。Method 3: Place the substrate with the structure shown in Figure 7 in a vacuum chamber, and adopt plasma treatment method, the general power is 1500-2500W, the pressure is 1000-2000mtorr, there are hydrogen (H2 ) plasma and oxygen ( There are two methods of O2 ) plasma treatment. When using hydrogen plasma or oxygen plasma treatment, the gas flow rate of hydrogen or oxygen is generally 5000-15000 sccm.
通过上述三种方式，可以使被金属化处理的金属氧化物薄膜13的载流子浓度提高，呈现导体特性，从而可以取代现有的像素电极材料。而刻蚀阻挡层14下未进行金属化处理的金属氧化物薄膜的载流子浓度较低，呈现半导体特性，即为半导体有源层134。Through the above-mentioned three methods, the carrier concentration of the metallized metal oxide thin film 13 can be increased, and the conductor characteristic can be exhibited, so that the existing pixel electrode material can be replaced. On the other hand, the metal oxide thin film under the etching barrier layer 14 without metallization treatment has a lower carrier concentration and exhibits semiconductor characteristics, that is, the semiconductor active layer 134 .
其中，经过金属化处理的金属氧化物薄膜13具体可以包括用于与TFT的源极电连接的源连接电极131、用于与TFT的漏极电连接的漏连接电极132以及第一透明电极133，漏连接电极132与第一透明电极133为一体结构。Wherein, the metal oxide thin film 13 after metallization may specifically include a source connection electrode 131 for electrically connecting with the source of the TFT, a drain connection electrode 132 for electrically connecting with the drain of the TFT, and a first transparent electrode 133 , the drain connection electrode 132 and the first transparent electrode 133 are integrally structured.
S205、在形成有刻蚀阻挡层和第一透明电极的基板上形成数据线、TFT的源极以及TFT的漏极。S205 , forming a data line, a source electrode of a TFT, and a drain electrode of a TFT on the substrate formed with the etch stop layer and the first transparent electrode.
具体的，如图9所示，基板上形成有位于源连接电极131之上的TFT的源极151、位于漏连接电极132之上的TFT的漏极152以及与TFT的源极151电连接的数据线(图9中未示出)。Specifically, as shown in FIG. 9 , the source electrode 151 of the TFT located on the source connection electrode 131, the drain electrode 152 of the TFT located on the drain connection electrode 132, and the TFT electrically connected to the source electrode 151 are formed on the substrate. data lines (not shown in Figure 9).
进一步地，可以采用构图工艺对形成有如图9所示结构的阵列基板进行进一步处理。例如，可以通过灰化工艺使得TFT的源极151与TFT的漏极152的厚度整体降低，直至TFT的源极151与TFT的漏极152的厚度与蚀阻挡层14的厚度相同。这样一来，消除了阵列基板上TFT的源极151、TFT的漏极152与蚀阻挡层14的段差，增加了膜层的平整性，进一步提高了显示装置产品的质量。Further, the array substrate formed with the structure shown in FIG. 9 can be further processed by using a patterning process. For example, the thicknesses of the TFT source 151 and the TFT drain 152 can be reduced overall through an ashing process until the thicknesses of the TFT source 151 and the TFT drain 152 are equal to the thickness of the etch stop layer 14 . In this way, the level difference between the source electrode 151 of the TFT, the drain electrode 152 of the TFT and the etch stop layer 14 on the array substrate is eliminated, the flatness of the film layer is increased, and the quality of the display device product is further improved.
S206、在形成有数据线、TFT的源极以及TFT的漏极的基板上形成含有过孔的钝化层，该过孔贯穿钝化层和栅绝缘层，露出公共电极线。S206 , forming a passivation layer including a via hole on the substrate formed with the data line, the source electrode of the TFT, and the drain electrode of the TFT, and the via hole penetrates through the passivation layer and the gate insulating layer to expose the common electrode line.
S207、在钝化层上形成第二透明电极，该第二透明电极通过过孔与公共电极线电连接。S207, forming a second transparent electrode on the passivation layer, where the second transparent electrode is electrically connected to the common electrode line through a via hole.
需要说明的是，在本发明实施例中，第一透明电极可以为像素电极，第二透明电极可以为公共电极。It should be noted that, in the embodiment of the present invention, the first transparent electrode may be a pixel electrode, and the second transparent electrode may be a common electrode.
具体的，TFT的源、漏电极、数据线、钝化层和第二透明电极分别可以通过三次构图工艺形成。Specifically, the source electrode, the drain electrode, the data line, the passivation layer and the second transparent electrode of the TFT can be formed through three patterning processes respectively.
采用现有的成膜方法如磁控溅射或热蒸发等方法在基板上形成金属薄膜，并通过构图工艺形成与源连接电极131电连接的TFT的源极151，和与漏连接电极132电连接的TFT的漏极152以及数据线的图案。其中，形成源、漏电极和数据线的金属薄膜可以是钼、铝、铝铷合金、钨、铬、铜等金属形成的单层薄膜，也可以是以上金属多层形成的多层薄膜。Adopt existing film-forming methods such as magnetron sputtering or thermal evaporation to form a metal thin film on the substrate, and form the source electrode 151 of the TFT electrically connected to the source connection electrode 131 through a patterning process, and electrically connected to the drain connection electrode 132. The drain electrode 152 of the connected TFT and the pattern of the data line. Wherein, the metal film forming the source, drain electrode and data line can be a single-layer film formed of metals such as molybdenum, aluminum, aluminum-rubidium alloy, tungsten, chromium, copper, etc., or a multi-layer film formed by multiple layers of the above metals.
接着，再在基板上通过化学气相沉积或热蒸发等方法制备绝缘薄膜形成钝化层16，该钝化层上通过构图工艺形成有过孔A，第二透明电极17可以通过过孔A与公共电极线112电连接。其中，该绝缘薄膜可以采用氮化硅、氧化硅或氮氧化硅的单层薄膜，也可以采用上述材料的多层形成的多层薄膜。Next, an insulating film is prepared on the substrate by methods such as chemical vapor deposition or thermal evaporation to form a passivation layer 16. A via hole A is formed on the passivation layer through a patterning process, and the second transparent electrode 17 can communicate with the common electrode through the via hole A. The electrode lines 112 are electrically connected. Wherein, the insulating film may be a single-layer film of silicon nitride, silicon oxide or silicon oxynitride, or a multi-layer film formed of multiple layers of the above materials.
最后，通过磁控溅射或热蒸发等方法形成透明导电薄膜，并通过构图工艺形成条状的第二透明电极17，最终形成如图10所示的阵列基板。其中，第一透明电极133与第二透明电极17之间可以形成多维电场。第二透明电极17的材料可以是ITO、ZnO、InGaZnO、InZnO、InGaO等透明导电材料。Finally, a transparent conductive film is formed by magnetron sputtering or thermal evaporation, and strip-shaped second transparent electrodes 17 are formed by a patterning process, finally forming an array substrate as shown in FIG. 10 . Wherein, a multi-dimensional electric field may be formed between the first transparent electrode 133 and the second transparent electrode 17 . The material of the second transparent electrode 17 may be a transparent conductive material such as ITO, ZnO, InGaZnO, InZnO, InGaO and the like.
本发明实施例提供的阵列基板制造方法，采用一次构图工艺形成金属氧化物薄膜的图形和刻蚀阻挡层的图形，并在金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。这样一来，可以在一次构图工艺中分别形成金属氧化物薄膜的图形、刻蚀阻挡层的图形以及第一透明电极，与现有技术相比，可以将阵列基板制作过程中的构图工艺使用次数减少到5次，从而简化了产品的生产步骤，显著降低了产品的生产成本。In the manufacturing method of the array substrate provided by the embodiment of the present invention, a patterning process is used to form the pattern of the metal oxide film and the pattern of the etching barrier layer, and metallization is performed on the pattern area of the metal oxide film to form the first transparent electrode. In this way, the pattern of the metal oxide film, the pattern of the etching barrier layer, and the first transparent electrode can be formed respectively in one patterning process. Reduced to 5 times, thereby simplifying the production steps of the product and significantly reducing the production cost of the product.
本发明实施例提供的阵列基板，如图10所示，包括薄膜晶体管TFT和第一透明电极133，还包括：The array substrate provided by the embodiment of the present invention, as shown in FIG. 10 , includes a thin film transistor TFT and a first transparent electrode 133, and further includes:
依次形成于阵列基板表面的金属氧化物薄膜13和刻蚀阻挡层薄膜14。The metal oxide thin film 13 and the etching stopper thin film 14 are sequentially formed on the surface of the array substrate.
其中，金属氧化物薄膜13的图形和刻蚀阻挡层14的图形通过一次构图工艺形成。Wherein, the pattern of the metal oxide thin film 13 and the pattern of the etching barrier layer 14 are formed through one patterning process.
通过金属化处理的金属氧化物薄膜13的图形区域包括第一透明电极133。The pattern area of the metal oxide thin film 13 processed by metallization includes the first transparent electrode 133 .
该阵列基板可以为采用上述各个实施例说明的阵列基板的制造方法制得的阵列基板。The array substrate may be an array substrate manufactured by using the method for manufacturing an array substrate described in the foregoing embodiments.
该阵列基板具体包括TFT、第一透明电极133和第二透明电极17。其中，源连接电极131、漏连接电极132、第一透明电极133以及半导体有源层134均是由同一金属氧化薄膜通过一次构图工艺形成的，其中，第一透明电极133由金属氧化物薄膜通过金属化处理得到，半导体有源层134由未被金属化处理的金属氧化物薄膜形成。The array substrate specifically includes TFTs, a first transparent electrode 133 and a second transparent electrode 17 . Among them, the source connection electrode 131, the drain connection electrode 132, the first transparent electrode 133 and the semiconductor active layer 134 are all formed by the same metal oxide film through a patterning process, wherein the first transparent electrode 133 is formed by the metal oxide film. Metallization results in that the semiconductor active layer 134 is formed of a metal oxide film that has not been metallized.
需要说明的是，上述各个实施例中是以像素电极和公共电极异层设置的阵列基板为例进行的说明。可以理解的是，以上实施例中像素电极和公共电极同层设置在阵列基板上时，也可以通过构图工艺、金属化处理等在一层金属氧化物薄膜上形成有源层、像素电极和公共电极的图案。因此，本发明实施例提供的阵列基板通过适当的变形也可以适用于IPS(In-Plane Switching，平面内开关)型和AD-SDS型的TFT阵列基板。It should be noted that, in the above-mentioned embodiments, the description is made by taking an array substrate with pixel electrodes and common electrodes arranged in different layers as an example. It can be understood that, when the pixel electrode and the common electrode are arranged on the same layer in the above embodiment, the active layer, the pixel electrode and the common electrode can also be formed on a layer of metal oxide film through patterning process, metallization treatment, etc. The pattern of the electrodes. Therefore, the array substrate provided by the embodiment of the present invention can also be applied to IPS (In-Plane Switching, in-plane switching) type and AD-SDS type TFT array substrate through appropriate deformation.
本发明实施例提供的阵列基板，采用一次构图工艺形成金属氧化物薄膜的图形和刻蚀阻挡层的图形，并在金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。这样一来，可以在一次构图工艺中分别形成金属氧化物薄膜的图形、刻蚀阻挡层的图形以及第一透明电极，与现有技术相比，可以将阵列基板制作过程中的构图工艺使用次数减少到5次，从而简化了产品的生产步骤，显著降低了产品的生产成本。The array substrate provided by the embodiment of the present invention adopts a single patterning process to form the pattern of the metal oxide thin film and the pattern of the etching barrier layer, and performs metallization treatment on the pattern area of the metal oxide thin film to form the first transparent electrode. In this way, the pattern of the metal oxide film, the pattern of the etching barrier layer, and the first transparent electrode can be formed respectively in one patterning process. Reduced to 5 times, thereby simplifying the production steps of the product and significantly reducing the production cost of the product.
进一步地，如图10所示，刻蚀阻挡层14的图形可以位于金属氧化物薄膜13图形表面，且覆盖TFT的沟道区域。Further, as shown in FIG. 10 , the pattern of the etching stopper layer 14 may be located on the surface of the pattern of the metal oxide film 13 and cover the channel region of the TFT.
通过金属化处理的金属氧化物薄膜13的图形区域还可以包括：The pattern area of the metal oxide film 13 processed by metallization can also include:
半导体有源层134，该半导体有源层134可以位于刻蚀阻挡层14下。The semiconductor active layer 134 may be located under the etch stop layer 14 .
以及用于与TFT的源极151电连接的源连接电极131、用于与TFT的漏极152电连接的漏连接电极132以及第一透明电极133，该漏连接电极132与第一透明电极133可以为一体结构。And the source connection electrode 131 for being electrically connected with the source electrode 151 of TFT, the drain connection electrode 132 for being electrically connected with the drain electrode 152 of TFT and the first transparent electrode 133, and the drain connection electrode 132 is connected with the first transparent electrode 133 Can be integrated structure.
进一步地，阵列基板还可以包括：Further, the array substrate may also include:
位于透明基板10和金属氧化物薄膜13之间的栅线(图10中未示出)、栅电极111以及公共电极线112。Gate lines (not shown in FIG. 10 ), gate electrodes 111 and common electrode lines 112 are located between the transparent substrate 10 and the metal oxide film 13 .
位于栅线、栅电极111以及公共电极线112和金属氧化物薄膜13之间的栅绝缘层12。The gate insulating layer 12 is located between the gate line, the gate electrode 111 , the common electrode line 112 and the metal oxide film 13 .
阵列基板还可以包括：Array substrates can also include:
位于刻蚀阻挡层14和第一透明电极133的表面的数据线(图10中未示出)、TFT的源极151以及TFT的漏极152。The data line (not shown in FIG. 10 ), the source electrode 151 of the TFT, and the drain electrode 152 of the TFT are located on the surface of the etching stopper layer 14 and the first transparent electrode 133 .
位于数据线、TFT的源极151以及TFT的漏极152的表面的含有过孔A的钝化层16，该过孔A贯穿钝化层16和栅绝缘层12，露出公共电极线112。The passivation layer 16 on the surface of the data line, the source electrode 151 of the TFT and the drain electrode 152 of the TFT contains a via hole A, and the via hole A penetrates the passivation layer 16 and the gate insulating layer 12 to expose the common electrode line 112 .
位于钝化层表面16的第二透明电极17，该第二透明电极17通过过孔A与公共电极线112电连接。The second transparent electrode 17 located on the surface 16 of the passivation layer is electrically connected to the common electrode line 112 through the via hole A.
在本发明实施例中，第一透明电极133可以为像素电极，第二透明电极17可以为公共电极。In the embodiment of the present invention, the first transparent electrode 133 may be a pixel electrode, and the second transparent electrode 17 may be a common electrode.
其中，金属氧化物薄膜13可以采用呈半导体特性的透明金属氧化物材料，例如，可以包括：InGaZnO、InGaO、ITZO、AlZnO中的至少一种。Wherein, the metal oxide thin film 13 may adopt a transparent metal oxide material with semiconductor characteristics, for example, may include: at least one of InGaZnO, InGaO, ITZO, and AlZnO.
本发明实施例提供的显示装置，包括如上所述的阵列基板。A display device provided by an embodiment of the present invention includes the above-mentioned array substrate.
该阵列基板具体包括TFT、第一透明电极和第二透明电极。其中，源连接电极、漏连接电极、第一透明电极以及半导体有源层均是由同一金属氧化薄膜通过一次构图工艺形成的，其中，第一透明电极由金属氧化物薄膜通过金属化处理得到，半导体有源层由未被金属化处理的金属氧化物薄膜形成。The array substrate specifically includes TFTs, first transparent electrodes and second transparent electrodes. Wherein, the source connection electrode, the drain connection electrode, the first transparent electrode and the semiconductor active layer are all formed by the same metal oxide film through a patterning process, wherein the first transparent electrode is obtained by metallizing the metal oxide film, The semiconductor active layer is formed of a metal oxide film that has not been metallized.
需要说明的是本发明所提供的显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。It should be noted that the display device provided by the present invention can be: liquid crystal panel, electronic paper, OLED panel, liquid crystal TV, liquid crystal display, digital photo frame, mobile phone, tablet computer and other products or components with any display function.
本发明实施例提供的显示装置，包括阵列基板，该阵列基板采用一次构图工艺形成金属氧化物薄膜的图形和刻蚀阻挡层的图形，并在金属氧化物薄膜的图形区域进行金属化处理以形成第一透明电极。这样一来，可以在一次构图工艺中分别形成金属氧化物薄膜的图形、刻蚀阻挡层的图形以及第一透明电极，与现有技术相比，可以将阵列基板制作过程中的构图工艺使用次数减少到5次，从而简化了产品的生产步骤，显著降低了产品的生产成本。The display device provided by the embodiment of the present invention includes an array substrate, the array substrate adopts a patterning process to form the pattern of the metal oxide film and the pattern of the etching barrier layer, and performs metallization treatment on the pattern area of the metal oxide film to form the first transparent electrode. In this way, the pattern of the metal oxide film, the pattern of the etching barrier layer, and the first transparent electrode can be formed respectively in one patterning process. Reduced to 5 times, thereby simplifying the production steps of the product and significantly reducing the production cost of the product.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
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| CN201210507742.4ACN103021939B (en) | 2012-11-30 | 2012-11-30 | Array substrate, manufacture method of array substrate and display device |
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| CN201210507742.4ACN103021939B (en) | 2012-11-30 | 2012-11-30 | Array substrate, manufacture method of array substrate and display device |
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