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CN103000530B - Manufacturing method of top-gate oxide thin-film transistor - Google Patents

Manufacturing method of top-gate oxide thin-film transistor
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CN103000530B
CN103000530BCN201210452913.8ACN201210452913ACN103000530BCN 103000530 BCN103000530 BCN 103000530BCN 201210452913 ACN201210452913 ACN 201210452913ACN 103000530 BCN103000530 BCN 103000530B
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oxide
oxide semiconductor
semiconductor layer
source electrode
grid
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CN103000530A (en
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刘萍
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Shenzhen Danbang Investment Group Co Ltd
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Abstract

The invention discloses a manufacturing method of a top-gate oxide thin-film transistor. The top-gate oxide thin-film transistor comprises an oxide semiconductor layer, a source electrode and a drain electrode, the source electrode and the drain electrode respectively contact with the oxide semiconductor layer, and the oxide semiconductor layer is made of indium oxide, gallium oxide, zinc oxide or stannic oxide or binary or multibasic oxide of indium, gallium, zinc and stannum. The source electrode, the drain electrode and the oxide semiconductor layer are radiated by a variable magnetic field. Field effect migration rate of the top-gate thin-film transistor is high, and current crowding of the output characteristics is avoided when the drain electrode is at low voltage.

Description

The manufacture method of top grid oxide film transistor
Technical field
The present invention relates to top gate type thin film transistor field, particularly relate to the manufacture method of top grid oxide film transistor.
Background technology
Compared with the current non-crystalline silicon tft (Thin Film Transistor (TFT)) extensively adopted in liquid crystal display active driving matrix, oxide semiconductor TFT has following advantage: (1) field-effect mobility is high; (2) on-off ratio is high; (3) preparation technology's temperature is low; (4) can make large area amorphous film, uniformity is good, has well consistent electrology characteristic; (5) affect by visible ray little, stablize than amorphous silicon and OTFT; (6) transparent devices can be made into.In flat display field, oxide TFT technology almost meets all requirements comprising AMOLED driving, fast many display modes such as jumbotron liquid crystal display, 3D display.In Flexible Displays, backing material can not bear high temperature, and preparation technology's temperature of oxide TFT is low, compatible with flexible substrate, thus possesses greater advantage.
The advantage of the top-gate thin-film transistors of based oxide semiconductor has: photoetching process number of times is few, and manufacturing process is simple, low cost of manufacture; Parasitic capacitance between grid and source-drain electrode is little; There is not the problem of Step Coverage in reciprocal cross stack structure, gate insulator can be very thin, and grid can be thicker, is conducive to the signal delay that reduction RC causes; Active layer also can be very thin, is conducive to reducing active layer to the absorption of light, reduces light to the impact of TFT performance; Be applicable to R2R technique (volume to volume technique).
But the performance of current top-gate thin-film transistors device is lower, and it shows: 1, the field-effect mobility of transistor is lower; 2, the output characteristic of TFT is when low drain voltage, there will be current crowding phenomenon.In addition, current electrode material has the work function do not matched with active layer semi-conducting material.
Summary of the invention
In order to solve the problems of the technologies described above, to make the field-effect mobility of transistor higher, and Thin Film Transistor (TFT) at low drain voltage time, be not easy to occur current crowding phenomenon, the invention provides the manufacture method of top grid oxide film transistor.
The manufacture method of top grid oxide film transistor, described top grid oxide film transistor comprises oxide semiconductor layer, source electrode and drain electrode, described source electrode contacts with oxide semiconductor layer respectively with drain electrode, described oxide semiconductor layer adopts indium oxide, gallium oxide, zinc oxide or tin oxide or indium, gallium, zinc, the binary of tin or multivariant oxide, adopts the magnetic field of change to carry out radiation to source electrode, drain electrode and oxide semiconductor layer.
After adopting such scheme, the magnetic field of change is at source electrode, drain electrode produces induced current, source electrode and drain electrode are heated rapidly, also heated with the oxide semiconductor layer of source electrode and drain contact, electric conductivity improves, conductivity increases, under the radiation in the magnetic field of change, also produce induced current and heated, not only heat by the conduction of source electrode and drain electrode with the oxide semiconductor layer of source electrode and drain contact like this, also sensed heating, temperature raises rapidly, make ionic bond fracture weak between metal and oxygen, carrier concentration improves rapidly, oxide semiconductor layer, and the conductance of oxide semiconductor layer and source electrode and drain contact areas significantly rises, in addition, heating make the material of source electrode and drain electrode the diffusion of oxide and the formation of the region alloy that contacts with each other also reduce source electrode and drain electrode and the contact resistance of oxide semiconductor layer (source electrode and drain respectively and define good contact between oxide semiconductor layer), reduce further source electrode and total series resistance that drains.Like this, the field-effect mobility of transistor can be higher, because: when source drain series resistance is larger, the drain voltage of applying has a larger voltage drop of can not ignore in higher source drain series resistance, thus causes the decline of field-effect mobility; Meanwhile, also can reduce or avoid occurring current crowding phenomenon, because: when source drain series resistance is larger, when the output characteristic of TFT is pressed at Low dark curient, there will be current crowding phenomenon.
In more excellent scheme, the substrate of described top grid oxide film transistor adopts flexible material, and described flexible material comprises plastics.
In more excellent scheme, to source electrode, drain electrode and and the oxide semiconductor layer of source electrode and drain contact adopt laser auxiliary heating.
In more excellent scheme, also comprise the steps:
1.1) depositing conducting layer on substrate;
1.2) etch described conductive layer and form source electrode and drain electrode;
1.3) deposition oxide semiconductive thin film in described substrate, source electrode and drain electrode;
1.4) hydrofluoric acid wet etching oxide semiconductor thin-film is adopted to form oxide semiconductor layer;
1.5) on oxide semiconductor layer, deposition forms gate insulator;
1.6) on gate insulator, deposition forms grid;
In step 1.4) and step 1.6) between adopt the magnetic field of change to carry out radiation to source electrode, drain electrode and oxide semiconductor layer.
In more excellent scheme, described step 1.5) comprising:
Deposition of gate insulation film on oxide semiconductor layer;
Deposition of gate metal level on grid insulating film;
Etching grid metal level forms grid;
Take grid as mask, etching grid insulation film forms gate insulator.
In more excellent scheme, adopt magnetron sputtering to form oxide semiconductor thin-film, magnetic control spattering target is by the equal In of molar percentage2o3, Ga2o3, ZnO composition, the thickness of oxide semiconductor thin-film is 10-2000nm.
In more excellent scheme, the material of source electrode and drain electrode adopts a kind of in titanium, silver, gold, chromium, aluminium, copper, molybdenum, tantalum, tungsten or more than one alloy or source electrode and drain electrode to adopt nesa coating as ITO, IZO.Because above-mentioned material has the work function matched with active layer semi-conducting material, thus can reduce contact berrier, and be beneficial to the injection of charge carrier, thus reduce ohmic contact resistance, improve the performance of device.
In more excellent scheme, also comprise the steps:
2.1) deposition oxide semiconductive thin film on substrate;
2.2) hydrofluoric acid wet etching oxide semiconductor thin-film is adopted to form oxide semiconductor layer;
2.3) depositing conducting layer on oxide semiconductor layer;
2.4) etch described conductive layer and form source electrode and drain electrode;
2.5) in described oxide semiconductor layer, source electrode and drain electrode, deposition forms gate insulator;
2.6) on gate insulator, deposition forms grid;
In step 2.4) and step 2.5) between adopt the magnetic field of change to carry out radiation to source electrode, drain electrode and oxide semiconductor layer.
In more excellent scheme, adopt magnetron sputtering to form oxide semiconductor thin-film, magnetic control spattering target is by the equal In of molar percentage2o3, Ga2o3, ZnO composition, the thickness of oxide semiconductor thin-film is 10-2000nm.
In more excellent scheme, the carrier concentration of oxide semiconductor thin-film is less than 1015cm-3, after the magnetic field radiation of change, be greater than 10 with the carrier concentration of the oxide semiconductor layer of source electrode and drain contact20cm-3.
Carrier concentration in such scheme control oxide semiconductive thin film, the carrier concentration in oxide semiconductor thin-film and source-drain electrode carrier concentration is made to have 2 orders of magnitude, there is the difference of more than 5 orders of magnitude further, utilize the magnetic field of change to source electrode, drain electrode and and the method that heats of the oxide semiconductor layer of source electrode and drain contact, greatly low series resistance between source electrode and drain electrode.Such scheme is rapid to the heating of source electrode, drain electrode and oxide semiconductor layer, effectively can reduce technological temperature, keeps substrate to be in low-temperature condition, thus can adopt flexible base, board, and can reduce technology difficulty, reduce production cost.
Accompanying drawing explanation
Fig. 1 is the generalized section of the top grid oxide film transistor of an embodiment of the present invention;
Fig. 2 is the generalized section of the top grid oxide film transistor of the another kind of embodiment of the present invention.
Embodiment
Below with reference to accompanying drawing, specific embodiments of the invention are described in further detail.
Embodiment 1
As shown in Figure 1, a kind of top grid oxide film transistor of embodiment, comprise substrate 1, form source electrode 3 on substrate 1 and drain electrode 4, be formed in source electrode 3, the oxide semiconductor layer 2 drained on 4 and substrate 1, gate insulator 5 on oxide semiconductor layer 2, and the grid 5 on gate insulator 5, oxide semiconductor layer 2 comprises the channel region 21 corresponding with area of grid, and channel region 21 both sides respectively with source electrode 3 and 4 regions contacted 22 and the region 23 of draining, channel region 21 is between source electrode 3 and drain electrode 4, wherein, grid 6 can form autoregistration with insulating barrier 5 and channel region 21.
The manufacture method of the top grid oxide film transistor of the present embodiment comprises the following steps:
1.1, substrate 1 can be that glass, quartz, silicon chip or other flexible base, board are as plastics, stainless steel etc., deposition forms conductive layer on substrate 1, depositional mode can adopt thermal evaporation, electron beam evaporation, magnetron sputtering etc., conductive layer can be titanium, silver, gold, chromium, aluminium, copper, molybdenum, tantalum, tungsten etc. or nesa coating, also can be the alloy of these electric conducting materials, both can be single layer structure, also can be the sandwich construction formed with these conductive layers.Preferred employing magnetron sputtering Titanium Ti, conductive layer thickness is between 10nm-1000nm, and preferred thickness is 200nm, and the background vacuum pressure of sputtering is less than 1 × 106holder.
1.2, wet method or dry etching conductive layer is adopted to form source electrode 3 and drain electrode 4.
1.3, on source electrode 3, drain electrode 4 and substrate 1, continue deposition oxide semiconductive thin film afterwards, oxide semiconductor material can be binary, the multicomponent alloy (binary or multivariant oxide) of indium oxide, gallium oxide, zinc oxide, tin oxide etc. and their formation.Depositional mode can adopt laser deposition, MOCVD(vapor phase epitaxial growth), the mode of magnetron sputtering or electron beam evaporation, typically, adopt magnetron sputtering technique to make IGZO film, magnetic control spattering target adopts In2o3, Ga2o3, and ZnO, the molar percentage of three is 1:1:1, sputtering power 2.47W/cm2, air pressure 0.5 millitorr, oxygen content 1%.Substrate 1 remains on room temperature state, and target-substrate distance (distance between magnetic control spattering target and substrate 1) is 7cm, and background vacuum is less than 1 × 10-7holder, pre-sputtering 10min.The IGZO film thickness formed is 10-2000nm, and preferably thickness is 50nm.Oxide semiconductor thin-film is annealed under oxidizing atmosphere, and oxidizing atmosphere is elemental oxygen, oxygen, water, ozone, and method for annealing can be furnace annealing, infrared heating or RTA, and heating-up temperature is 100-600 DEG C.The carrier concentration of oxide semiconductor thin-film is less than 1018cm-3, be even less than 1015cm-3.Certainly, also by controlling partial pressure of oxygen between 0.01-7.0Pa, the carrier concentration of control oxide semiconductive thin film can be carried out.
1.4, hydrofluoric acid wet etching oxide semiconductor thin-film is adopted to form oxide semiconductor layer 2.
1.5, the magnetic field of change is utilized to carry out radiation to source electrode 3, drain electrode 4 and oxide semiconductor layer 2.The open at one end of induction coil can be utilized to press close to the rete at source electrode 3 and drain electrode 4 places, the alternating magnetic field that energising produces is perpendicular to source electrode 3 and drain electrode 4, thus source electrode 3 and drain electrode 4 produce induction eddy current, rapid heating source electrode 3 and drain electrode 4, thus heat the region (such as region 22 and region 23) of the oxide semiconductor layer 2 contacted with both, after oxides thing semiconductor layer 2 is heated, electric conductivity improves, conductivity increases, also eddy current can be produced under magnetic fields, like this, oxide semiconductor layer 2 and source electrode 3 and drain 4 contact area except by source electrode 3 with drain 4 heat transfer heat except, also be subject to induction heating, temperature raises rapidly the ionic bond In-O key caused between metal weak in oxide semiconductor layer 2 and oxygen, Zn-O bond fission, the carrier concentration of oxide semiconductor layer 2 is higher than 1018cm-3, further can higher than 1020cm-3, contact area conductivity significantly rises.The diffusion of metal in oxide semiconductor layer 2 of source electrode 3 and drain electrode 4, and the formation of contact area alloy also reduces the contact resistance of source electrode 3 and drain electrode 4 and oxide semiconductor layer 2, reduce further total series resistance of source electrode 3 and drain electrode 4.Adjusting of the material electric conductivity that induction coil electric current, heating time can adopt according to source electrode 3 and drain electrode 4, thickness.Field frequency can select power frequency (50HZ), intermediate frequency (1-10KHZ) and high frequency (more than 10KHZ).Heating atmosphere can be inert atmosphere, hydrogen or vacuum atmosphere.Oxide semiconductor layer 2 and source electrode 3 and drain 4 the induction heating of contact area can also (as laser) be assisted to heat with light further, accelerate processing speed further, the temperature of the substrate 1 when can reduce process further.
1.6, on oxide semiconductor layer 2, form grid insulating film, the depositional mode of grid insulating film can adopt PECVD, PLD, electron beam evaporation, magnetron sputtering and ALD, can by silicon nitride (SiNx), silica (SiO2), silicon oxynitride, aluminium oxide, yittrium oxide or HfO2etc. making, a kind of structure of optimization adopts ALD technology, and the at room temperature a-SiOx grid insulating film of deposit thickness 100nm, the background vacuum of deposition is less than 1 × 106holder.
1.7, on grid insulating film, form gate metal layer, the depositional mode of gate metal layer can adopt the technology such as thermal evaporation, electron beam evaporation, magnetron sputtering.
1.8, adopt wet method or dry etching gate metal layer to form the grid 6 of top grid oxide film transistor, then with grid 6 for mask, dry etching grid insulating film form the top grid oxide film transistor gate dielectric 5 consistent with grid 6 pattern.
Wherein, step 1.8 can after step 1.7, and with source electrode 3 and drain electrode 4 for exposure mask, adopt back-exposure mode to realize autoregistration top grid oxide film transistor arrangement, namely grid 6, gate insulator 5 and channel region 21 are all aimed at.
Above-mentioned steps 1.6 and step 1.5 can reversed order, carry out step 1.7 and step 1.8 more afterwards, in step 1.8, back-exposure mode can be adopted equally to realize autoregistration top grid oxide film transistor arrangement.
Embodiment 2
As shown in Figure 2, top grid oxide film transistor comprises substrate 7, be formed in the oxide semiconductor layer 8 of on substrate 7, be formed in source electrode 9 on oxide semiconductor layer 8 and drain electrode 10, gate insulator 11, the grid 12 be formed on gate insulator 11 be formed on source electrode 3, drain electrode 4 and oxide semiconductor layer 8, oxide semiconductor layer 8 comprises the region 82 and 83 that the channel region 81 corresponding with area of grid and raceway groove both sides touch source-drain electrode 9 and 10 respectively, and channel region is between source electrode 9 and drain electrode 10;
The manufacture method of the top grid oxide film transistor of the present embodiment comprises the following steps:
2.1, substrate 7 can be that glass, quartz, silicon chip or other flexible base, board are as plastics, stainless steel etc., on substrate 7, deposition forms oxide semiconductor thin-film, and oxide semiconductor material can be binary, the multicomponent alloy (binary or multivariant oxide) of indium oxide, gallium oxide, zinc oxide, tin oxide etc. and their formation.Depositional mode can adopt laser deposition, MOCVD(vapor phase epitaxial growth), the mode of magnetron sputtering or electron beam evaporation, typically, adopt magnetron sputtering technique to make IGZO film, magnetic control spattering target adopts In2o3, Ga2o3, and ZnO, the molar percentage of three is 1:1:1, sputtering power 2.47W/cm2, air pressure 0.5 millitorr, oxygen content 1%.Substrate 7 remains on room temperature state, and target-substrate distance (distance between magnetic control spattering target and substrate 7) is 7cm, and background vacuum is less than 1 × 10-7holder, pre-sputtering 10min.The IGZO film thickness formed is 10-2000nm, and preferably thickness is 50nm.Oxide semiconductor thin-film is annealed under oxidizing atmosphere, and oxidizing atmosphere is elemental oxygen, oxygen, water, ozone, and method for annealing can be furnace annealing, infrared heating or RTA, and heating-up temperature is 100-600 DEG C.The carrier concentration of oxide semiconductor thin-film is less than 1018cm-3, reach <10 further15cm-3.Certainly, also by controlling partial pressure of oxygen between 0.01-7.0Pa, the carrier concentration of control oxide semiconductive thin film can be carried out.
2.2, hydrofluoric acid wet etching oxide semiconductor thin-film is adopted to form oxide semiconductor layer 8.
2.3, depositing conducting layer on oxide semiconductor layer 8, depositional mode can adopt thermal evaporation, electron beam evaporation, magnetron sputtering etc., conductive layer can be that titanium, silver, gold, chromium, aluminium, copper, molybdenum, tantalum, tungsten etc. or nesa coating are as ITO, IZO etc., also can be the alloy of these electric conducting materials, both can be single layer structure, also can be the sandwich construction formed with these conductive layers.Preferred employing magnetron sputtering Titanium Ti, conductive layer thickness is between 10nm-1000nm, and preferred thickness is 200nm, and the background vacuum pressure of sputtering is less than 1 × 106holder.
2.4, wet method or dry etching conductive layer is adopted to form source electrode 3 and drain electrode 4.
2.5, this step is identical with the step 1.5 of embodiment 1.
2.6, deposition of gate insulation film in oxide semiconductor layer 8, source electrode 9 and drain electrode 11, the depositional mode of grid insulating film can adopt PECVD, PLD, electron beam evaporation, magnetron sputtering and ALD, can by silicon nitride (SiNx), silica (SiO2), silicon oxynitride, aluminium oxide, yittrium oxide or HfO2etc. making, a kind of structure of optimization adopts ALD technology, and the at room temperature a-SiOx grid insulating film of deposit thickness 100nm, the background vacuum of deposition is less than 1 × 106holder.
2.7, on grid insulating film, form gate metal layer, the depositional mode of gate metal layer can adopt the technology such as thermal evaporation, electron beam evaporation, magnetron sputtering.
2.8, adopt wet method or dry etching gate metal layer to form the grid 12 of top grid oxide film transistor, then with grid 12 for mask, dry etching grid insulating film form the top grid oxide film transistor gate dielectric 11 consistent with grid 12 pattern.
Step 2.8 can after step 2.7, and with source electrode 9 and drain electrode 11 for exposure mask, adopt back-exposure mode to realize autoregistration top grid oxide film transistor arrangement, namely grid 12, gate insulator 11 and channel region 81 are all aimed at.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.

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CN201210452913.8A2012-11-132012-11-13Manufacturing method of top-gate oxide thin-film transistorExpired - Fee RelatedCN103000530B (en)

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