CN102999441A - Fine granularity memory access method - Google Patents

Abstract

Translated fromChinese

本发明涉及计算机系统结构技术领域，公开了一种细粒度内存访问的方法。本发明通过在字节这一级别标识被修改的数据和零值数据来避免无效传输，因此降低了高速缓存数据区到内存的带宽占用，降低了额外写入的开销；另外，对于写损耗的存储器件，该方法可以减少其平均写入次数，延长其寿命，同时降低功耗。

The invention relates to the technical field of computer system structure and discloses a fine-grained memory access method. The present invention avoids invalid transmission by identifying modified data and zero-value data at the byte level, thereby reducing the bandwidth occupation from the cache data area to the memory, and reducing the overhead of additional writing; in addition, for the loss of writing For a storage device, the method can reduce its average write times, prolong its life, and reduce power consumption at the same time.

Description

A kind of method of fine granularity internal storage access

Technical field

The present invention relates to the Computer Systems Organization technical field, particularly relate to a kind of method of fine granularity internal storage access.

Background technology

The performance boost speed of calculator memory lags far behind the speed that processor performance promotes.With respect to processor, internal storage access postpones with 5 times speed increment in per ten years, and this system architecture unbalance formed and hindered " the storage wall " that processor performance promotes, thereby so that memory system becomes one of performance bottleneck of whole computer system.In order to address this problem, a lot of new memory techniques are suggested, and the fine granularity internal storage access is exactly one of them.The fine granularity internal storage access can accurately be controlled every a slice storage chip, can also avoid extra read-write, saves bandwidth.

Present fine granularity memory Accessing Mechanism concentrates on the DRAM(dynamic RAM) in the realization, purpose be for better under the polycaryon processor environment excavated space locality improve the efficient of internal storage access, effect is all undesirable.And having the device of the loss write for NAND-FLASH, phase transition internal memory etc., existing memory pool access method all can not reduce its loss.

Summary of the invention

The technical matters that (one) will solve

The technical matters that the present invention at first will solve is: how to avoid the invalid transmission in the internal storage access process.

(2) technical scheme

In order to solve the problems of the technologies described above, the invention provides a kind of method of fine granularity internal storage access, may further comprise the steps:

S1, define the dirty bitmap of fine granularity high-speed cache in the following manner: the content that the dirty bitmap of described fine granularity high-speed cache uses one or more 8 bit memory cell in the delegation in the one or more bits sign cached datas district whether initial value when reading in is different; Described cached data district is the data field of not writing loss or having the memory device of the loss write;

S2, define the null value bitmap in the following manner: described null value bitmap uses whether the data in one or more 8 bit memory cell in one or more bits sign internal memories are zero;

S3, define memory line in the following manner: in internal memory, a plurality of volatile or non-volatile memory chips increase the data that can store on each address by sharing read/write address, the storage space that each read/write address is corresponding is a memory line, and described memory line is made of the storage chip of 8 or more 1 byte bit wides; Described internal memory is to have the described internal memory of not writing loss or having the memory device of the loss write;

S4, utilize the dirty bitmap of described fine granularity high-speed cache to realize the read-write in cached data district;

S5, utilize described null value bitmap and memory line to realize the read-write of internal memory.

Preferably, step S4 is specially:

When the data line in described cached data district was read into, the bit in the initial dirty bitmap of fine granularity high-speed cache was considered as full 0 or complete 1;

When the data line in described cached data district is updated, according to byte newer data and legacy data, according to the two identical content of revising in the dirty bitmap of described fine granularity high-speed cache whether;

When the data line in described cached data district is replaced out, if the data in the sign of the bit in the dirty bitmap of described fine granularity high-speed cache cached data district do not change, then abandon the data that are replaced out, otherwise according to the bit in the dirty bitmap of described fine granularity high-speed cache, with the content write memory that has in the described cached data district in the byte of modification.

Preferably, step S5 is specially:

According to bit and the address in the dirty bitmap of described fine granularity high-speed cache, the row that is replaced out in the described cached data district is sent to the capable storage chip of correspondence memory in the internal memory;

When internal memory is read, according to corresponding bit in the null value bitmap, only send non-vanishing data, for the data that do not send, fill zero in the destination;

When data are written to internal memory, generate corresponding to the bit in the null value bitmap according to the data of write memory, and use the bit that generates to upgrade the null value bitmap.

Preferably, the size of the dirty bitmap of described fine granularity high-speed cache is 1/8 of cached data district size.

Preferably, the size of described null value bitmap is 1/8 of described memory size.

Preferably, described internal memory behavior 64 bits or more high-bit width.

(3) beneficial effect

Technique scheme has following advantage: avoid invalid transmission by the data and the null value data that are modified in this rank sign of byte, therefore reduced the bandwidth occupancy of cached data district to internal memory, reduced the expense that additionally writes; In addition, for the memory device of writing loss, the method can reduce it and on average write indegree, prolongs its life-span, reduces simultaneously power consumption.

Description of drawings

Fig. 1 is method flow diagram of the present invention;

Fig. 2 is the schematic diagram of the fine granularity internal storage access framework that defines in the method for the present invention;

Fig. 3 is the dirty bitmap schematic diagram of fine granularity high-speed cache of definition;

Fig. 4 is the schematic diagram of the null value bitmap of definition;

Fig. 5 is the process of writing of fine granularity internal storage access framework;

Fig. 6 is the read procedure of Fig. 5 fine granularity internal storage access framework.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for explanation the present invention, but are not used for limiting the scope of the invention.

As shown in Figure 1 and Figure 2, the invention provides a kind of method of fine granularity internal storage access, may further comprise the steps:

S1, define the dirty bitmap of fine granularity high-speed cache in the following manner: the content that the dirty bitmap of described fine granularity high-speed cache uses one or more 8 bit memory cell in the delegation in the one or more bits sign cached datas district whether initial value when reading in is different, that is to say the value that was written into from original different; Described cached data district is the data field of memory device (also can be the memory device of not writing loss) with the loss write; As shown in Figure 3.Among Fig. 3,8 Bit datas in each bit identification cached data district of the dirty bitmap of fine granularity high-speed cache.

S2, define the null value bitmap in the following manner: described null value bitmap uses whether the data in one or more 8 bit memory cell in one or more bits sign internal memories are zero; As shown in Figure 4.Among Fig. 4,8 bit memory cell in each sign memory line.

S3, define memory line in the following manner: in internal memory, a plurality of volatile or non-volatile memory chips increase the data that can store on each address by sharing read/write address, the storage space that each read/write address is corresponding is a memory line, be 64 bit bit wides, described memory line is made of the storage chip of 8 or more 8 bit bit wides, and off bit figure is stored in the extra storage chip; Described internal memory is to have the described internal memory of writing the memory device (also can be the memory device of not writing loss) of loss;

S4, utilize the dirty bitmap of described fine granularity high-speed cache to realize the read-write in cached data district; Step S4 is the read-write rule in cached data district.

S5, utilize described null value bitmap and memory line to realize the read-write of internal memory.Step S5 has described the rule of memory read-write.The data that the cached data district replaces out are one of sources of internal storage data.Simultaneously, internal storage data also is the source of cached data.

Such as Fig. 5, shown in Figure 6, step S4 is specially:

When the data line in described cached data district was read into, the bit in the initial dirty bitmap of fine granularity high-speed cache was considered as full 0 or complete 1;

When the data line in described cached data district is updated, according to byte newer data and legacy data, according to the two identical content of revising in the dirty bitmap of described fine granularity high-speed cache whether;

When the data line in described cached data district is replaced out, if the data in the sign of the bit in the dirty bitmap of described fine granularity high-speed cache cached data district do not change, then abandon the data that are replaced out, otherwise according to the bit in the dirty bitmap of described fine granularity high-speed cache, with the content write memory that has in the described cached data district in the byte of modification.

Such as Fig. 5, shown in Figure 6, step S5 is specially:

In Memory Controller Hub, according to bit and the address in the dirty bitmap of described fine granularity high-speed cache, the row that is replaced out in the described cached data district is sent to the capable storage chip of correspondence memory in the internal memory;

When data are read into internal memory from disk, according to the value of each byte, the null value bitmap is carried out assignment.When this byte was 0, bit corresponding in the null value bitmap was assigned 0 or 1.When this byte was not 0, assignment was its opposite number.

When high-speed cache need to read in data line from internal memory, Memory Controller Hub only sent non-vanishing data according to corresponding bit in the null value bitmap, after high-speed cache receives data, automatic filling 0 Value Data for the data that do not send, fills zero in the destination.

When data are written to internal memory, generate corresponding to the bit in the null value bitmap according to the data of write memory, and use the bit that generates to upgrade the null value bitmap.

Preferably, the size of the dirty bitmap of described fine granularity high-speed cache is 1/8 of cached data district size.

Preferably, the size of described null value bitmap is 1/8 of described memory size.

Preferably, described internal memory behavior 64 bits or more high-bit width.

As can be seen from the above embodiments, the present invention avoids invalid transmission by the data and the null value data that are modified in this rank of byte sign, has therefore reduced the cached data district to the taking of memory bandwidth, and has reduced the expense that additionally writes; In addition, for the memory device of writing loss, the method can reduce it and on average write indegree, prolongs its life-span, reduces simultaneously power consumption.

The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and replacement, these improvement and replacement also should be considered as protection scope of the present invention.

Claims (6)

1. the method for a fine granularity internal storage access is characterized in that, may further comprise the steps:

S1, define the dirty bitmap of fine granularity high-speed cache in the following manner: the content that the dirty bitmap of described fine granularity high-speed cache uses one or more 8 bit memory cell in the delegation in the one or more bits sign cached datas district whether initial value when reading in is different; Described cached data district is the data field of not writing loss or having the memory device of the loss write;

S2, define the null value bitmap in the following manner: described null value bitmap uses whether the data in one or more 8 bit memory cell in one or more bits sign internal memories are zero;

S3, define memory line in the following manner: in internal memory, a plurality of volatile or non-volatile memory chips increase the data that can store on each address by sharing read/write address, the storage space that each read/write address is corresponding is a memory line, and described memory line is made of the storage chip of 8 or more 1 byte bit wides; Described internal memory is to have the described internal memory of not writing loss or having the memory device of the loss write;

S4, utilize the dirty bitmap of described fine granularity high-speed cache to realize the read-write in cached data district;

S5, utilize described null value bitmap and memory line to realize the read-write of internal memory.

2. the method for claim 1 is characterized in that, step S4 is specially:

When the data line in described cached data district was read into, the bit in the initial dirty bitmap of fine granularity high-speed cache was considered as full 0 or complete 1;

When the data line in described cached data district is updated, according to byte newer data and legacy data, according to the two identical content of revising in the dirty bitmap of described fine granularity high-speed cache whether;

When the data line in described cached data district is replaced out, if the data in the sign of the bit in the dirty bitmap of described fine granularity high-speed cache cached data district do not change, then abandon the data that are replaced out, otherwise according to the bit in the dirty bitmap of described fine granularity high-speed cache, with the content write memory that has in the described cached data district in the byte of modification.

3. the method for claim 1 is characterized in that, step S5 is specially:

According to bit and the address in the dirty bitmap of described fine granularity high-speed cache, the row that is replaced out in the described cached data district is sent to the capable storage chip of correspondence memory in the internal memory;

When internal memory is read, according to corresponding bit in the null value bitmap, only send non-vanishing data, for the data that do not send, fill zero in the destination;

When data are written to internal memory, generate corresponding to the bit in the null value bitmap according to the data of write memory, and use the bit that generates to upgrade the null value bitmap.

4. the method for claim 1 is characterized in that, the size of the dirty bitmap of described fine granularity high-speed cache is 1/8 of cached data district size.

5. the method for claim 1 is characterized in that, the size of described null value bitmap is 1/8 of described memory size.

6. such as each described method in the claim 1 ~ 5, it is characterized in that described internal memory behavior 64 bits or high-bit width more.

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