技术领域technical field
本发明涉及数字信号传输领域，特别是涉及一种对MPEG帧进行帧同步的处理方法及帧同步电路。The invention relates to the field of digital signal transmission, in particular to a frame synchronization processing method for MPEG frames and a frame synchronization circuit.
背景技术Background technique
在同步数字通信中，数据均按照约定的帧格式进行发送和接收。如果传输距离较长,为了节省连线资源,一般不会使用单独的连线去传输数据的帧定位信息到接收端。对于长距离传输，采用的方法是：在发送端，每隔一段时间插入一个固定的帧同步头，在帧同步头之间排列需要传输的有效数据；在接收端，通过帧同步技术重新识别帧同步头，以确定有效数据的位置。简单来说，帧同步就是确定有效数据序列的帧同步头的位置,进而完成整个有效数据序列的定位关系的过程。In synchronous digital communication, data are sent and received according to the agreed frame format. If the transmission distance is long, in order to save connection resources, a separate connection is generally not used to transmit the frame alignment information of the data to the receiving end. For long-distance transmission, the method used is: at the sending end, insert a fixed frame synchronization header at regular intervals, and arrange the effective data to be transmitted between the frame synchronization headers; at the receiving end, re-identify the frame through frame synchronization technology synchronization header to determine the location of valid data. In simple terms, frame synchronization is the process of determining the position of the frame synchronization header of the valid data sequence, and then completing the positioning relationship of the entire valid data sequence.
在J.83B标准的数字电视系统中，数字电视系统的发送端发送的MPEG帧的帧同步头不是简单加入同步头，而是在发送MPEG帧之前，需要对每个要发送的有效数据进行处理，处理的过程包括：发送端将需要传输的有效数据（1496bit）输入一个线性反馈移位电路，线性反馈移位电路输出得到8bit校验和。将该校验和输入一个附加的有限冲激响应（FIR）滤波器，有限冲激响应滤波器输出得到一个8bit数据的结果。将该得到的结果补充到原来的有效数据（1496bit）的后面，获得新的1504bit数据，该1504bit数据即为要发送的一个完整的MPEG帧。如果再将一个经过上述处理的1504bit数据的完整MPEG帧输入线性反馈移位电路，那么正常情况下线性反馈移位电路输出的校验结果应该为一个预定数据，业界一般将此预定数据设为47H。In the digital TV system of the J.83B standard, the frame synchronization header of the MPEG frame sent by the sending end of the digital TV system is not simply added to the synchronization header, but before sending the MPEG frame, each valid data to be sent needs to be processed , the processing process includes: the sending end inputs the valid data (1496bit) to be transmitted into a linear feedback shift circuit, and the linear feedback shift circuit outputs an 8-bit checksum. The checksum is input into an additional finite impulse response (FIR) filter, and the output of the finite impulse response filter obtains a result of 8bit data. Add the obtained result to the back of the original valid data (1496bit) to obtain new 1504bit data, which is a complete MPEG frame to be sent. If a complete MPEG frame of 1504bit data processed above is input to the linear feedback shift circuit, then under normal circumstances, the verification result output by the linear feedback shift circuit should be a predetermined data, and the industry generally sets this predetermined data to 47H .
相应地，在J.83B标准的数字电视系统的接收端，只要将接收到的MPEG帧输入线性反馈移位电路进行校验，线性反馈移位电路输出的校验结果为上述预定数据47H，那么认为这个MPEG帧可能是完整的帧。Correspondingly, at the receiving end of the digital television system of the J.83B standard, as long as the received MPEG frame is input to the linear feedback shift circuit for verification, the verification result output by the linear feedback shift circuit is the above-mentioned predetermined data 47H, then Think this MPEG frame may be a complete frame.
上述数字电视系统接收端的处理过程即为帧同步的处理过程。在同步数字通信中，帧同步电路即是实现帧同步处理过程的电路。现有技术的帧同步电路是在内部使用了一个帧同步状态计数器和帧同步标志。帧同步标志若为低时，则说明尚未实现帧同步；而相应地，帧同步标志若为高时，则说明实现帧同步。具体地，帧同步状态计数器的初值为最小值0，在接收到帧头比较器的第一个高脉冲后，帧同步状态计数器加1；根据数据帧的长度，经过一帧的时间后，如果后面的帧在对应时刻没有产生帧同步脉冲，则帧同步状态计数器减1。当帧同步状态计数器达到上限T，表明完成帧同步，帧同步标志置为高。在实现帧同步以后，只在预测的帧同步头位置进行帧同步头判断。如果对应时刻没有产生帧同步脉冲，则帧同步状态计数器减1；如果对应时刻产生帧同步脉冲，则帧同步状态计数器加1或者保持T。在帧同步标志为高的情况下，一旦帧同步状态计数器的值为0，则表明帧同步失败，同时置帧同步标志为低。The above-mentioned processing process at the receiving end of the digital television system is the processing process of frame synchronization. In synchronous digital communication, the frame synchronization circuit is the circuit that realizes the frame synchronization process. The frame synchronization circuit in the prior art internally uses a frame synchronization state counter and a frame synchronization flag. If the frame synchronization flag is low, it means that frame synchronization has not been achieved; and correspondingly, if the frame synchronization flag is high, it means that frame synchronization has been achieved. Specifically, the initial value of the frame synchronization state counter is the minimum value 0, and after receiving the first high pulse of the frame header comparator, the frame synchronization state counter adds 1; according to the length of the data frame, after one frame time, If the following frame does not generate a frame synchronization pulse at the corresponding moment, the frame synchronization status counter is decremented by 1. When the frame synchronization state counter reaches the upper limit T, it indicates that the frame synchronization is completed, and the frame synchronization flag is set high. After the frame synchronization is realized, the frame synchronization head judgment is only performed at the predicted frame synchronization head position. If no frame synchronization pulse is generated at the corresponding time, the frame synchronization state counter is decremented by 1; if a frame synchronization pulse is generated at the corresponding time, the frame synchronization state counter is incremented by 1 or keeps T. When the frame synchronization flag is high, once the value of the frame synchronization state counter is 0, it indicates that the frame synchronization fails, and the frame synchronization flag is set low at the same time.
本申请的发明人在长期的研发中发现，上述帧同步电路处理帧同步的过程应用到J.83B标准的数字电视系统时，当一MPEG帧的帧长度范围内的码流通过线性反馈移位电路后得到的校验结果为47H时，现有帧同步电路的检测机制会锁定该码流中校验结果为47H时的位置，后续每一MPEG帧的帧长度范围内的码流在该锁定的位置判断该码流通过线性反馈移位电路后得到的校验结果是否仍为47H，如果该锁定位置的校验结果不是47H，则重新进行上述过程，搜索码流通过线性反馈移位电路后得到的校验结果为47H的位置。另外，由于线性反馈移位电路的校验能力不强，导致一个MPEG帧的帧长度范围内的码流经过线性反馈移位电路校验后，可能有不止一个位置的校验结果为47H。这使得上锁过程（即寻找同一位置出现校验结果为47H的位置点的过程）反复搜索，帧同步处理时间变长。The inventors of the present application have found in the long-term research and development that when the above-mentioned frame synchronization circuit processing frame synchronization process is applied to the digital television system of the J.83B standard, when the code stream within the frame length range of an MPEG frame is shifted by linear feedback When the verification result obtained after the circuit is 47H, the detection mechanism of the existing frame synchronization circuit will lock the position when the verification result is 47H in the code stream, and the code stream within the frame length range of each subsequent MPEG frame will be locked at this position. Judging whether the verification result obtained after the code stream passes through the linear feedback shift circuit is still 47H, if the verification result of the locked position is not 47H, then repeat the above process, and search for the code stream after passing through the linear feedback shift circuit The obtained verification result is the position of 47H. In addition, because the verification ability of the linear feedback shift circuit is not strong, after the code stream within the frame length range of an MPEG frame is verified by the linear feedback shift circuit, there may be more than one position where the verification result is 47H. This makes the locking process (that is, the process of finding a position point with a check result of 47H at the same position) search repeatedly, and the frame synchronization processing time becomes longer.
发明内容Contents of the invention
本发明主要解决的技术问题是提供一种对MPEG帧进行帧同步的处理方法及帧同步电路，能够大大减少重复搜索的次数，缩短帧同步的时间。The technical problem mainly solved by the present invention is to provide a frame synchronization processing method for MPEG frames and a frame synchronization circuit, which can greatly reduce the number of repeated searches and shorten the frame synchronization time.
本发明的一方面是：提供一种对MPEG帧进行帧同步的处理方法，包括：获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组；获取下一MPEG帧范围内的码流在所述第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组；利用所述符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。One aspect of the present invention is: provide a kind of processing method that frame synchronization is carried out to MPEG frame, comprise: obtain at least two position points that the first verification result of the code stream in the range of MPEG frame conforms to preset target, denoted as The first position group; obtain the position point where the first verification result of the code stream within the next MPEG frame range in the first position group meets the preset target, and record it as a fixed position group; use the conforming to the preset target At least one fixed position point in the fixed position group performs frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
其中，所述获取下一MPEG帧范围内的码流在所述第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组的步骤之后，还包括：将第n个所述MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n个所述码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始；将第n+1个所述MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n+1个所述码流在固定位置点的第二校验结果；判断第一差值是否等于0，所述第一差值是第n+1个所述码流与第n个所述码流分别在固定位置点的第二校验结果之间的差值；若第一差值不等于0，则确定第n+1个所述码流与第n个所述码流不是重复帧码流，并使帧同步计数器的值加1，所述帧同步计数器的初始值为0。Wherein, after the step of obtaining the code stream within the range of the next MPEG frame in the first position group where the first verification result meets the preset target, and recording it as a fixed position group, it also includes: The code streams within the range of the n MPEG frames are detected by the frame feature extraction circuit, and the second verification result of the nth code stream at a fixed position point is obtained, wherein n is a natural number, and n starts from 2; The code stream within the range of the n+1 MPEG frame is detected by the frame feature extraction circuit, and the second verification result of the n+1 code stream at a fixed position point is obtained; whether the first difference is equal to 0, the first difference is the difference between the n+1th code stream and the second verification result of the nth code stream at fixed positions; if the first difference is not equal to 0, it is determined that the n+1th code stream and the nth code stream are not repeated frame code streams, and the value of the frame synchronization counter is increased by 1, and the initial value of the frame synchronization counter is 0.
其中，所述判断第一差值是否等于0的步骤之后，还包括：若第一差值等于0，则确定第n+1个所述码流与第n个所述码流是重复帧码流，并使帧同步计数器的值不加1，保持不变。Wherein, after the step of judging whether the first difference is equal to 0, it also includes: if the first difference is equal to 0, then determining that the n+1th code stream and the nth code stream are repeated frame codes stream, and the value of the frame synchronization counter is not increased by 1, and remains unchanged.
其中，所述利用所述符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理的步骤，包括：判断所述帧同步计数器的值是否等于预定的阈值；若等于所述预定的阈值，则将所述固定位置点锁定，利用所述锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。Wherein, the step of using at least one fixed position point in the fixed position group that meets the preset target to perform frame synchronization processing on the code stream within the range of each subsequent MPEG frame includes: judging whether the value of the frame synchronization counter is is equal to a predetermined threshold; if equal to the predetermined threshold, the fixed position point is locked, and frame synchronization processing is performed on the code stream within the range of each subsequent MPEG frame by using the locked fixed position point.
其中，所述帧特征提取电路使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行检测。Wherein, the frame feature extraction circuit uses a cyclic redundancy check 16-bit algorithm (CRC16), a cyclic redundancy check 32-bit algorithm (CRC32), or a message digest algorithm version 5 (MD5) for detection.
其中，所述获取下一MPEG帧范围内的码流在所述第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组的步骤，包括：检测下一MPEG帧范围内的码流，获得所述码流在第一位置组中的位置点的第一校验结果；判断所述码流在第一位置组中是否有第一校验结果符合预设目标的位置点；若在第一位置组中有第一校验结果符合预设目标的位置点，则将所述码流在第一位置组中的第一校验结果符合预设目标的位置点记为固定位置组，并将所述固定位置组中第一校验结果符合预设目标的第一个位置点记为固定位置点。Wherein, the step of obtaining the position point where the first verification result of the code stream within the range of the next MPEG frame in the first position group conforms to the preset target is recorded as a fixed position group includes: detecting the next MPEG For the code stream within the frame range, obtain the first verification result of the position point of the code stream in the first position group; judge whether the first verification result of the code stream in the first position group meets the preset target If there is a position point where the first verification result meets the preset target in the first position group, the first verification result of the code stream in the first position group meets the position point of the preset target Record it as a fixed position group, and record the first position point in the fixed position group whose first verification result meets the preset target as a fixed position point.
其中，所述判断所述码流在第一位置组中是否有第一校验结果符合预设目标的位置点的步骤之后，还包括：若在第一位置组中没有第一校验结果符合预设目标的位置点，则返回所述获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组的步骤。Wherein, after the step of judging whether the code stream has a position point whose first verification result meets the preset target in the first position group, it further includes: if there is no first verification result in the first position group For the position point of the preset target, return at least two position points where the first verification result of the obtained code stream within an MPEG frame range conforms to the preset target, which is recorded as the step of the first position group.
所述利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理的步骤，包括：判断第m个MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，m是自然数，m从3开始；若符合所述预设目标，则继续判断第m+1个MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，直到同步处理结束。The step of using at least one fixed position point in the fixed position group that meets the preset target to perform frame synchronization processing on the code stream within each subsequent MPEG frame range includes: judging that the code stream within the range of the mth MPEG frame is within the range Whether the first verification result of the fixed position point meets the preset target, m is a natural number, and m starts from 3; if it meets the preset target, continue to judge whether the code stream within the range of the m+1th MPEG frame is in the Whether the first verification result of the fixed position point meets the preset target until the synchronization process ends.
所述获取下一MPEG帧范围内的码流在所述第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组的步骤，包括：获取下一MPEG帧范围内的码流的第一校验结果符合预设目标的位置点，记为第二位置组；获取所述第一位置组与第二位置组中位置相同的位置点，记为固定位置组。The step of obtaining the position point where the first verification result of the code stream within the next MPEG frame range in the first position group conforms to the preset target and recorded as a fixed position group includes: obtaining the next MPEG frame range The position points where the first verification result of the code stream in the code stream conforms to the preset target are recorded as the second position group; the position points whose positions in the first position group and the second position group are obtained are the same as the fixed position group.
本发明的另一方面是：提供一种帧同步电路，所述帧同步电路包括第一获取模块、第二获取模块以及同步处理模块；所述第一获取模块用于获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组，并向所述第二获取模块发送所述第一位置组；所述第二获取模块用于接收所述第一获取模块发送的第一位置组，获取下一MPEG帧范围内的码流在所述第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组，向所述同步处理模块发送所述固定位置组；所述同步处理模块用于接收所述第二获取模块发送的固定位置组，利用所述符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。Another aspect of the present invention is to provide a frame synchronization circuit, the frame synchronization circuit includes a first acquisition module, a second acquisition module and a synchronization processing module; the first acquisition module is used to acquire an MPEG frame range The first verification result of the code stream conforms to at least two position points of the preset target, recorded as a first position group, and sending the first position group to the second acquisition module; the second acquisition module is used to Receive the first position group sent by the first acquisition module, and obtain the position point where the first verification result of the code stream within the range of the next MPEG frame in the first position group meets the preset target, and record it as a fixed position group, sending the fixed position group to the synchronization processing module; the synchronization processing module is configured to receive the fixed position group sent by the second acquisition module, and use at least one fixed position group in the fixed position group that meets the preset target The position point performs frame synchronization processing on the code stream within the range of each subsequent MPEG frame.
其中，所述帧同步电路还包括第一获得模块、第二获得模块、判断模块以及第一确定模块；所述第一获得模块用于将第n个所述MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n个所述码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始，并向所述判断模块发送第n个所述码流在固定位置点的第二校验结果；所述第二获得模块用于将第n+1个所述MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n+1个所述码流在固定位置点的第二校验结果，并向所述判断模块发送第n+1个所述码流在固定位置点的第二校验结果；所述判断模块用于接收所述第一获得模块和第二获得模块发送的第n个码流和第n+1个码流分别在固定位置点的第二校验结果，并判断第一差值是否等于0，并向所述第一确定模块或相关模块发送判断结果，所述第一差值是第n+1个所述码流与第n个所述码流分别在固定位置点的第二校验结果之间的差值；所述第一确定模块用于接收所述判断模块发送的判断结果，在判断结果为第一差值不等于0时，确定第n+1个所述码流与第n个所述码流不是重复帧码流，并使帧同步计数器的值加1，所述帧同步计数器的初始值为0。Wherein, the frame synchronization circuit also includes a first obtaining module, a second obtaining module, a judging module and a first determining module; the first obtaining module is used to pass the code stream within the range of the nth MPEG frame through the frame The feature extraction circuit performs detection to obtain the second verification result of the nth code stream at a fixed position point, wherein n is a natural number, and n starts from 2, and sends the nth code stream to the judgment module The second verification result at a fixed position point; the second obtaining module is used to detect the code stream within the range of the n+1th MPEG frame through the frame feature extraction circuit, and obtain the n+1th said The second verification result of the code stream at a fixed position point, and send the second verification result of the n+1th code stream at a fixed position point to the judgment module; the judgment module is used to receive the first The second verification result of the nth code stream and the n+1th code stream sent by the first obtaining module and the second obtaining module at the fixed position points respectively, and judging whether the first difference is equal to 0, and sending to the first A determination module or a related module sends a judgment result, and the first difference is the difference between the n+1th code stream and the second verification result of the nth code stream at a fixed position point respectively ; The first determination module is used to receive the judgment result sent by the judgment module, and when the judgment result is that the first difference is not equal to 0, determine the n+1th code stream and the nth code stream The frame code stream is not repeated, and the value of the frame synchronization counter is increased by 1, and the initial value of the frame synchronization counter is 0.
其中，所述帧同步电路还包括第二确定模块，所述第二确定模块用于接收所述判断模块发送的判断结果，在判断结果为第一差值等于0时，确定第n+1个所述码流与第n个所述码流是重复帧码流，并使帧同步计数器的值不加1，保持不变。Wherein, the frame synchronization circuit further includes a second determination module, the second determination module is used to receive the judgment result sent by the judgment module, and when the judgment result is that the first difference is equal to 0, determine the n+1th The code stream and the nth code stream are repeated frame code streams, and the value of the frame synchronization counter is not incremented by 1 and remains unchanged.
其中，所述同步处理模块包括第一判断单元和同步处理单元；所述第一判断单元用于判断所述帧同步计数器的值是否等于预定的阈值，并向所述同步处理单元发送判断结果；所述同步处理单元用于接收所述第一判断单元发送的判断结果，在判断结果为等于所述预定的阈值时，将所述固定位置点锁定，利用所述锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。Wherein, the synchronization processing module includes a first judgment unit and a synchronization processing unit; the first judgment unit is used to judge whether the value of the frame synchronization counter is equal to a predetermined threshold, and send the judgment result to the synchronization processing unit; The synchronization processing unit is configured to receive the judgment result sent by the first judgment unit, and when the judgment result is equal to the predetermined threshold, lock the fixed position point, and use the locked fixed position point for each subsequent The frame synchronization process is performed on the code stream within the range of an MPEG frame.
其中，所述帧特征提取电路使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行检测。Wherein, the frame feature extraction circuit uses a cyclic redundancy check 16-bit algorithm (CRC16), a cyclic redundancy check 32-bit algorithm (CRC32), or a message digest algorithm version 5 (MD5) for detection.
其中，所述第二获取模块包括获得单元、第二判断单元以及记录单元；所述获得单元用于接收所述第一获取模块发送的第一位置组，检测下一MPEG帧范围内的码流，获得所述码流在第一位置组中的位置点的第一校验结果，并向所述第二判断单元发送获得的结果；所述第二判断单元用于接收所述获得单元发送的获得的结果，判断所述码流在第一位置组中是否有第一校验结果符合预设目标的位置点，并向所述记录单元或相关单元发送判断结果；所述记录单元用于接收所述第二判断单元发送的判断结果，在判断结果为第一位置组中有第一校验结果符合预设目标的位置点时，将所述码流在第一位置组中的第一校验结果符合预设目标的位置点记为固定位置组，并将所述固定位置组中第一校验结果符合预设目标的第一个位置点记为固定位置点。Wherein, the second acquisition module includes an acquisition unit, a second judgment unit, and a recording unit; the acquisition unit is used to receive the first position group sent by the first acquisition module, and detect the code stream within the range of the next MPEG frame , obtaining the first verification result of the position point of the code stream in the first position group, and sending the obtained result to the second judging unit; the second judging unit is configured to receive the result sent by the obtaining unit According to the obtained result, it is judged whether the code stream has a position point whose first verification result meets the preset target in the first position group, and the judgment result is sent to the recording unit or a related unit; the recording unit is used to receive The judgment result sent by the second judging unit, when the judging result is that there is a position point in the first position group where the first verification result meets the preset target, the first verification result of the code stream in the first position group The position point whose verification result meets the preset target is marked as a fixed position group, and the first position point in the fixed position group whose first verification result meets the preset target is marked as a fixed position point.
其中，所述第二获取模块还包括返回单元，所述返回单元用于接收所述第二判断单元发送的判断结果，在判断结果为第一位置组中没有第一校验结果符合预设目标的位置点时，返回所述第一获取模块。Wherein, the second acquisition module further includes a return unit, the return unit is used to receive the judgment result sent by the second judgment unit, and the judgment result is that no first verification result in the first position group meets the preset target When the location point is , return to the first acquisition module.
其中，所述同步处理模块包括第三判断单元和控制单元；所述第三判断单元用于判断第m个MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，并向所述控制单元发送判断结果，m是自然数，m从3开始；控制单元用于接收所述第三判断单元发送的判断结果，在判断结果符合所述预设目标时，继续判断第m+1个的MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，直到同步处理结束。Wherein, the synchronization processing module includes a third judging unit and a control unit; the third judging unit is used to judge whether the first verification result of the code stream within the range of the mth MPEG frame at the fixed position meets the predetermined Set a target and send a judgment result to the control unit, m is a natural number, and m starts from 3; the control unit is used to receive the judgment result sent by the third judgment unit, and when the judgment result meets the preset target, continue Judging whether the first verification result of the code stream within the range of the m+1th MPEG frame at the fixed position point meets a preset target until the synchronization process ends.
其中，所述第二获取模块包括第一获取单元和第二获取单元；所述第一获取单元用于获取下一MPEG帧范围内的码流的第一校验结果符合所述预设目标的位置点，记为第二位置组，并向所述第二获取单元发送第二位置组；所述第二获取单元用于接收所述第一获取模块发送的第一位置组和所述第一获取单元发送的第二位置组，获取所述第一位置组与第二位置组中位置相同的位置点，记为固定位置组。Wherein, the second acquisition module includes a first acquisition unit and a second acquisition unit; the first acquisition unit is used to acquire the first verification result of the code stream within the range of the next MPEG frame conforming to the preset target A position point, recorded as a second position group, and sending the second position group to the second acquisition unit; the second acquisition unit is used to receive the first position group and the first position group sent by the first acquisition module The second position group sent by the acquisition unit is acquired, and the position points in the first position group and the second position group are acquired, which are recorded as a fixed position group.
本发明的有益效果是：区别于现有技术的情况，本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，能够大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。The beneficial effects of the present invention are: different from the situation of the prior art, the present invention determines the first position group within the scope of one frame, that is, the first verification result is at least two position points of the preset target, and the first position In the group, it is determined that the first verification result of the next frame at the corresponding position is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset In this way, the possible starting position of the complete frame can be locked in only 2 frames, which can greatly reduce the number of repeated searches, shorten the time of frame synchronization, and greatly improve the accuracy of the starting position of the complete frame.
附图说明Description of drawings
图1是本发明对MPEG帧进行帧同步的处理方法一实施方式的流程图；Fig. 1 is the flow chart of an embodiment of the processing method that the present invention carries out frame synchronization to MPEG frame;
图2是本发明对MPEG帧进行帧同步的处理方法另一实施方式的流程图；Fig. 2 is the flow chart of another embodiment of the processing method that the present invention carries out frame synchronization to MPEG frame;
图3是本发明对MPEG帧进行帧同步的处理方法又一实施方式的流程图；Fig. 3 is the flow chart of another embodiment of the processing method that the present invention carries out frame synchronization to MPEG frame;
图4是本发明帧同步电路一实施方式的结构示意图；4 is a schematic structural diagram of an embodiment of the frame synchronization circuit of the present invention;
图5是本发明帧同步电路另一实施方式的结构示意图；5 is a schematic structural diagram of another embodiment of the frame synchronization circuit of the present invention;
图6是本发明帧同步电路又一实施方式的结构示意图；6 is a schematic structural diagram of another embodiment of the frame synchronization circuit of the present invention;
图7是本发明帧同步装置一实施方式的结构示意图。FIG. 7 is a schematic structural diagram of an embodiment of a frame synchronization device according to the present invention.
具体实施方式detailed description
下面结合附图和实施方式对本发明进行详细说明。The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.
参阅图1，图1是本发明对MPEG帧进行帧同步的处理方法一实施方式的流程图，包括：Referring to Fig. 1, Fig. 1 is the flow chart of an embodiment of the processing method that the present invention carries out frame synchronization to MPEG frame, comprises:
步骤S101：获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组。Step S101: Obtain at least two position points whose first verification result of the code stream within an MPEG frame range meets a preset target, and record them as a first position group.
一MPEG帧范围，是指与一个完整的MPEG帧的帧长度一样的MPEG帧码流。An MPEG frame range refers to an MPEG frame code stream that has the same frame length as a complete MPEG frame.
第一校验结果是MPEG帧码流串行通过线性移位寄存器而进行检验后，所获得的校验结果。本实施方式所称的校验是MPEG帧码流串行通过线性移位寄存器所进行的校验。当然，在本发明精神范围内，只要满足要求并且合适，可以用其他类型的校验，在此不再赘述。随着码流持续不断地通过线性移位寄存器，在每个码流的位置点均会得到的第一检验结果。这些第一校验结果有的相同，有的不同。The first check result is the check result obtained after the MPEG frame code stream is checked serially through the linear shift register. The verification referred to in this embodiment is the verification performed by the MPEG frame code stream serially passing through the linear shift register. Of course, within the scope of the spirit of the present invention, as long as the requirements are met and appropriate, other types of verification can be used, which will not be repeated here. As the code stream continuously passes through the linear shift register, the first inspection result will be obtained at each position of the code stream. Some of these first verification results are the same, and some are different.
预设目标是指第一校验结果所要满足的要求。The preset target refers to the requirement to be met by the first verification result.
首先确定第一校验结果的预设目标，当一MPEG帧范围内的码流串行通过线性移位寄存器后，即可获得码流的每个位置点的第一校验结果，查找一MPEG帧范围内的码流的位置点的第一校验结果符合预设目标的至少两个位置点，将这些第一校验结果符合预设目标的至少两个位置点，记为第一位置组。First, determine the preset target of the first verification result. When the code stream within the range of an MPEG frame passes through the linear shift register in series, the first verification result of each position point of the code stream can be obtained, and an MPEG The first verification results of the position points of the code stream within the frame range meet at least two position points of the preset target, and these first verification results meet at least two position points of the preset target, which are recorded as the first position group .
例如，在检测MPEG帧时，如果确定第一校验结果的预设目标为47H，使一MPEG帧范围内的码流串行通过线性移位寄存器检测，即可得到该码流每个位置点的第一校验结果，再确定第一校验结果为47H的至少两个位置点，并记录下来，记为第一位置组。For example, when detecting an MPEG frame, if it is determined that the preset target of the first verification result is 47H, and the code stream within the range of an MPEG frame is serially detected by a linear shift register, each position point of the code stream can be obtained Then determine at least two position points whose first verification result is 47H, and record them as the first position group.
上述列举的例子具体的实现过程可以是：MPEG帧码流串行通过线性移位寄存器得到码流每个位置点的第一校验结果后，将该第一校验结果串行通过8bit的帧头比较器，通过帧头比较器判断当前串行通过的8bit数据（即第一校验结果）是否为47H。当检测到第一个第一校验结果为47H时，位置计数器的值为0。以后，在每输入一个有效数据时位置计数器的值加1，当再检测到一个第一校验结果为47H时，用位置寄存器记下这个第一校验结果为47H所对应的位置计数器的值，即一个完整帧可能的位置点（1~1503），最多记下N个（N可配）。当位置计数器达到1503时，完成帧位置存储。The specific implementation process of the examples listed above can be: after the MPEG frame code stream is serially passed through the linear shift register to obtain the first verification result of each position point of the code stream, the first verification result is serially passed through the 8bit frame The header comparator, through the frame header comparator, judges whether the current 8-bit data passed serially (that is, the first verification result) is 47H. When it is detected that the first first verification result is 47H, the value of the position counter is 0. Afterwards, add 1 to the value of the position counter every time a valid data is input, and when a first check result is detected to be 47H, use the position register to record the value of the position counter corresponding to the first check result of 47H , that is, the possible position points (1~1503) of a complete frame, and record N at most (N can be configured). When the position counter reaches 1503, frame position storage is complete.
MPEG帧一帧的长度为1504bit，在一MPEG帧随机码流中，每个位置出现第一校验结果为47H的概率为1/256，因此每帧出现第一校验结果为47H位置点数的概率为5.875。按照概率来说，只要设置位置寄存器个数N不小于6，经过帧位置计数器检测后，一帧中出现第一校验结果为47H的位置均可记录下来。The length of one MPEG frame is 1504bit. In the random code stream of an MPEG frame, the probability of the first verification result being 47H in each position is 1/256, so the first verification result in each frame is 47H. The probability is 5.875. In terms of probability, as long as the number N of position registers is set to be not less than 6, after detection by the frame position counter, the position where the first verification result is 47H in a frame can be recorded.
当然，本实施方式仅是列举了第一校验结果为47H（预设目标），第一校验结果还可以为其它的预设目标，根据具体应用进行确定，在此不再进行赘叙。Of course, this embodiment only lists that the first verification result is 47H (preset target), and the first verification result can also be other preset targets, which are determined according to specific applications, and will not be repeated here.
步骤S102：获取下一MPEG帧范围内的码流在第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组。Step S102: Obtain the position points of the code stream within the next MPEG frame range in the first position group whose first verification result meets the preset target, and record it as a fixed position group.
检测下一MPEG帧范围内码流时，只是检测步骤S101的第一位置组中的位置点的第一校验结果，查找下一MPEG帧范围内的码流在步骤S101的第一位置组中的位置点的第一校验结果符合预设目标的位置点，并记为固定位置组。When detecting the code stream in the next MPEG frame range, only the first verification result of the position point in the first position group of step S101 is detected, and the code stream in the next MPEG frame range is searched in the first position group of step S101 The first verification result of the position points conforms to the position point of the preset target, and is recorded as a fixed position group.
或者下一MPEG帧范围内码流串行通过线性移位寄存器时，获得该一MPEG帧范围内码流每个位置点的第一校验结果，确定该一MPEG帧范围内码流每个位置点的第一校验结果符合预设目标的位置点，可以找到在步骤S101的第一位置组中，步骤S102的第一校验结果符合预设目标的位置点，并记为固定位置组。Or when the code stream in the next MPEG frame range passes through the linear shift register serially, the first check result of each position point of the code stream in the MPEG frame range is obtained, and each position of the code stream in the MPEG frame range is determined The position point whose first verification result of the point meets the preset target can be found in the first position group in step S101 and the position point whose first verification result in step S102 meets the preset target, and recorded as a fixed position group.
例如，检测MPEG帧时，可以找到下一MPEG帧范围内码流在第一位置组中的第一校验结果为47H的位置点，记为固定位置组。For example, when detecting an MPEG frame, the position point at which the first check result of the code stream in the first position group is 47H within the range of the next MPEG frame can be found, which is recorded as a fixed position group.
步骤S103：利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。Step S103: Use at least one fixed position point in the fixed position group meeting the preset target to perform frame synchronization processing on the code stream within each subsequent MPEG frame range.
固定位置点即为完整帧的可能的起始位置点，固定位置组中的固定位置点可能只有一个，可能是一个以上，当固定位置点只有一个时，在该固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理，当固定位置点有一个以上时，选择其中的一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。The fixed position point is the possible starting position point of the complete frame. There may be only one fixed position point in the fixed position group, and there may be more than one. When there is only one fixed position point, each subsequent MPEG The code stream within the frame range is subjected to frame synchronization processing. When there are more than one fixed position point, one of the fixed position points is selected to perform frame synchronization processing on the code stream within each subsequent MPEG frame range.
在实际应用中，一般通常将固定位置组中的第一校验结果符合预设目标的第一个位置点指定为固定位置点。In practical applications, generally, the first position point in the fixed position group whose first verification result meets the preset target is designated as the fixed position point.
步骤S103中进行帧同步处理的大概过程是：将后续每一MPEG帧范围内的码流串行通过线性移位寄存器，获得固定位置点的第一校验结果，判断该固定位置点的第一校验结果是否符合预设目标，如果符合预设目标，则继续后续每一MPEG帧范围内的码流在固定位置点的第一校验结果的判断。如果不符合预设目标，并且固定位置点只有一个，则返回步骤S101；如果不符合预设目标，并且固定位置点有两个或以上时，可以选择另外的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理，而无需返回步骤S101重新进行固定位置点的查找。The general process of frame synchronization processing in step S103 is: serially pass the code stream within the range of each subsequent MPEG frame through the linear shift register to obtain the first verification result of the fixed position point, and judge the first verification result of the fixed position point. Whether the verification result meets the preset target, and if it meets the preset target, continue to judge the first verification result of the code stream within the range of each MPEG frame at a fixed position point. If it does not meet the preset target, and there is only one fixed position point, then return to step S101; if it does not meet the preset target, and there are two or more fixed position points, another fixed position point can be selected for each subsequent MPEG frame The frame synchronization processing is performed on the code stream within the range, without returning to step S101 to search for the fixed position point again.
本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。The present invention determines the first position group within the range of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first verification result of the next frame at the corresponding position in the first position group It is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames to lock The possible starting position of the complete frame greatly reduces the number of repeated searches, shortens the frame synchronization time, and greatly improves the accuracy of the starting position of the complete frame.
参阅图2，图2是本发明对MPEG帧进行帧同步的处理方法另一实施方式的流程图，包括：Referring to Fig. 2, Fig. 2 is the flow chart of another embodiment of the processing method that the present invention carries out frame synchronization to MPEG frame, comprises:
步骤S201：获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组。Step S201: Obtain at least two position points whose first verification result of the code stream within an MPEG frame range meets a preset target, and record them as a first position group.
首先确定第一校验结果的预设目标，使一MPEG帧范围内的码流串行通过线性移位寄存器检测，即可确定该一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，并记为第一位置组。First determine the preset target of the first verification result, and make the code stream within the range of an MPEG frame serially pass through the linear shift register to detect, and then it can be determined that the first verification result of the code stream within the range of the MPEG frame meets the preset Set at least two position points of the target, and record them as the first position group.
步骤S202：获取下一MPEG帧范围内的码流在第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组。Step S202: Obtain the position points of the code stream within the next MPEG frame range in the first position group where the first verification result meets the preset target, and record it as a fixed position group.
下一MPEG帧范围内的码流串行通过线性移位寄存器时，可以找到在第一位置组中的第一校验结果符合预设目标的位置点，并记为固定位置组。When the code stream within the range of the next MPEG frame serially passes through the linear shift register, the position point at which the first verification result in the first position group meets the preset target can be found, and recorded as a fixed position group.
例如，检测MPEG帧时，可以找到下一MPEG帧范围内码流在第一位置组中的第一校验结果为47H的位置点，记为固定位置组。For example, when detecting an MPEG frame, the position point at which the first check result of the code stream in the first position group is 47H within the range of the next MPEG frame can be found, which is recorded as a fixed position group.
步骤S202之后，进入步骤S203和步骤S204，即步骤S203和步骤S204并行进行。After step S202, enter step S203 and step S204, that is, step S203 and step S204 are performed in parallel.
步骤S203：利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。Step S203: Use at least one fixed position point in the fixed position group meeting the preset target to perform frame synchronization processing on the code stream within each subsequent MPEG frame range.
固定位置组中的固定位置点可能只有一个，可能是一个以上，当固定位置点只有一个时，在该固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理，当固定位置点有一个以上时，选择其中的一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。There may be only one fixed position point in the fixed position group, and there may be more than one. When there are more than one, select one of the fixed position points to perform frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
在实际应用中，一般通常将固定位置组中的第一校验结果符合预设目标的第一个位置点指定为固定位置点。In practical applications, generally, the first position point in the fixed position group whose first verification result meets the preset target is designated as the fixed position point.
步骤S204：将包括步骤S202的码流在内的后续每一MPEG帧范围内的码流通过帧特征提取电路进行检测，获得每一MPEG帧范围内的码流在固定位置点的第二校验结果。该步骤包括：步骤S204a、步骤S204b、步骤S204c、步骤S204d以及步骤S204e。Step S204: Detect the subsequent code streams in each MPEG frame range including the code stream in step S202 through the frame feature extraction circuit, and obtain the second verification of the code streams in the fixed position points of each MPEG frame range result. This step includes: step S204a, step S204b, step S204c, step S204d and step S204e.
步骤S204a：将第n个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n个码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始；Step S204a: Detect the code stream within the range of the nth MPEG frame through the frame feature extraction circuit, and obtain the second verification result of the nth code stream at a fixed position point, wherein n is a natural number, and n starts from 2;
步骤S204a可以获得第n个码流在固定位置点的第二校验结果。In step S204a, the second verification result of the nth code stream at a fixed position can be obtained.
n为2时，第2个MPEG帧范围内的码流即为步骤S202中的下一MPEG帧范围内的码流。When n is 2, the code stream within the range of the second MPEG frame is the code stream within the range of the next MPEG frame in step S202.
帧特征提取电路包括但不限于使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行检测，只要能实现帧特征提取的类似功能的算法，帧特征提取电路均可使用。The frame feature extraction circuit includes but is not limited to the use of cyclic redundancy check 16-bit algorithm (CRC16), or cyclic redundancy check 32-bit algorithm (CRC32), or message digest algorithm version 5 (MD5) for detection, as long as the frame Algorithms with similar functions for feature extraction and frame feature extraction circuits can be used.
CRC校验全称CyclicRedundancyCheck，又叫循环冗余校验。它是一种散列函数，用来检测或校验传输或保存的数据错误，在通信领域广泛地用于实现差错控制，比如通信系统多使用CRC12、CRC16等等（12、16、32等值均是指多项式的最高阶N次幂）。CRC校验的编解码方法都非常简单，运算时间也很短。按照ITU规范标准条件下，CRC32比CRC16具有更可靠的验证性。The full name of CRC check is CyclicRedundancyCheck, also known as cyclic redundancy check. It is a hash function used to detect or verify data errors in transmission or storage. It is widely used in the field of communication to implement error control. For example, communication systems often use CRC12, CRC16, etc. (12, 16, 32, etc. Both refer to the highest order Nth power of the polynomial). The encoding and decoding methods of the CRC check are very simple, and the operation time is also very short. According to the standard conditions of ITU specification, CRC32 has more reliable verifiability than CRC16.
MD全称MessageDigest，又称消息摘要算法，MD5从MD2/3/4演化而来，MD5散列长度通常是128位，也是目前被大量广泛使用的散列算法之一，主要用于密码加密和文件校验等。MD5是一种不可逆的加密算法，它对应任何字符串都可以加密成一段唯一的固定长度的代码。通过MD5可以判断原始值是否正确（是否被更改过）。The full name of MD is MessageDigest, also known as message digest algorithm. MD5 evolved from MD2/3/4. The hash length of MD5 is usually 128 bits. It is also one of the widely used hash algorithms, mainly used for password encryption and file encryption. Calibration, etc. MD5 is an irreversible encryption algorithm, which can encrypt any character string into a unique fixed-length code. MD5 can be used to judge whether the original value is correct (whether it has been changed).
步骤S204b：将第n+1个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n+1个码流在固定位置点的第二校验结果；Step S204b: Detect the code stream within the range of the n+1th MPEG frame through the frame feature extraction circuit, and obtain the second verification result of the n+1th code stream at a fixed position point;
步骤S204b可以获得第n+1个码流在固定位置点的第二校验结果。In step S204b, the second verification result of the n+1th code stream at a fixed position can be obtained.
步骤S204c：判断第一差值是否等于0，第一差值是第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值；Step S204c: judging whether the first difference is equal to 0, the first difference is the difference between the n+1th code stream and the second verification result of the nth code stream respectively at fixed positions;
步骤S204c是判断第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值是否等于0。Step S204c is to judge whether the difference between the n+1th code stream and the second verification result of the nth code stream at fixed positions is equal to 0.
步骤S204d：若第一差值不等于0，则确定第n+1个码流与第n个码流不是重复帧码流，并使帧同步计数器的值加1，帧同步计数器的初始值为0。Step S204d: If the first difference is not equal to 0, then determine that the n+1th code stream and the nth code stream are not repeated frame code streams, and add 1 to the value of the frame synchronization counter, and the initial value of the frame synchronization counter is 0.
如果第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值不等于0，表明这两个码流不是重复帧码流。If the difference between the n+1th code stream and the second verification result of the nth code stream at the fixed position points is not equal to 0, it indicates that the two code streams are not repeated frame code streams.
步骤S204e：若第一差值等于0，则确定第n+1个码流与第n个码流是重复帧码流，并使帧同步计数器的值不加1，保持不变。Step S204e: If the first difference is equal to 0, determine that the n+1th code stream and the nth code stream are repetitive frame code streams, and keep the value of the frame synchronization counter unchanged by not adding 1.
如果第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值等于0，表明这两个码流是重复帧码流。If the difference between the n+1th code stream and the second verification result of the nth code stream at the fixed position points is equal to 0, it indicates that the two code streams are repetitive frame code streams.
虽然步骤S201、步骤S202、步骤S203可以很快锁定固定位置点，但是当遇到非完整帧的位置重复出现第一校验结果为预设目标（如47H）时，此时，锁定的固定位置点为假锁定，通过步骤S204，帧特征提取电路可以有效识别出重复帧，避免重复位置出现非完整帧的位置的第一校验结果为预设目标（如47H）导致的假同步，大大增加帧同步电路的可靠性。Although step S201, step S202, and step S203 can quickly lock the fixed position point, but when the position of the incomplete frame repeatedly appears that the first verification result is the preset target (such as 47H), at this time, the locked fixed position The point is a false lock, through step S204, the frame feature extraction circuit can effectively identify the repeated frame, avoiding the false synchronization caused by the first verification result of the position of the incomplete frame in the repeated position being the preset target (such as 47H), greatly increasing reliability of the frame synchronization circuit.
在步骤S203和步骤S204并行进行的过程中，步骤S203还可以包括以下具体内容：In the parallel process of step S203 and step S204, step S203 may also include the following specific content:
203a：判断帧同步计数器的值是否等于预定的阈值；203a: Determine whether the value of the frame synchronization counter is equal to a predetermined threshold;
203b：若等于预定的阈值，则将所述固定位置点锁定，利用所述锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。203b: If it is equal to the predetermined threshold, lock the fixed position point, and use the locked fixed position point to perform frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
帧同步计数器的值达到预定的阈值，说明连续在预定的阈值次数内，在相同固定位置点都检测出第一校验结果为预设目标，且第二校验结果均不相等，此时，即可锁定该固定位置点，进入同步锁定状态，利用该锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。此时的固定位置点即可认为是完整帧的起始位置点。The value of the frame synchronization counter reaches the predetermined threshold, indicating that within the predetermined threshold times, the first verification result is detected as the preset target at the same fixed position point, and the second verification results are not equal. At this time, That is to say, the fixed position point is locked and enters into a synchronously locked state, and frame synchronization processing is performed on the code stream within the scope of each subsequent MPEG frame by using the locked fixed position point. The fixed position point at this time can be regarded as the starting position point of the complete frame.
综上，本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。To sum up, the present invention determines the first position group within the scope of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first position point at the corresponding position in the next frame in the first position group. The verification result is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames The possible starting position of the complete frame can be locked, the number of repeated searches is greatly reduced, the frame synchronization time is shortened, and the accuracy of the starting position of the complete frame is greatly improved.
另外，帧特征提取电路可以有效识别出重复帧，避免重复位置出现非完整帧的位置的第一校验结果为预设目标（如47H）导致的假同步，大大增加帧同步电路的可靠性。In addition, the frame feature extraction circuit can effectively identify repeated frames, avoid false synchronization caused by the first verification result of the position where the repeated position has an incomplete frame as the preset target (such as 47H), and greatly increase the reliability of the frame synchronization circuit.
参阅图3，图3是本发明对MPEG帧进行帧同步的处理方法又一实施方式的流程图，包括：Referring to Fig. 3, Fig. 3 is the flow chart of another embodiment of the processing method that the present invention carries out frame synchronization to MPEG frame, comprises:
步骤S301：获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组。Step S301: Obtain at least two position points whose first verification result of the code stream within an MPEG frame range meets a preset target, and record them as a first position group.
步骤S302：获取下一MPEG帧范围内的码流在第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组。Step S302: Obtain the position points of the code stream within the range of the next MPEG frame in the first position group whose first verification result meets the preset target, and record it as a fixed position group.
例如，检测MPEG帧时，可以找到下一MPEG帧范围内码流在第一位置组中的第一校验结果为47H的位置点，记为固定位置组。For example, when detecting an MPEG frame, the position point at which the first check result of the code stream in the first position group is 47H within the range of the next MPEG frame can be found, which is recorded as a fixed position group.
其中，步骤S302可以通过两种方式实现，第一种方式是：Wherein, step S302 can be realized in two ways, the first way is:
步骤S302a：检测下一MPEG帧范围内的码流，获得码流在第一位置组中的位置点的第一校验结果；Step S302a: Detect the code stream within the range of the next MPEG frame, and obtain the first verification result of the position point of the code stream in the first position group;
步骤S302b：判断码流在第一位置组中是否有第一校验结果符合预设目标的位置点；Step S302b: judging whether there is a position point in the code stream in the first position group whose first verification result meets the preset target;
步骤S302c：若在第一位置组中有第一校验结果符合预设目标的位置点，则将所述码流在第一位置组中的第一校验结果符合预设目标的位置点记为固定位置组，并将所述固定位置组中第一校验结果符合预设目标的第一个位置点记为固定位置点。若在第一位置组中没有第一校验结果符合预设目标的位置点，则返回步骤S301。Step S302c: If there is a position point in the first position group whose first verification result meets the preset target, mark the position point of the code stream in the first position group whose first verification result meets the preset target is a fixed position group, and the first position point in the fixed position group whose first verification result meets the preset target is recorded as a fixed position point. If there is no location point whose first verification result meets the preset target in the first location group, return to step S301.
例如，如果检测MPEG帧码流，第一校验结果为47H时，那么上述S301、步骤S302a、步骤S302b、步骤S302c的具体过程是：For example, if the MPEG frame code stream is detected, and the first check result is 47H, then the concrete processes of above-mentioned S301, step S302a, step S302b, and step S302c are:
MPEG帧码流串行通过线性移位寄存器得到码流每个位置点的第一校验结果后，将该第一校验结果串行通过8bit的帧头比较器，通过帧头比较器判断当前串行通过的8bit数据（即第一校验结果）是否为47H。当检测到第一个第一校验结果为47H时，位置计数器的值为0。以后，在每输入一个有效数据时位置计数器的值加1，当再检测到一个第一校验结果为47H时，用位置寄存器记下这个第一校验结果为47H所对应的位置计数器的值，即完整帧的可能的起始位置点（1~1503），最多记下N个（N可配）。当位置计数器达到1503时，完成帧位置存储。After the MPEG frame code stream is serially passed through the linear shift register to obtain the first verification result of each position point of the code stream, the first verification result is serially passed through the 8-bit frame header comparator, and the frame header comparator is used to judge the current Whether the 8-bit data passed serially (that is, the first verification result) is 47H. When it is detected that the first first verification result is 47H, the value of the position counter is 0. Afterwards, add 1 to the value of the position counter every time a valid data is input, and when a first check result is detected to be 47H, use the position register to record the value of the position counter corresponding to the first check result of 47H , that is, the possible starting position points (1~1503) of the complete frame, and record N at most (N can be configured). When the position counter reaches 1503, frame position storage is complete.
下一个MPEG帧范围内的码流串行通过线性移位寄存器所输入的数据有效时，位置计数器的值为0，以后每当数据有效时，位置计数器的值加1，当到达位置存储器中的位置时就检测第一校验结果是否为47H，如果不是，就到下一个位置，依次对比，直到位置计数器的值达到1503。如果在位置计数器的值达到1503时还没有匹配上，就返回步骤S301；如果有一次匹配上，就进入下一个过程：固定位置点检测。When the code stream in the next MPEG frame is serially passed through the data input by the linear shift register, the value of the position counter is 0, and whenever the data is valid later on, the value of the position counter is increased by 1. When checking the position, check whether the first verification result is 47H, if not, go to the next position, and compare in turn until the value of the position counter reaches 1503. If there is no match when the value of the position counter reaches 1503, then return to step S301; if there is a match, then enter the next process: fixed position point detection.
第二种方式是：The second way is:
302A：获取下一MPEG帧范围内的码流的第一校验结果符合预设目标的位置点，记为第二位置组；302A: Obtain the position point where the first verification result of the code stream within the range of the next MPEG frame meets the preset target, and record it as the second position group;
302B：获取第一位置组与第二位置组中位置相同的位置点，记为固定位置组。302B: Obtain the same position points in the first position group and the second position group, which are recorded as fixed position groups.
步骤S302之后，进入步骤S303和步骤S304，即步骤S303和步骤S304并行进行。After step S302, enter step S303 and step S304, that is, step S303 and step S304 are performed in parallel.
步骤S303：利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。Step S303: Use at least one fixed position point in the fixed position group meeting the preset target to perform frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
当步骤S302以第一种方式实现时，步骤S303包括：When step S302 is implemented in the first manner, step S303 includes:
步骤S303A：判断第m个MPEG帧范围内的码流在固定位置点的第一校验结果是否符合预设目标，m是自然数，m从3开始；Step S303A: judging whether the first verification result of the code stream within the range of the mth MPEG frame at a fixed position meets the preset target, m is a natural number, and m starts from 3;
m为3时，第3个MPEG帧范围内的码流即为步骤S302的码流之后的第一个MPEG帧范围内的码流。When m is 3, the code stream in the range of the third MPEG frame is the code stream in the range of the first MPEG frame after the code stream in step S302.
步骤S303B：若符合预设目标，则继续判断第m+1个MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，直到同步处理结束，若不符合预设目标，则返回步骤S301。Step S303B: If the preset target is met, continue to judge whether the first verification result of the code stream within the range of the m+1th MPEG frame at the fixed position point meets the preset target until the synchronization process ends, if not If the target is preset, return to step S301.
在实际应用中，一般预先设置一个预定次数，该预定次数即为不符合预设目标的连续次数，若不符合预设目标，且不符合预设目标的次数达到了预定次数，则返回步骤S301，若不符合预设目标，且不符合预设目标的次数没有达到预定次数，则还是继续判断后续MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标。In practical applications, a preset number of times is generally preset, and the preset number of times is the number of consecutive times that do not meet the preset target. If the preset target is not met, and the number of times that does not meet the preset target reaches the preset number of times, then return to step S301 , if it does not meet the preset target, and the number of times that does not meet the preset target does not reach the predetermined number of times, continue to judge whether the first verification result of the code stream within the range of the subsequent MPEG frame at the fixed position point meets the preset target .
步骤S304：将包括步骤S302的码流在内的后续每一MPEG帧范围内的码流通过帧特征提取电路进行检测，获得每一MPEG帧范围内的码流在固定位置点的第二校验结果。该步骤包括：步骤S304a、步骤S304b、步骤S304c、步骤S304d以及步骤S304e。Step S304: Detect the subsequent code streams in each MPEG frame range including the code stream in step S302 through the frame feature extraction circuit, and obtain the second verification of the code streams in the fixed position points of each MPEG frame range result. This step includes: step S304a, step S304b, step S304c, step S304d and step S304e.
步骤S304a：将第n个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n个码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始；Step S304a: Detect the code stream within the range of the nth MPEG frame through the frame feature extraction circuit, and obtain the second verification result of the nth code stream at a fixed position point, wherein n is a natural number, and n starts from 2;
步骤S304a可以获得第n个码流在固定位置点的第二校验结果。In step S304a, the second verification result of the nth code stream at a fixed position can be obtained.
n为2时，第2个MPEG帧范围内的码流即为步骤S302中的下一MPEG帧范围内码流。When n is 2, the code stream within the range of the second MPEG frame is the code stream within the range of the next MPEG frame in step S302.
帧特征提取电路包括但不限于使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行检测，只要能实现帧特征提取的类似功能的算法，帧特征提取电路均可使用。The frame feature extraction circuit includes but is not limited to the use of cyclic redundancy check 16-bit algorithm (CRC16), or cyclic redundancy check 32-bit algorithm (CRC32), or message digest algorithm version 5 (MD5) for detection, as long as the frame Algorithms with similar functions for feature extraction and frame feature extraction circuits can be used.
步骤S304b：将第n+1个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n+1个码流在固定位置点的第二校验结果；Step S304b: Detect the code stream within the range of the n+1th MPEG frame through the frame feature extraction circuit, and obtain the second verification result of the n+1th code stream at a fixed position point;
步骤S304b可以获得第n+1个码流在固定位置点的第二校验结果。In step S304b, the second verification result of the n+1th code stream at a fixed position can be obtained.
步骤S304c：判断第一差值是否等于0，第一差值是第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值；Step S304c: judging whether the first difference is equal to 0, the first difference is the difference between the n+1th code stream and the second verification result of the nth code stream respectively at fixed positions;
步骤S304c是判断第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值是否等于0。Step S304c is to judge whether the difference between the n+1th code stream and the second verification result of the nth code stream at fixed positions is equal to 0.
步骤S304d：若第一差值不等于0，则确定第n+1个码流与第n个码流不是重复帧码流，并使帧同步计数器的值加1，帧同步计数器的初始值为0。Step S304d: If the first difference is not equal to 0, then determine that the n+1th code stream and the nth code stream are not repeated frame code streams, and add 1 to the value of the frame synchronization counter, and the initial value of the frame synchronization counter is 0.
如果第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值不等于0，表明这两个码流不是重复帧码流。If the difference between the n+1th code stream and the second verification result of the nth code stream at the fixed position points is not equal to 0, it indicates that the two code streams are not repeated frame code streams.
步骤S304e：若第一差值等于0，则确定第n+1个码流与第n个码流是重复帧码流，并使帧同步计数器的值不加1，保持不变。Step S304e: If the first difference is equal to 0, determine that the n+1th code stream and the nth code stream are repetitive frame code streams, and keep the value of the frame synchronization counter unchanged by not adding 1.
如果第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值等于0，表明这两个码流是重复帧码流。If the difference between the n+1th code stream and the second verification result of the nth code stream at the fixed position points is equal to 0, it indicates that the two code streams are repetitive frame code streams.
在步骤S303和步骤S304并行进行的过程中，步骤S303还可以包括以下具体内容：In the parallel process of step S303 and step S304, step S303 may also include the following specific content:
303a：判断帧同步计数器的值是否等于预定的阈值；303a: judging whether the value of the frame synchronization counter is equal to a predetermined threshold;
303b：若等于预定的阈值，则将所述固定位置点锁定，利用所述锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。303b: If it is equal to the predetermined threshold, lock the fixed position point, and use the locked fixed position point to perform frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
此时的固定位置点即可认为是完整帧的起始位置点。The fixed position point at this time can be regarded as the starting position point of the complete frame.
需要指出的是，在实际应用中可以根据需要增减本发明各个实施方式中的各个步骤，在此不再一一进行赘叙。It should be pointed out that in practical applications, steps in each embodiment of the present invention may be added or subtracted as required, and will not be repeated here.
本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。帧特征提取电路可以有效识别出重复帧，避免重复位置出现非完整帧的起始位置的第一校验结果为预设目标导致的假同步，大大增加帧同步电路的可靠性。The present invention determines the first position group within the range of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first verification result of the next frame at the corresponding position in the first position group It is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames to lock The possible starting position of the complete frame greatly reduces the number of repeated searches, shortens the frame synchronization time, and greatly improves the accuracy of the starting position of the complete frame. The frame feature extraction circuit can effectively identify repeated frames, avoid false synchronization caused by the first verification result of the initial position of an incomplete frame at the repeated position being a preset target, and greatly increase the reliability of the frame synchronization circuit.
参阅图4，图4是本发明帧同步电路一实施方式的结构示意图。Referring to FIG. 4 , FIG. 4 is a schematic structural diagram of an embodiment of a frame synchronization circuit according to the present invention.
可选地，图4所示的帧同步电路能够实现如图1或图2或图3所示的实施方式中的操作。Optionally, the frame synchronization circuit shown in FIG. 4 can implement operations in the implementation manner shown in FIG. 1 or FIG. 2 or FIG. 3 .
该帧同步电路包括：第一获取模块401、第二获取模块402以及同步处理模块403。The frame synchronization circuit includes: a first acquisition module 401 , a second acquisition module 402 and a synchronization processing module 403 .
第一获取模块401用于获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组，并向第二获取模块402发送第一位置组；The first obtaining module 401 is used to obtain at least two position points where the first verification result of the code stream within the range of an MPEG frame meets the preset target, which is recorded as the first position group, and sends the first position point to the second obtaining module 402. location group;
第二获取模块402用于接收第一获取模块401发送的第一位置组，获取下一MPEG帧范围内的码流在第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组，向同步处理模块403发送固定位置组；The second obtaining module 402 is configured to receive the first position group sent by the first obtaining module 401, and obtain the position point where the first verification result of the code stream within the range of the next MPEG frame in the first position group meets the preset target, Record it as a fixed position group, and send the fixed position group to the synchronization processing module 403;
同步处理模块403用于接收第二获取模块402发送的固定位置组，利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。The synchronization processing module 403 is used to receive the fixed position group sent by the second acquisition module 402, and use at least one fixed position point in the fixed position group meeting the preset target to perform frame synchronization processing on the code stream within each subsequent MPEG frame range.
本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。The present invention determines the first position group within the range of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first verification result of the next frame at the corresponding position in the first position group It is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames to lock The possible starting position of the complete frame greatly reduces the number of repeated searches, shortens the frame synchronization time, and greatly improves the accuracy of the starting position of the complete frame.
参阅图5，图5是本发明帧同步电路另一实施方式的结构示意图。Referring to FIG. 5 , FIG. 5 is a schematic structural diagram of another embodiment of the frame synchronization circuit of the present invention.
可选地，图5所示的帧同步电路能够实现如图1或图2所示的实施方式中的操作。Optionally, the frame synchronization circuit shown in FIG. 5 can implement operations in the implementation manner shown in FIG. 1 or FIG. 2 .
该帧同步电路包括：第一获取模块501、第二获取模块502、同步处理模块503、第一获得模块504、第二获得模块505、判断模块506、第一确定模块507以及第二确定模块508。The frame synchronization circuit includes: a first acquisition module 501, a second acquisition module 502, a synchronization processing module 503, a first acquisition module 504, a second acquisition module 505, a judgment module 506, a first determination module 507 and a second determination module 508 .
第一获取模块501用于获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组，并向第二获取模块502发送第一位置组；The first obtaining module 501 is used to obtain at least two position points where the first verification result of the code stream within the range of an MPEG frame meets the preset target, which is recorded as the first position group, and sends the first position point to the second obtaining module 502. location group;
第二获取模块502用于接收第一获取模块501发送的第一位置组，获取下一MPEG帧范围内的码流在第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组，向同步处理模块503发送固定位置组；The second acquisition module 502 is configured to receive the first position group sent by the first acquisition module 501, and acquire the position point where the first verification result of the code stream within the range of the next MPEG frame in the first position group meets the preset target, Record it as a fixed position group, and send the fixed position group to the synchronization processing module 503;
同步处理模块503用于接收第二获取模块502发送的固定位置组，利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。The synchronization processing module 503 is used to receive the fixed position group sent by the second acquisition module 502, and use at least one fixed position point in the fixed position group that meets the preset target to perform frame synchronization processing on the code stream within the range of each subsequent MPEG frame.
同步处理模块503包括第一判断单元和同步处理单元。The synchronization processing module 503 includes a first judging unit and a synchronization processing unit.
第一判断单元用于判断帧同步计数器的值是否等于预定的阈值，并向同步处理单元发送判断结果；The first judgment unit is used to judge whether the value of the frame synchronization counter is equal to a predetermined threshold, and send the judgment result to the synchronization processing unit;
同步处理单元用于接收判断单元发送的判断结果，在判断结果为等于预定的阈值时，将固定位置点锁定，利用锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。The synchronization processing unit is used to receive the judgment result sent by the judgment unit, and when the judgment result is equal to a predetermined threshold, lock the fixed position point, and use the locked fixed position point to perform frame synchronization processing on the code stream within the range of each subsequent MPEG frame .
第一获得模块504用于将第n个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n个码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始，并向判断模块506发送第n个码流在固定位置点的第二校验结果；The first obtaining module 504 is used to detect the code stream within the range of the nth MPEG frame through the frame feature extraction circuit, and obtain the second verification result of the nth code stream at a fixed position point, wherein n is a natural number, n Start from 2, and send the second verification result of the nth code stream at a fixed position point to the judgment module 506;
帧特征提取电路包括但不限于使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行检测，只要能实现帧特征提取的类似功能的算法，帧特征提取电路均可使用。The frame feature extraction circuit includes but is not limited to the use of cyclic redundancy check 16-bit algorithm (CRC16), or cyclic redundancy check 32-bit algorithm (CRC32), or message digest algorithm version 5 (MD5) for detection, as long as the frame Algorithms with similar functions for feature extraction and frame feature extraction circuits can be used.
第二获得模块505用于将第n+1个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n+1个码流在固定位置点的第二校验结果，并向判断模块506发送第n+1个码流在固定位置点的第二校验结果；The second obtaining module 505 is used to detect the code stream in the range of the n+1 MPEG frame through the frame feature extraction circuit, obtain the second verification result of the n+1 code stream at a fixed position point, and send it to the judgment Module 506 sends the second verification result of the n+1 code stream at a fixed position point;
判断模块506用于接收第一获得模块504和第二获得模块505发送的第n个码流和第n+1个码流分别在固定位置点的第二校验结果，并判断第一差值是否等于0，并向第一确定模块507或相关模块（如第二确定模块508）发送判断结果，第一差值是第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值；The judging module 506 is used to receive the second verification results of the nth code stream and the n+1th code stream at fixed positions respectively sent by the first obtaining module 504 and the second obtaining module 505, and judge the first difference Whether it is equal to 0, and send the judgment result to the first determination module 507 or related modules (such as the second determination module 508), the first difference is the difference between the n+1th code stream and the nth code stream at fixed positions the difference between the second verification results;
第一确定模块507用于接收判断模块506发送的判断结果，在判断结果为第一差值不等于0时，确定第n+1个码流与第n个码流不是重复帧码流，并使帧同步计数器的值加1，帧同步计数器的初始值为0。The first determination module 507 is used to receive the judgment result sent by the judgment module 506, and when the judgment result is that the first difference is not equal to 0, it is determined that the n+1 code stream and the n code stream are not repeated frame code streams, and The value of the frame synchronization counter is increased by 1, and the initial value of the frame synchronization counter is 0.
第二确定模块508用于接收判断模块506发送的判断结果，在判断结果为第一差值等于0时，确定第n+1个码流与第n个码流是重复帧码流，并使帧同步计数器的值不加1，保持不变。The second determination module 508 is used to receive the judgment result sent by the judgment module 506, and when the judgment result is that the first difference is equal to 0, it is determined that the n+1 code stream and the n code stream are repeated frame code streams, and make The value of the frame synchronization counter does not increase by 1 and remains unchanged.
综上，本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。To sum up, the present invention determines the first position group within the scope of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first position point at the corresponding position in the next frame in the first position group. The verification result is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames The possible starting position of the complete frame can be locked, the number of repeated searches is greatly reduced, the frame synchronization time is shortened, and the accuracy of the starting position of the complete frame is greatly improved.
另外，帧特征提取电路可以有效识别出重复帧，避免重复位置出现非完整帧的起始位置的第一校验结果为预设目标导致的假同步，大大增加帧同步电路的可靠性。In addition, the frame feature extraction circuit can effectively identify repeated frames, avoid false synchronization caused by the first verification result of the initial position of an incomplete frame at the repeated position being a preset target, and greatly increase the reliability of the frame synchronization circuit.
参阅图6，图6是本发明帧同步电路又一实施方式的结构示意图。Referring to FIG. 6 , FIG. 6 is a schematic structural diagram of another embodiment of the frame synchronization circuit of the present invention.
可选地，图6所示的帧同步电路能够实现如图1或图3所示的实施方式中的操作。Optionally, the frame synchronization circuit shown in FIG. 6 can implement operations in the implementation manner shown in FIG. 1 or FIG. 3 .
该帧同步电路包括：第一获取模块601、第二获取模块602、同步处理模块603、第一获得模块604、第二获得模块605、判断模块606、第一确定模块607以及第二确定模块608。The frame synchronization circuit includes: a first acquisition module 601, a second acquisition module 602, a synchronization processing module 603, a first acquisition module 604, a second acquisition module 605, a judgment module 606, a first determination module 607 and a second determination module 608 .
第一获取模块601用于获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组，并向第二获取模块602发送第一位置组；The first obtaining module 601 is used to obtain at least two position points where the first verification result of the code stream within the range of an MPEG frame meets the preset target, record it as the first position group, and send the first position point to the second obtaining module 602 location group;
第二获取模块602用于接收第一获取模块601发送的第一位置组，获取下一MPEG帧范围内的码流在第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组，向同步处理模块603发送固定位置组；The second obtaining module 602 is configured to receive the first position group sent by the first obtaining module 601, and obtain the position point where the first verification result of the code stream within the range of the next MPEG frame in the first position group meets the preset target, Record it as a fixed position group, and send the fixed position group to the synchronization processing module 603;
第二获取模块602包括两种情况下的第二获取模块。第一种情况的第二获取模块602包括获得单元6021、第二判断单元6022以及记录单元6023。The second acquiring module 602 includes second acquiring modules in two cases. The second obtaining module 602 in the first case includes an obtaining unit 6021 , a second judging unit 6022 and a recording unit 6023 .
获得单元6021用于接收第一获取模块601发送的第一位置组，检测下一MPEG帧范围内的码流，获得码流在第一位置组中的位置点的第一校验结果，并向第二判断单元6022发送获得的结果；The obtaining unit 6021 is used to receive the first position group sent by the first obtaining module 601, detect the code stream within the range of the next MPEG frame, obtain the first verification result of the position point of the code stream in the first position group, and send the The second judging unit 6022 sends the obtained result;
第二判断单元6022用于接收获得单元6021发送的获得的结果，判断码流在第一位置组中是否有第一校验结果符合预设目标的位置点，并向记录单元6023或相关单元（例如返回单元）发送判断结果；The second judging unit 6022 is used to receive the obtained result sent by the obtaining unit 6021, judge whether there is a position point in the code stream in the first position group whose first verification result meets the preset target, and report to the recording unit 6023 or a related unit ( For example, the return unit) sends the judgment result;
记录单元6023用于接收第二判断单元6022发送的判断结果，在判断结果为第一位置组中有第一校验结果符合预设目标的位置点时，将码流在第一位置组中的第一校验结果符合预设目标的位置点记为固定位置组，并将固定位置组中第一校验结果符合预设目标的第一个位置点记为固定位置点。The recording unit 6023 is used to receive the judgment result sent by the second judgment unit 6022, and when the judgment result is that there is a position point in the first position group whose first verification result meets the preset target, the code stream in the first position group The position point whose first verification result meets the preset target is marked as a fixed position group, and the first position point in the fixed position group whose first verification result meets the preset target is marked as a fixed position point.
第二获取模块602还包括返回单元，返回单元用于接收第二判断单元6022发送的判断结果，在判断结果为第一位置组中没有第一校验结果符合预设目标的位置点时，返回第一获取模块601。The second acquisition module 602 also includes a return unit, the return unit is used to receive the judgment result sent by the second judgment unit 6022, and when the judgment result is that there is no position point in the first position group whose first verification result meets the preset target, return The first acquiring module 601.
第二种情况的第二获取模块602包括第一获取单元和第二获取单元。The second obtaining module 602 in the second case includes a first obtaining unit and a second obtaining unit.
第一获取单元用于获取下一MPEG帧范围内的码流的第一校验结果符合预设目标的位置点，记为第二位置组，并向第二获取单元发送第二位置组；The first acquisition unit is used to acquire the position point where the first verification result of the code stream within the next MPEG frame range meets the preset target, which is recorded as the second position group, and sends the second position group to the second acquisition unit;
第二获取单元用于接收第一获取模块601发送的第一位置组和第一获取单元发送的第二位置组，获取第一位置组与第二位置组中位置相同的位置点，记为固定位置组。The second acquisition unit is used to receive the first position group sent by the first acquisition module 601 and the second position group sent by the first acquisition unit, and acquire the same position points in the first position group and the second position group, denoted as fixed location group.
同步处理模块603用于接收第二获取模块602发送的固定位置组，利用符合预设目标的固定位置组中至少一个固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。The synchronization processing module 603 is used to receive the fixed position group sent by the second acquisition module 602, and use at least one fixed position point in the fixed position group that meets the preset target to perform frame synchronization processing on the code stream within each subsequent MPEG frame range.
当第二获取模块602是第一种情况的第二获取模块602时，同步处理模块603包括第三判断单元6031和控制单元6032。When the second acquisition module 602 is the second acquisition module 602 in the first case, the synchronization processing module 603 includes a third judging unit 6031 and a control unit 6032 .
第三判断单元6031用于判断第m个MPEG帧范围内的码流在固定位置点的第一校验结果是否符合预设目标，并向控制单元6032发送判断结果，m是自然数，m从3开始；The third judging unit 6031 is used to judge whether the first verification result of the code stream within the range of the m-th MPEG frame at a fixed point meets the preset target, and sends the judging result to the control unit 6032, m is a natural number, and m starts from 3 start;
控制单元6032用于接收第三判断单元6031发送的判断结果，在判断结果符合预设目标时，继续判断第m+1个的MPEG帧范围内的码流在固定位置点的第一校验结果是否符合预设目标，直到同步处理结束，在判断结果不符合预设目标时，返回第一获取模块601。The control unit 6032 is used to receive the judgment result sent by the third judgment unit 6031, and when the judgment result meets the preset target, continue to judge the first verification result of the code stream within the range of the m+1th MPEG frame at a fixed position point Whether the preset target is met, until the synchronization process ends, and when the judgment result does not meet the preset target, return to the first acquiring module 601 .
在实际应用中，一般预先设置一个预定次数，该预定次数即为不符合预设目标的连续次数，若不符合预设目标，且不符合预设目标的次数达到了预定次数，则返回第一获取模块601，若不符合预设目标，且不符合预设目标的次数没有达到预定次数，则还是继续判断后续MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标。In practical applications, a predetermined number of times is generally preset, which is the number of consecutive times that do not meet the preset target. If the number of times that does not meet the preset target reaches the predetermined number, return to the first The acquisition module 601, if it does not meet the preset target, and the number of times of not meeting the preset target does not reach the predetermined number of times, then continue to judge whether the first verification result of the code stream within the range of the subsequent MPEG frame at the fixed position point meets preset goals.
当第二获取模块602是第二种情况的第二获取模块602时，同步处理模块603包括第一判断单元和同步处理单元。When the second acquisition module 602 is the second acquisition module 602 in the second case, the synchronization processing module 603 includes a first judging unit and a synchronization processing unit.
第一判断单元用于判断帧同步计数器的值是否等于预定的阈值，并向同步处理单元发送判断结果；The first judgment unit is used to judge whether the value of the frame synchronization counter is equal to a predetermined threshold, and send the judgment result to the synchronization processing unit;
同步处理单元用于接收第一判断单元发送的判断结果，在判断结果为等于预定的阈值时，将固定位置点锁定，利用锁定的固定位置点对后续每一MPEG帧范围内的码流进行帧同步处理。The synchronization processing unit is used to receive the judgment result sent by the first judgment unit, and when the judgment result is equal to a predetermined threshold, lock the fixed position point, and use the locked fixed position point to frame the code stream within the range of each subsequent MPEG frame Synchronous processing.
第一获得模块604用于将第n个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n个码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始，并向判断模块606发送第n个码流在固定位置点的第二校验结果；The first obtaining module 604 is used to detect the code stream within the range of the nth MPEG frame through the frame feature extraction circuit, and obtain the second verification result of the nth code stream at a fixed position point, wherein n is a natural number, n Start from 2, and send the second verification result of the nth code stream at a fixed position point to the judgment module 606;
帧特征提取电路包括但不限于使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行检测，只要能实现帧特征提取的类似功能的算法，帧特征提取电路均可使用。The frame feature extraction circuit includes but is not limited to the use of cyclic redundancy check 16-bit algorithm (CRC16), or cyclic redundancy check 32-bit algorithm (CRC32), or message digest algorithm version 5 (MD5) for detection, as long as the frame Algorithms with similar functions for feature extraction and frame feature extraction circuits can be used.
第二获得模块605用于将第n+1个MPEG帧范围内的码流通过帧特征提取电路进行检测，获得第n+1个码流在固定位置点的第二校验结果，并向判断模块606发送第n+1个码流在固定位置点的第二校验结果；The second obtaining module 605 is used to detect the code stream in the range of the n+1 MPEG frame through the frame feature extraction circuit, obtain the second verification result of the n+1 code stream at a fixed position point, and send the result to the judgment Module 606 sends the second verification result of the n+1 code stream at a fixed position point;
判断模块606用于接收第一获得模块604和第二获得模块605发送的第n个码流和第n+1个码流分别在固定位置点的第二校验结果，并判断第一差值是否等于0，并向第一确定模块607或相关模块（如第二确定模块608）发送判断结果，第一差值是第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值；The judging module 606 is used to receive the second verification results of the nth code stream and the n+1th code stream at fixed positions respectively sent by the first obtaining module 604 and the second obtaining module 605, and judge the first difference Whether it is equal to 0, and send the judgment result to the first determination module 607 or related modules (such as the second determination module 608), the first difference is the difference between the n+1th code stream and the nth code stream at fixed positions the difference between the second verification results;
第一确定模块607用于接收判断模块606发送的判断结果，在判断结果为第一差值不等于0时，确定第n+1个码流与第n个码流不是重复帧码流，并使帧同步计数器的值加1，帧同步计数器的初始值为0。The first determination module 607 is used to receive the judgment result sent by the judgment module 606, and when the judgment result is that the first difference is not equal to 0, it is determined that the n+1 code stream and the n code stream are not repeated frame code streams, and The value of the frame synchronization counter is increased by 1, and the initial value of the frame synchronization counter is 0.
第二确定模块608用于接收判断模块606发送的判断结果，在判断结果为第一差值等于0时，确定第n+1个码流与第n个码流是重复帧码流，并使帧同步计数器的值不加1，保持不变。The second determination module 608 is used to receive the judgment result sent by the judgment module 606, and when the judgment result is that the first difference is equal to 0, it is determined that the n+1 code stream and the n code stream are repeated frame code streams, and make The value of the frame synchronization counter does not increase by 1 and remains unchanged.
需要说明的是，可以根据实际应用情况增减本发明上述实施方式中的模块或单元，在此不再进行赘叙。It should be noted that the modules or units in the above embodiments of the present invention may be increased or decreased according to actual application conditions, and details are not repeated here.
综上，本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。另外，帧特征提取电路可以有效识别出重复帧，避免重复位置出现非完整帧的起始位置的第一校验结果为预设目标导致的假同步，大大增加帧同步电路的可靠性。To sum up, the present invention determines the first position group within the scope of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first position point at the corresponding position in the next frame in the first position group. The verification result is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames The possible starting position of the complete frame can be locked, the number of repeated searches is greatly reduced, the frame synchronization time is shortened, and the accuracy of the starting position of the complete frame is greatly improved. In addition, the frame feature extraction circuit can effectively identify repeated frames, avoid false synchronization caused by the first verification result of the initial position of an incomplete frame at the repeated position being a preset target, and greatly increase the reliability of the frame synchronization circuit.
本发明还提供一种帧同步装置，如图7所示，该装置包括：移位寄存器701、处理器702、位置计数器703、位置寄存器704、帧同步计数器705。The present invention also provides a frame synchronization device. As shown in FIG. 7 , the device includes: a shift register 701 , a processor 702 , a position counter 703 , a position register 704 , and a frame synchronization counter 705 .
处理器702通过移位寄存器701、位置计数器703、位置寄存器704，获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组，并再次获取下一MPEG帧范围内的码流在所述第一位置组中的第一校验结果符合预设目标的位置点，记为固定位置组；处理器702利用符合预设目标的固定位置组中至少一个固定位置点，控制移位寄存器701、位置计数器703、位置寄存器704对后续每一MPEG帧范围内的码流进行帧同步处理。The processor 702 obtains at least two position points where the first verification result of the code stream within the range of an MPEG frame meets the preset target through the shift register 701, the position counter 703, and the position register 704, which are recorded as the first position group, And obtain again the location point where the first verification result of the code stream within the next MPEG frame range in the first location group meets the preset target, and record it as a fixed location group; the processor 702 utilizes the fixed location point that meets the preset goal. At least one fixed position point in the position group controls the shift register 701, the position counter 703, and the position register 704 to perform frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
处理器702还用于通过帧特征提取电路获得第n个码流在固定位置点的第二校验结果，其中，n是自然数，n从2开始；通过帧特征提取电路获得第n+1个码流在固定位置点的第二校验结果；判断第一差值是否等于0，第一差值是所述第n+1个码流与第n个码流分别在固定位置点的第二校验结果之间的差值；在第一差值不等于0时，确定第n+1个码流与第n个码流不是重复帧码流，并使帧同步计数器705的值加1，帧同步计数器705的初始值为0，在第一差值等于0时，确定第n+1个码流与第n个码流是重复帧码流，并使帧同步计数器705的值不加1，保持不变。The processor 702 is also used to obtain the second verification result of the nth code stream at a fixed position through the frame feature extraction circuit, wherein n is a natural number, and n starts from 2; the n+1th code stream is obtained through the frame feature extraction circuit The second verification result of the code stream at the fixed position point; judging whether the first difference is equal to 0, the first difference is the second difference between the n+1 code stream and the nth code stream at the fixed position point respectively The difference between the verification results; when the first difference is not equal to 0, it is determined that the n+1 code stream and the n code stream are not repeated frame code streams, and the value of the frame synchronization counter 705 is added by 1, The initial value of the frame synchronization counter 705 is 0, and when the first difference is equal to 0, it is determined that the n+1 code stream and the n code stream are repeated frame code streams, and the value of the frame synchronization counter 705 is not increased by 1 ,constant.
处理器702还用于判断帧同步计数器705的值是否等于预定的阈值；在等于预定的阈值时，锁定该固定位置点，利用锁定的固定位置点，控制移位寄存器701、位置计数器703、位置寄存器704对后续每一MPEG帧范围内的码流进行帧同步处理。The processor 702 is also used to judge whether the value of the frame synchronization counter 705 is equal to a predetermined threshold; when it is equal to the predetermined threshold, lock the fixed position point, and use the locked fixed position point to control the shift register 701, the position counter 703, the position The register 704 performs frame synchronization processing on the code stream within the scope of each subsequent MPEG frame.
处理器702在获得固定位置点的第二校验结果时帧特征提取电路包括但不限于使用循环冗余校验16位算法（CRC16）、或循环冗余校验32位算法（CRC32）、或消息摘要算法版本5（MD5）进行计算，只要能实现帧特征提取的类似功能的算法，帧特征提取电路均可使用。When the processor 702 obtains the second verification result of the fixed position point, the frame feature extraction circuit includes but is not limited to using a cyclic redundancy check 16-bit algorithm (CRC16), or a cyclic redundancy check 32-bit algorithm (CRC32), or Message Digest Algorithm Version 5 (MD5) is used for calculation. As long as the algorithm can realize the similar function of frame feature extraction, the frame feature extraction circuit can be used.
处理器702还用于通过移位寄存器701、位置计数器703、位置寄存器704检测下一MPEG帧范围内的码流，获得所述码流在第一位置组中的位置点的第一校验结果；判断所述码流在第一位置组中是否有第一校验结果符合预设目标的位置点；在第一位置组中有第一校验结果符合预设目标的位置点时，将所述码流在第一位置组中的第一校验结果符合预设目标的位置点记为固定位置组，并将所述固定位置组中第一校验结果符合预设目标的第一个位置点记为固定位置点；在第一位置组中没有第一校验结果符合预设目标的位置点时，返回并重新通过移位寄存器701、位置计数器703、位置寄存器704获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组。The processor 702 is also configured to detect the code stream within the range of the next MPEG frame through the shift register 701, the position counter 703, and the position register 704, and obtain the first verification result of the position point of the code stream in the first position group ; Judging whether the code stream has a position point whose first verification result meets the preset target in the first position group; when there is a position point in the first position group whose first verification result meets the preset target, the The position point where the first verification result of the code stream in the first position group meets the preset target is marked as a fixed position group, and the first position in the fixed position group where the first verification result meets the preset target The point is marked as a fixed position point; when there is no position point in the first position group where the first verification result meets the preset target, return and re-acquire within the range of an MPEG frame through the shift register 701, the position counter 703, and the position register 704 At least two position points where the first verification result of the code stream conforms to the preset target are recorded as the first position group.
处理器702还用于判断第m个MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，m是自然数，m从3开始；在符合预设目标时，继续判断第m+1个MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标，直到同步处理结束。The processor 702 is also used to judge whether the first verification result of the code stream within the range of the mth MPEG frame meets the preset target at the fixed position point, m is a natural number, and m starts from 3; when the preset target is met , continue to judge whether the first verification result of the code stream within the range of the m+1th MPEG frame at the fixed position point meets the preset target, until the synchronization process ends.
在实际应用中，一般预先设置一个预定次数，该预定次数即为不符合预设目标的连续次数，若不符合预设目标，且不符合预设目标的次数达到了预定次数，则返回并重新通过移位寄存器701、位置计数器703、位置寄存器704获取一MPEG帧范围内的码流的第一校验结果符合预设目标的至少两个位置点，记为第一位置组；若不符合预设目标，且不符合预设目标的次数没有达到预定次数，则还是继续判断后续MPEG帧范围内的码流在所述固定位置点的第一校验结果是否符合预设目标。In practical applications, a preset number of times is generally preset, which is the number of consecutive times that do not meet the preset goal. If the number of times that does not meet the preset goal reaches the predetermined number, return and restart Obtain at least two position points where the first verification result of the code stream within the MPEG frame range meets the preset target by the shift register 701, the position counter 703, and the position register 704, and record it as the first position group; if it does not meet the preset If the target is set, and the number of times of failure to meet the preset target does not reach the predetermined number, continue to judge whether the first verification result of the code stream within the range of the subsequent MPEG frame at the fixed position meets the preset target.
处理器702还用于通过移位寄存器701、位置计数器703、位置寄存器704，获取下一MPEG帧范围内码流第一校验结果符合预设目标的位置点，记为第二位置组；获取所述第一位置组与第二位置组中位置相同的位置点，记为固定位置组。The processor 702 is also used to obtain the position point where the first verification result of the code stream within the range of the next MPEG frame meets the preset target through the shift register 701, the position counter 703, and the position register 704, and record it as the second position group; The position points in the first position group and the second position group are the same as the fixed position group.
本发明在一帧的范围内确定第一位置组，即第一校验结果为预设目标的至少两个位置点，在第一位置组中确定下一帧在相应位置的第一校验结果也为预设目标的位置点，从而确定固定位置点，后续帧码流只是检测该固定位置点的第一校验结果是否为预设目标；通过这种方式，只需2帧时间即可锁定完整帧的可能起始位置，大大减少重复搜索的次数，缩短帧同步的时间，且大大提高完整帧的起始位置的准确性。The present invention determines the first position group within the range of one frame, that is, at least two position points whose first verification result is the preset target, and determines the first verification result of the next frame at the corresponding position in the first position group It is also the position point of the preset target, so as to determine the fixed position point, and the subsequent frame code stream only detects whether the first verification result of the fixed position point is the preset target; in this way, it only takes 2 frames to lock The possible starting position of the complete frame greatly reduces the number of repeated searches, shortens the frame synchronization time, and greatly improves the accuracy of the starting position of the complete frame.
在本发明所提供的几个实施方式中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施方式仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementations described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例实施方式方案的目的。The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the implementation scheme of this embodiment.
另外，在本发明各个实施方式中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备（可以是个人计算机，服务器，或者网络设备等）或处理器（processor）执行本发明各个实施方式所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器（ROM，Read-OnlyMemory）、随机存取存储器（RAM，RandomAccessMemory）、磁碟或者光盘等各种可以存储程序代码的介质。If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disk or optical disk, and other media that can store program codes.
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。The above is only the embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technologies fields, all of which are equally included in the scope of patent protection of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210487221.7ACN102984549B (en) | 2012-11-26 | 2012-11-26 | Carry out processing method and the vertical sync circuit of frame synchronization |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210487221.7ACN102984549B (en) | 2012-11-26 | 2012-11-26 | Carry out processing method and the vertical sync circuit of frame synchronization |
| Publication Number | Publication Date |
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| CN102984549A CN102984549A (en) | 2013-03-20 |
| CN102984549Btrue CN102984549B (en) | 2016-03-30 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201210487221.7AActiveCN102984549B (en) | 2012-11-26 | 2012-11-26 | Carry out processing method and the vertical sync circuit of frame synchronization |
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| CN (1) | CN102984549B (en) |
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