CN102957315A - Boost integrated circuit for tuner - Google Patents
Boost integrated circuit for tunerDownload PDFInfo
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- CN102957315A CN102957315ACN2011102390997ACN201110239099ACN102957315ACN 102957315 ACN102957315 ACN 102957315ACN 2011102390997 ACN2011102390997 ACN 2011102390997ACN 201110239099 ACN201110239099 ACN 201110239099ACN 102957315 ACN102957315 ACN 102957315A
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Abstract
Description
Technical Field
The invention relates to the field of electrical design, in particular to a boosting integrated circuit.
Background
The Tuner, known as Tuner, is a device for completing receiving, gating, frequency conversion and demodulation processes in an analog mode, is commonly called Tuner in televisions, and has wide application in televisions and FM/AM radios. Such as an M/AM tuner or a TV tuner, FM and AM are both signal modulation methods, FM refers to frequency modulation, and AM refers to amplitude modulation.
The current tuner operation requires a +33V voltage, and the tuning operation voltage is currently provided by the following two methods:
firstly, the main board provides the tuning working voltage electrical signal, and most of the main boards at present use low voltage (for example + 5V) for power supply, so a general boosting circuit must be set during implementation, and the low voltage electrical signal (for example + 5V) is boosted to a high voltage telecommunication signal (+ 33V) through the boosting circuit. Therefore, the circuit implementation cost of the solution is high, and the implementation mode needs to occupy the mainboard resource, so that the implementation mode is basically eliminated at present.
Secondly, the power supply of +33V is carried in the tuner, and a booster circuit is added in the tuner. At present, a vibration booster circuit is mainly formed by more than ten devices such as a triode, an inductor and the like, the circuit is complex in structure and high in failure rate, and the vibration generated by the booster circuit can interfere with a tuned signal, so that the realization solution has high requirements on the precision and anti-interference parameters of the devices, and the device cost is high.
Disclosure of Invention
A first object of the embodiments of the present invention is to provide a boosting integrated circuit, which can boost a low-voltage electrical signal into a required high-voltage electrical signal, and is adaptable and adjustable according to practical applications.
The embodiment of the invention provides a boost integrated circuit, which comprises: a clock oscillation circuit, a charge pump circuit, and a voltage stabilizing circuit, wherein,
the clock oscillation circuit is electrically connected with the charge pump circuit and is used for providing a clock frequency signal for the charge pump circuit,
the input end of the low-noise circuit is externally connected with an external input low-voltage signal, and the output end of the low-noise circuit is electrically connected with the voltage stabilizing circuit; wherein,
the charge pump circuit comprises a charge pump subcircuit and an output load circuit which are sequentially cascaded by N stages, wherein N is a natural number;
each charge pump sub-circuit includes:
a first voltage regulator diode (D1), a second voltage regulator diode (D2), a third voltage regulator diode (D3) and a fourth voltage regulator diode (D4) which are mutually and electrically connected in series and have the same electrical parameter,
a first parasitic capacitor (CS 1), a second parasitic capacitor (CS 2) and a third parasitic capacitor (CS 3) which are respectively and electrically connected between the negative terminal and the ground terminal of the second voltage-regulator diode (D2), the third voltage-regulator diode (D3) and the fourth voltage-regulator diode (D4) and have the same electrical parameter,
a third load capacitor (C3) electrically connected between the negative terminal of the zener diode D4 and the first input terminal of the clock frequency signal,
a second load capacitor (C2) electrically connected between the negative terminal of the zener diode D3 and the second input terminal of the clock frequency signal,
a first load capacitor (C1) electrically connected between the negative terminal of the zener diode D2 and the first input terminal of the clock frequency signal,
wherein the electrical parameters of the first load capacitor (C1), the second load capacitor (C2), and the third load capacitor (C3) are the same;
the positive electrode end of a fourth voltage stabilizing diode (D4) in the 1 st-level charge pump sub-circuit can be externally connected with the external low-voltage electric signal, and the negative electrode of a first voltage stabilizing diode (D1) of the Nth-level charge pump sub-circuit outputs a required high-voltage electric signal outwards through the voltage stabilizer.
Optionally, the voltage stabilizer is: an RC filter circuit composed of a side-ground capacitor (Cout) and a side-ground resistor (R) connected in parallel,
the first voltage stabilizing diode (D1) of the Nth stage charge pump subcircuit outputs the required high-voltage electric signal outwards through the voltage stabilizer: in particular, the method comprises the following steps of,
one end of the RC filter circuit is electrically connected with the cathode of a first voltage stabilizing diode (D1) of the Nth-stage charge pump subcircuit, and the other end of the RC filter circuit is grounded.
Optionally, the first zener diode (D1), the second zener diode (D2), the third zener diode (D3) and the fourth zener diode (D4) are metal oxide semiconductor diodes.
Optionally, the boost integrated circuit is a cmos packaged chip.
Optionally, the boosted integrated circuit cmos packaging process granularity is 0.18 μm.
Optionally, the boost integrated circuit is a SOT-23 package.
Optionally, the method further comprises:
and the input filter circuit is connected with the positive electrode end of a fourth voltage stabilizing diode (D4) in the 1 st stage charge pump subcircuit of the charge pump circuit, and is also electrically connected with a high-frequency filter capacitor (Co 1) and a low-frequency filter capacitor (Co 2) in a bypass mode.
Optionally, the following peripheral circuits are also included:
the capacitance value of the high-frequency filter capacitor (Co 1) is 100PF,
the capacitance value of the low-frequency filter capacitor (Co 2) is 4.7 mu F.
Optionally, the following peripheral circuits are also included:
an output filter capacitor (Co 3) electrically connected between the cathode of the first zener diode (D1) of the Nth stage charge pump sub-circuit and ground;
an output load resistor (R1) is electrically connected in series with the negative terminal of the first zener diode (D1) of the Nth stage charge pump sub-circuit to externally output the supply voltage.
As can be seen from the above, by applying the technical solution of the embodiment of the present invention, the circuit structure adopted in the boost integrated circuit provided in this embodiment can adjust the capacitance values C of the first parasitic capacitors CS1, CS2, and CS3 and the stage number of the charge pump according to the actual conditions (the input low-voltage parameter, the required output voltage parameter), so that the circuit structure has stronger adjustment flexibility according to the actual requirements.
In addition, the boost integrated circuit of the embodiment adopts a CMOS packaging IC chip form, and has a small size, a stable structure and better anti-interference performance.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention:
fig. 1 is a schematic block diagram of a schematic structure of a boost integrated circuit according to embodiment 1 of the present invention;
fig. 2 is a schematic circuit diagram of an implementation circuit of the charge pump circuit in fig. 1 according to embodiment 1 of the present invention;
fig. 3 is a schematic circuit structure diagram of a boost integrated circuit with a peripheral circuit according to embodiment 1 of the present invention.
Detailed Description
The present invention will now be described in detail with reference to the drawings and specific embodiments, wherein the exemplary embodiments and descriptions of the present invention are provided to explain the present invention without limiting the invention thereto.
Example 1:
referring to fig. 1 to 3, the boost integrated circuit 100 provided in this embodiment mainly includes the following three parts: a clock oscillation circuit 101, acharge pump circuit 102, and avoltage stabilizing circuit 103.
The clock oscillation circuit 101 is electrically connected to thecharge pump circuit 102, the clock oscillation circuit 101 is configured to provide a clock frequency signal for thecharge pump circuit 102, an input end of the low noise circuit is externally connected to an external input low voltage signal, and an output end of the low noise circuit is electrically connected to thevoltage stabilizing circuit 103.
Thecharge pump circuit 102 includes N stages of charge pump sub-circuits, which are sequentially cascaded, and an output load circuit, where N is a natural number, such as 1, 2, and 3 … … N.
Each stage of charge pump sub-circuit is respectively composed of a first voltage stabilizing diode D1, a second voltage stabilizing diode D2, a third voltage stabilizing diode D3, a fourth voltage stabilizing diode D4, a first parasitic capacitor CS1, a second parasitic capacitor CS2, a third parasitic capacitor CS3, a first load capacitor C1, a second load capacitor C2 and a third load capacitor C3.
The first zener diode D1, the second zener diode D2, the third zener diode D3 and the fourth zener diode D4 have the same electrical parameters, and the first parasitic capacitor CS1, the second parasitic capacitor CS2 and the third parasitic capacitor CS3 have the same electrical parameters.
In the charge pump subcircuits of each stage, the circuit connection relationship is as follows:
the first zener diode D1, the second zener diode D2, the third zener diode D3, and the fourth zener diode D4 are electrically connected in series with each other.
The first parasitic capacitor CS1 is electrically connected between the cathode of the second zener diode D2 and the ground terminal; the third parasitic capacitor CS3 is electrically connected between the cathode of the third zener diode D3 and the ground terminal; the second parasitic capacitor CS2 is electrically connected between the cathode of the fourth zener diode D4 and the ground.
The third load capacitor C3 point is connected between the cathode of the voltage stabilizing diode D4 and the first input end of the clock frequency signal;
the second load capacitor C2 point is connected between the cathode of the voltage stabilizing diode D3 and the second input end of the clock frequency signal;
the first load capacitor C1 is connected between the cathode of the zener diode D2 and the first input terminal of the clock frequency signal.
The connection relationship between the wholecharge pump circuit 102 and thevoltage stabilizing circuit 103 and the external input and output is as follows: the positive terminal of a fourth voltage stabilizing diode D4 in the 1 st-stage charge pump sub-circuit can be externally connected with an external low-voltage electric signal, and the negative terminal of a first voltage stabilizing diode D1 of the Nth-stage charge pump sub-circuit outputs a required high-voltage electric signal outwards through the voltage stabilizer.
The voltage stabilizer is as follows: the first voltage stabilizing diode D1 of the Nth level charge pump subcircuit outputs the required high-voltage electric signal to the outside through the voltage stabilizer: specifically, one end of the RC filter circuit is electrically connected to the cathode of the first zener diode D1 of the nth stage charge pump sub-circuit, and the other end is grounded.
Referring to fig. 2, it is assumed that the clock frequency provided by the clock oscillation circuit 101 is fosc, which may be, but is not limited to, 2 MHZ), Cs is the capacitance value of the first parasitic capacitor Cs1, the second parasitic capacitor Cs2, and the third parasitic capacitor Cs3 is Cs, the voltage drop of the first zener diode D1, the second zener diode D2, the third zener diode D3, and the fourth zener diode D4 is Vd (which may be, but is not limited to, 0.3V), the load current is Iout (which may be, but is not limited to, 50 μ a), and the capacitance value of the load capacitor C1, C2, and C3 is C.
As can be seen from the circuit of fig. 2, the output voltage Vout can be determined according to the following equation:
Vout=Vin+N*{（C∕(C+Cs) *Vd-Vd-Iout∕[(C+Cs)*Fosc]}-Vd；
as can be seen from the above formula, the output value of the output voltage Vout can be changed by changing the N value as well as the C value in the present embodiment.
For example, when the boost integrated circuit 100 provided by the present embodiment is applied to a tuner, i.e. the input voltage of the boost integrated circuit 100 takes a commonly used low-voltage electrical signal +5V, and the +5V low-voltage electrical signal is boosted to a +33V high-voltage electrical signal, i.e. a +33V electrical signal is output, the capacitance C of the first load capacitors C1, C2, and C3 in the formula and the number N of stages of the charge pump can be determined according to the input voltage and the output voltage when the boost integrated circuit 100 of the present invention is applied to the tuner.
As can be seen from the above, the circuit structure adopted in the boost integrated circuit 100 provided in this embodiment is flexible, and can be flexibly determined according to various actual needs by adjusting the capacitance values C of the first parasitic capacitors CS1, CS2, and CS3 and the number of stages of the charge pump according to actual situations, so that the flexibility of circuit design is stronger.
In this embodiment, the boost integrated circuit 100 of this embodiment may be packaged in the form of an IC chip, which may be but is not limited to: the SOT-23 chip, as shown in FIG. 3, has three pins, wherepin 301 is a ground terminal,pin 302 is an input access terminal, and pin 303 is a voltage output terminal.
The integrated circuit of this embodiment is preferably manufactured by a Complementary Metal Oxide Semiconductor (CMOS) integrated circuit manufacturing process, so as to obtain a CMOS integrated circuit chip.
The first zener diode D1, the second zener diode D2, the third zener diode D3 and the fourth zener diode D4 in this embodiment are preferably metal oxide semiconductor diodes (built-up MOS diodes), which are compatible with CMOS processes of integrated IC chips without adding a mask during the manufacturing process to increase the manufacturing cost.
In the present embodiment, the boost integrated circuit 100IC chip of the present embodiment is preferably manufactured by a CMOS process with a grain size of 0.18 μm.
The performance of the whole circuit can be more stable by adopting the mode of an integrated circuit IC chip, and the volume of the circuit is small.
Referring to fig. 3, in the practical application of the boost integrated circuit 100 of the present embodiment, a peripheral circuit may be further overlapped according to the boost integrated circuit 100 of the present embodiment: and input to a filter circuit. The input filter circuit may be composed of a high frequency filter capacitor Co1 and a low frequency filter capacitor C2 electrically connected to the input pin 302 (actually, the cathode terminal of the fourth zener diode D4 electrically connected to the 1 st stage charge pump sub-circuit of the boost integrated circuit 100), respectively. The capacitance of the high-frequency filter capacitor Co1 may be, but is not limited to, 100PF, and the capacitance of the low-frequency filter capacitor Co2 may be, but is not limited to, 4.7 μ F. Thus, the interference signal in the low-voltage electrical signal can be removed from the high-frequency and low-frequency interference signals before being input into the boost integrated circuit 100 of the present embodiment, so that the stability of the input signal source is higher, and the interference of the output electrical signal is reduced.
Referring to fig. 3, in the practical application of the boost integrated circuit 100 of the present embodiment, a peripheral circuit may be further overlapped according to the boost integrated circuit 100 of the present embodiment: the output filter load circuit specifically comprises an output filter capacitor C3 and an output load resistor R1. The output filter capacitor Co3 is electrically connected to theoutput pin 303 of the boosting ic 100 of this embodiment (actually, the cathode of the first zener diode D1 of the nth-stage charge pump sub-circuit in the boosting ic 100) in a side-by-side manner, and the output load resistor R1 is electrically connected to theoutput pin 303 of the boosting ic 100 of this embodiment (actually, the cathode of the first zener diode D1 of the nth-stage charge pump sub-circuit in the boosting ic 100) in a series manner to output the externally supplied power voltage. In this way, before the high piezoelectric signal externally output by the boost integrated circuit 100 of the present embodiment is input to an external power consumption component (such as a tuner in the present embodiment), the high piezoelectric signal is filtered by the bypass output filter capacitor Co3 in advance, and the power consumption voltage VTu of +33V is output to the power consumption component through the voltage division of the output load resistor R1, the resistance value of the output load resistor R1 may be selected according to actual needs, in the present embodiment, the capacitance value of the output filter capacitor Co3 is 2.2nF, and the resistance value of the output load resistor R1 is 270K Ω.
The technical solutions provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by using specific examples, and the descriptions of the embodiments are only used to help understanding the principles of the embodiments of the present invention; meanwhile, for a person skilled in the art, according to the embodiments of the present invention, there may be variations in the specific implementation manners and application ranges, and in summary, the content of the present description should not be construed as a limitation to the present invention.
Claims (9)
1. A boost integrated circuit, comprising: a clock oscillation circuit, a charge pump circuit, and a voltage stabilizing circuit, wherein,
the clock oscillation circuit is electrically connected with the charge pump circuit and is used for providing a clock frequency signal for the charge pump circuit,
the input end of the low-noise circuit is externally connected with an external input low-voltage signal, and the output end of the low-noise circuit is electrically connected with the voltage stabilizing circuit; wherein,
the charge pump circuit comprises a charge pump subcircuit and an output load circuit which are sequentially cascaded by N stages, wherein N is a natural number;
each charge pump sub-circuit includes:
a first voltage regulator diode (D1), a second voltage regulator diode (D2), a third voltage regulator diode (D3) and a fourth voltage regulator diode (D4) which are mutually and electrically connected in series and have the same electrical parameter,
a first parasitic capacitor (CS 1), a second parasitic capacitor (CS 2) and a third parasitic capacitor (CS 3) which are respectively and electrically connected between the negative terminal and the ground terminal of the second voltage-regulator diode (D2), the third voltage-regulator diode (D3) and the fourth voltage-regulator diode (D4) and have the same electrical parameter,
a third load capacitor (C3) electrically connected between the negative terminal of the zener diode D4 and the first input terminal of the clock frequency signal,
a second load capacitor (C2) electrically connected between the negative terminal of the zener diode D3 and the second input terminal of the clock frequency signal,
a first load capacitor (C1) electrically connected between the negative terminal of the zener diode D2 and the first input terminal of the clock frequency signal,
wherein the electrical parameters of the first load capacitor (C1), the second load capacitor (C2), and the third load capacitor (C3) are the same;
the positive electrode end of a fourth voltage stabilizing diode (D4) in the 1 st-level charge pump sub-circuit can be externally connected with the external low-voltage electric signal, and the negative electrode of a first voltage stabilizing diode (D1) of the Nth-level charge pump sub-circuit outputs a required high-voltage electric signal outwards through the voltage stabilizer.
2. The boost integrated circuit of claim 1,
the voltage stabilizer is as follows: an RC filter circuit composed of a side-ground capacitor (Cout) and a side-ground resistor (R) connected in parallel,
the first voltage stabilizing diode (D1) of the Nth stage charge pump subcircuit outputs the required high-voltage electric signal outwards through the voltage stabilizer: in particular, the method comprises the following steps of,
one end of the RC filter circuit is electrically connected with the cathode of a first voltage stabilizing diode (D1) of the Nth-stage charge pump subcircuit, and the other end of the RC filter circuit is grounded.
3. The boost integrated circuit of claim 1,
the first voltage-regulator diode (D1), the second voltage-regulator diode (D2), the third voltage-regulator diode (D3) and the fourth voltage-regulator diode (D4) are metal oxide semiconductor diodes.
4. The boost integrated circuit of claim 1,
the boosting integrated circuit is a complementary metal oxide semiconductor packaging chip.
5. The boost integrated circuit of claim 4,
the packaging process granularity of the boosting integrated circuit complementary metal oxide semiconductor is 0.18 mu m.
6. The boost integrated circuit of claim 4,
the boost integrated circuit is a SOT-23 package.
7. A boost integrated circuit according to any of claims 1 to 6, further comprising:
and the input filter circuit is connected with the positive electrode end of a fourth voltage stabilizing diode (D4) in the 1 st stage charge pump subcircuit of the charge pump circuit, and is also electrically connected with a high-frequency filter capacitor (Co 1) and a low-frequency filter capacitor (Co 2) in a bypass mode.
8. The boost integrated circuit of claim 7, further comprising the following peripheral circuits:
the capacitance value of the high-frequency filter capacitor (Co 1) is 100PF,
the capacitance value of the low-frequency filter capacitor (Co 2) is 4.7 mu F.
9. The boost integrated circuit of claim 1, further comprising the following peripheral circuits:
an output filter capacitor (Co 3) electrically connected between the cathode of the first zener diode (D1) of the Nth stage charge pump sub-circuit and ground;
an output load resistor (R1) is electrically connected in series with the negative terminal of the first zener diode (D1) of the Nth stage charge pump sub-circuit to externally output the supply voltage.
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| CN2011102390997ACN102957315A (en) | 2011-08-19 | 2011-08-19 | Boost integrated circuit for tuner |
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| CN2011102390997ACN102957315A (en) | 2011-08-19 | 2011-08-19 | Boost integrated circuit for tuner |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103490617A (en)* | 2013-08-29 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Negative voltage charge pump circuit |
| WO2015100631A1 (en)* | 2013-12-31 | 2015-07-09 | 无锡华润矽科微电子有限公司 | Silicon microphone and special integrated circuit therein |
| CN106406418A (en)* | 2015-07-28 | 2017-02-15 | 株式会社电装 | Switching element driving circuit |
| CN110326205A (en)* | 2017-01-30 | 2019-10-11 | ams有限公司 | Electric pressure converter and the method converted for voltage |
| CN111490675A (en)* | 2019-01-29 | 2020-08-04 | 合肥格易集成电路有限公司 | Charge pump circuit, nonvolatile memory and method for controlling output voltage of charge pump |
| CN113824317A (en)* | 2021-10-28 | 2021-12-21 | 福州京东方光电科技有限公司 | A charge pump and power drive circuit, display |
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| CN101034536A (en)* | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | A charge pump circuit in a TFT driving circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101034536A (en)* | 2006-03-08 | 2007-09-12 | 天利半导体（深圳）有限公司 | A charge pump circuit in a TFT driving circuit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490617A (en)* | 2013-08-29 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Negative voltage charge pump circuit |
| WO2015100631A1 (en)* | 2013-12-31 | 2015-07-09 | 无锡华润矽科微电子有限公司 | Silicon microphone and special integrated circuit therein |
| CN106406418A (en)* | 2015-07-28 | 2017-02-15 | 株式会社电装 | Switching element driving circuit |
| CN110326205A (en)* | 2017-01-30 | 2019-10-11 | ams有限公司 | Electric pressure converter and the method converted for voltage |
| US10972004B2 (en) | 2017-01-30 | 2021-04-06 | Ams Ag | Voltage converter and method for voltage conversion |
| CN111490675A (en)* | 2019-01-29 | 2020-08-04 | 合肥格易集成电路有限公司 | Charge pump circuit, nonvolatile memory and method for controlling output voltage of charge pump |
| CN113824317A (en)* | 2021-10-28 | 2021-12-21 | 福州京东方光电科技有限公司 | A charge pump and power drive circuit, display |
| CN113824317B (en)* | 2021-10-28 | 2022-11-11 | 福州京东方光电科技有限公司 | Charge pump, power supply driving circuit and display |
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