技术领域technical field
本发明涉及电子技术领域，具体涉及一种现场可编程门阵列的加载方法、装置及系统。The invention relates to the field of electronic technology, in particular to a method, device and system for loading a field programmable gate array.
背景技术Background technique
目前，现场可编程门阵列（Field Programmable Gate Array，简称FPGA）技术普遍应用于各种专用集成电路，是集成度最高的一项技术，为小批量系统提高系统集成度、可靠性的最佳选择之一。FPGA芯片的工作状态是由存放在芯片内的RAM中的程序来设置的，因此，需对FPGA芯片内的RAM进行编程配置。用户可以采用不同的配置方式应用于FPGA芯片，所以每次上电，需要先对FPGA芯片进行程序加载，才能正常使用FPGA芯片。因此，应用FPGA芯片时，数据及程序的加载技术是不可缺少的一种应用，加载速度和加载质量是FPGA技术应用的关键指标。At present, Field Programmable Gate Array (Field Programmable Gate Array, referred to as FPGA) technology is widely used in various application-specific integrated circuits. It is the most integrated technology and the best choice for improving system integration and reliability for small batch systems. one. The working state of the FPGA chip is set by the program stored in the RAM in the chip. Therefore, the RAM in the FPGA chip needs to be programmed and configured. Users can use different configuration methods to apply to the FPGA chip, so every time the power is turned on, the FPGA chip needs to be loaded with programs before the FPGA chip can be used normally. Therefore, when using FPGA chips, data and program loading technology is an indispensable application, and loading speed and loading quality are key indicators for FPGA technology applications.
现有应用FPGA芯片的电路中，为了节省系统IO端口数量，普遍应用被动配置方式实现FPGA芯片的程序及数据的加载，主要由外部计算机或控制器控制FPGA芯片的配置过程。配置期间，数据从外部储存部件，通过数据输入引脚送入FPGA芯片，1个时钟周期传送1位数据。不管配置的数据源从哪里来，只要可以模拟出FPGA芯片需要的配置时序来，将配置数据写入FPGA芯片就可以。配置完成后，内部寄存器以及I/O管脚必须进行初始化，等到初始化完成以后，芯片才会按照用户设计的功能正常工作。然而，每传输1位数据就需要读取反馈信号，如此传输总线会产生两次传输操作，影响到了数据的加载速度，反馈信号的同时还需要等待数据的到来后，再进行加载，进而产生了加载空隙。In existing circuits using FPGA chips, in order to save the number of system IO ports, the passive configuration method is generally used to load the program and data of the FPGA chip, and the configuration process of the FPGA chip is mainly controlled by an external computer or controller. During configuration, data is sent from the external storage unit to the FPGA chip through the data input pin, and 1 bit of data is transmitted in 1 clock cycle. Regardless of where the configuration data source comes from, as long as the configuration timing required by the FPGA chip can be simulated, the configuration data can be written into the FPGA chip. After the configuration is completed, the internal registers and I/O pins must be initialized. After the initialization is completed, the chip will work normally according to the functions designed by the user. However, the feedback signal needs to be read every time one bit of data is transmitted, so that the transmission bus will generate two transmission operations, which affects the data loading speed, and the feedback signal needs to wait for the arrival of the data before loading, which in turn generates Load void.
现有的也有通过延时设计取消反馈信号的传输，确保延时时间内当前数据已被写入后再写入新的数据，虽然减轻了传输总线的操作负担，一定程度上提升了加载速度，然而依旧会产生加载空隙，同时加载可靠性有所降低，极易出现写入数据有延迟，延迟时间超过预设值，进而加载数据被冲掉致使整体加载失败，降低了加载效率。The existing ones also cancel the transmission of the feedback signal through the delay design to ensure that the current data has been written within the delay time before writing new data. Although the operational burden of the transmission bus is reduced, the loading speed is improved to a certain extent. However, there will still be loading gaps, and at the same time, the reliability of loading will be reduced. It is very easy to delay the writing of data. The delay time exceeds the preset value, and then the loaded data will be flushed out, resulting in the overall loading failure and reducing the loading efficiency.
发明内容Contents of the invention
本发明实施例提供了一种现场可编程门阵列的加载方法、装置及系统，解决了现有现场可编程门阵列的加载速度低和加载质量低的问题。Embodiments of the present invention provide a field programmable gate array loading method, device and system, which solve the problems of low loading speed and low loading quality of the existing field programmable gate array.
本发明实施例的第一方面提供的一种现场可编程门阵列的加载方法，包括：A method for loading a field programmable gate array provided in the first aspect of an embodiment of the present invention includes:
获取处理器传送过来的数据；Get the data sent by the processor;
判断缓存区存储的数据量是否在预设范围内，如果是，将所述数据存储至缓存区，并且通知所述处理器继续传输数据；judging whether the amount of data stored in the buffer area is within a preset range, if so, storing the data in the buffer area, and notifying the processor to continue transmitting data;
以及，将所述缓存区中的数据加载至所述现场可编程门阵列。And, loading the data in the buffer area to the field programmable gate array.
在第一种可能的实现方式中，所述判断缓存区存储的数据量是否在预设范围内包括：In a first possible implementation manner, the judging whether the amount of data stored in the cache area is within a preset range includes:
判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果是，则确认缓存区存储的数据量在预设范围内；所述缓存区的水线值L用于标识所述缓存区的存储空间的使用情况。Judging whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, if yes, confirming that the amount of data stored in the buffer area is within a preset range; the waterline value L of the buffer area is used to identify the The usage of the storage space of the cache area.
结合第一方面的第一种可能的实现方式，在第二种可能实现方式中，所述方法还包括：With reference to the first possible implementation of the first aspect, in a second possible implementation, the method further includes:
若所述缓存区存储的数据量大于或等于所述缓存区的水线值L，则发送所述缓存区数据存储量将满指示给所述处理器，以指示所述处理器停止传送数据；If the amount of data stored in the buffer is greater than or equal to the waterline value L of the buffer, then sending an indication that the amount of data stored in the buffer will be full to the processor to instruct the processor to stop transmitting data;
继续判断缓存区存储的数据量是否小于所述缓存区的水线值L。Continue to judge whether the amount of data stored in the buffer is smaller than the waterline value L of the buffer.
结合第一方面、第一方面的第一种可能的实现方式或者第二种可能的实现方式，在第三种可能的实现方式中，所述通知所述处理器继续传输数据包括：With reference to the first aspect, the first possible implementation manner of the first aspect, or the second possible implementation manner, in a third possible implementation manner, the notifying the processor to continue transmitting data includes:
发送所述缓存区数据存储量未满指示给所述处理器，以指示所述处理器继续传送数据。Sending an indication that the amount of data stored in the buffer area is not full to the processor, so as to instruct the processor to continue transmitting data.
结合第一方面的第一种可能的实现方式，在第四种可能的实现方式中，所述获取所述处理器传送过来的数据包括：With reference to the first possible implementation manner of the first aspect, in a fourth possible implementation manner, the acquiring the data transmitted by the processor includes:
获取所述处理器通过数据总线在n个周期T内传送的数据，所述n>0，所述T>0。Obtain the data transmitted by the processor in n cycles T through the data bus, where n>0 and T>0.
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述将所述缓存区中的数据加载至所述现场可编程门阵列包括：With reference to the fourth possible implementation of the first aspect, in a fifth possible implementation, loading the data in the buffer area to the field programmable gate array includes:
将所述缓存区中的数据通过加载线以t为周期，1bits/t为加载速度加载至所述现场可编程门阵列，所述t大于0。The data in the buffer area is loaded to the field programmable gate array through the loading line at a period of t and a loading speed of 1 bits/t, and the t is greater than 0.
结合第一方面的第五种可能的实现方式，在第六种可能的实现方式中，所述缓存区存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，所述N为所述周期T内传送的数据量。In combination with the fifth possible implementation of the first aspect, in the sixth possible implementation, the maximum amount of data stored in the cache area is Hmax, then n needs to satisfy the inequality 0<N/T*nT- (n+1)T/t<Hmax; wherein, the N is the amount of data transmitted in the period T.
结合第一方面的第六种可能的实现方式中，在第七种可能的实现方式中，所述判断所述缓存区存储的数据量是否小于所述缓存区的水线值L包括：With reference to the sixth possible implementation manner of the first aspect, in the seventh possible implementation manner, the judging whether the amount of data stored in the buffer area is smaller than the watermark value L of the buffer area includes:
判断n值是否满足预设条件，所述预设条件为0<N/T*nT-（n+1）T/t<L；Judging whether the n value satisfies the preset condition, the preset condition is 0<N/T*nT-(n+1)T/t<L;
如果是，则确定所述缓存区存储的数据量小于所述缓存区的水线值L；如果否，则确定所述缓存区存储的数据量大于或等于所述缓存区的水线值L。If yes, determine that the amount of data stored in the buffer is less than the waterline value L of the buffer; if not, determine that the amount of data stored in the buffer is greater than or equal to the waterline L of the buffer.
结合第一方面的第七种可能的实现方式，在第八种可能的实现方式中，所述n满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足所述缓存区在下一n个周期T内获取的数据小于且等于所述Hleft，所述Hleft为所述缓存区存储的数据量的最大值为Hmax与所述缓存区的水线值L的差值。In combination with the seventh possible implementation of the first aspect, in the eighth possible implementation, the n satisfies the inequality 0<N/T*nT-(n+1)T/t<Hleft, so as to satisfy all The data acquired by the buffer area in the next n periods T is less than and equal to the Hleft, and the Hleft is the maximum value of the amount of data stored in the buffer area is the difference between Hmax and the waterline value L of the buffer area .
结合第一方面的第五种可能的实现方式，在第九种可能的实现方式中，所述缓存区的水线值L需满足不等式L>2T/t，以满足所述缓存区通过所述加载线以t为周期，1bits/t为加载速度连续地加载数据至所述现场可编程门阵列。With reference to the fifth possible implementation of the first aspect, in a ninth possible implementation, the waterline value L of the buffer needs to satisfy the inequality L>2T/t, so that the buffer passes through the The loading line continuously loads data to the FPGA with a period of t and a loading speed of 1 bits/t.
本发明实施例的第二方面提供了一种现场可编程门阵列的加载装置，包括：A second aspect of the embodiments of the present invention provides a loading device for a field programmable gate array, including:
获取单元，用于获取处理器传送过来的数据；an acquisition unit, configured to acquire data transmitted by the processor;
判断单元，用于判断缓存区存储的数据量是否在预设范围内；a judging unit, configured to judge whether the amount of data stored in the buffer area is within a preset range;
所述缓存区，用于根据所述判断单元判断为是的结果存储所述数据；The buffer area is used to store the data according to the result judged to be yes by the judging unit;
发送单元，用于根据所述判断单元判断为是的结果发送通知至所述处理器，以通知所述处理器继续传送数据；a sending unit, configured to send a notification to the processor according to a result determined to be yes by the judging unit, so as to notify the processor to continue transmitting data;
所述发送单元，还用于将所述缓存区中的数据加载至所述现场可编程门阵列。The sending unit is further configured to load the data in the buffer area to the field programmable gate array.
在第一种可能的实现方式中，所述判断单元，具体用于判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果是，则确认缓存区存储的数据量是在预设范围内；所述缓存区的水线值L用于标识所述缓存区的存储空间的使用情况。In a first possible implementation manner, the judging unit is specifically configured to judge whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, and if so, confirm that the amount of data stored in the buffer area is within Within a preset range; the waterline value L of the cache area is used to identify the usage of the storage space of the cache area.
结合第二方面的第一种可能的实现方式，在第二种可能的实现方式中，所述发送单元，还用于根据所述判断单元判断为否的结果，发送所述缓存区数据存储量将满指示给所述处理器，以指示所述处理器停止传送数据；With reference to the first possible implementation of the second aspect, in a second possible implementation, the sending unit is further configured to send the buffer data storage amount indicating full to the processor to instruct the processor to stop transferring data;
所述判断单元，还用于根据所述判断单元判断为否的结果，继续判断所述缓存区存储的数据量是否小于所述缓存区的水线值L。The judging unit is further configured to continue judging whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area according to the result of the judging unit judging No.
结合第二方面、第二方面的第一种可能的实现方式或者第二方面的第二种可能的实现方式，在第三种可能的实现方式中，所述发送单元，具体用于根据所述判断单元判断为是的结果发送所述缓存区数据存储量未满指示给所述处理器，以指示所述处理器继续传送数据。With reference to the second aspect, the first possible implementation of the second aspect, or the second possible implementation of the second aspect, in a third possible implementation, the sending unit is specifically configured to If the judging unit judges yes, it sends an indication that the data storage capacity of the buffer area is not full to the processor, so as to instruct the processor to continue to transmit data.
结合第二方面的第一种可能的实现方式，在第四种可能的实现方式中，所述获取单元，具体用于获取所述处理器通过数据总线在n个周期T内传送的数据，所述n>0，所述T>0。With reference to the first possible implementation manner of the second aspect, in a fourth possible implementation manner, the acquiring unit is specifically configured to acquire the data transmitted by the processor in n cycles T through the data bus, so Said n>0, said T>0.
结合第二方面的第四种可能的实现方式，在第五种可能的实现方式中，所述发送单元，具体用于将所述缓存区中的数据通过加载线以t为周期，1bits/t为加载速度加载至所述现场可编程门阵列，所述t大于0。With reference to the fourth possible implementation of the second aspect, in the fifth possible implementation, the sending unit is specifically configured to pass the data in the buffer area through the loading line at a cycle of t, 1bits/t For loading speed into the FPGA, the t is greater than 0.
结合第二方面的第五种可能的实现方式，在第六种可能的实现方式中，所述缓存区存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，所述N为所述周期T内传送的数据量。In combination with the fifth possible implementation of the second aspect, in the sixth possible implementation, the maximum value of the amount of data stored in the buffer area is Hmax, then n needs to satisfy the inequality 0<N/T*nT- (n+1)T/t<Hmax; wherein, the N is the amount of data transmitted in the period T.
结合第二方面的第六种可能的实现方式，在第七种可能的实现方式中，所述判断单元，具体用于判断n值是否满足预设条件，所述预设条件为0<N/T*nT-（n+1）T/t<L；如果是，则确定所述缓存区存储的数据量小于所述缓存区的水线值L；如果否，则确定所述缓存区存储的数据量大于或等于所述缓存区的水线值L。With reference to the sixth possible implementation manner of the second aspect, in a seventh possible implementation manner, the judging unit is specifically configured to judge whether the value of n satisfies a preset condition, and the preset condition is 0<N/ T*nT-(n+1)T/t<L; if yes, determine that the amount of data stored in the cache is less than the waterline value L of the cache; if not, determine that the amount of data stored in the cache is The amount of data is greater than or equal to the waterline value L of the buffer.
结合第二方面的第七种可能的实现方式，在第八种可能的实现方式中，所述n还需满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足所述缓存区在下一n个周期T内获取的数据小于且等于所述Hleft，所述Hleft为所述缓存区存储的数据量的最大值为Hmax与所述缓存区的水线值L的差值。In combination with the seventh possible implementation of the second aspect, in the eighth possible implementation, the n also needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hleft, so that It is satisfied that the data acquired by the buffer area in the next n period T is less than and equal to the Hleft, and the maximum value of the data stored by the Hleft in the buffer area is the ratio of Hmax and the waterline value L of the buffer area difference.
结合第二方面的第五种可能的实现方式，在第九种可能的实现方式中，所述缓存区的水线值L需满足不等式L>2T/t，以满足所述缓存区通过所述加载线以t为周期，1bits/t为加载速度连续地加载数据至所述现场可编程门阵列。With reference to the fifth possible implementation of the second aspect, in a ninth possible implementation, the waterline value L of the buffer needs to satisfy the inequality L>2T/t, so that the buffer passes the The loading line continuously loads data to the FPGA with a period of t and a loading speed of 1 bits/t.
本发明实施例的第三方面提供了一种现场可编程门阵列的加载系统，包括：处理器、加载装置和现场可编程门阵列，所述加载装置包括缓存区；A third aspect of the embodiments of the present invention provides a loading system for a field programmable gate array, including: a processor, a loading device and a field programmable gate array, the loading device includes a buffer area;
其中，所述处理器，用于传送数据至所述加载装置；Wherein, the processor is configured to transmit data to the loading device;
所述加载装置，用于获取所述处理器传送过来的数据，判断所述缓存区存储的数据量是否在预设范围内，如果是，将所述数据存储至所述缓存区，并且通知所述处理器继续传输数据；以及用于将所述缓存区中的数据加载至所述现场可编程门阵列；The loading device is used to obtain the data transmitted by the processor, determine whether the amount of data stored in the buffer area is within a preset range, and if so, store the data in the buffer area and notify the The processor continues to transmit data; and is used to load the data in the buffer area to the field programmable gate array;
所述处理器，还用于接收所述加载装置发送的触发所述处理器继续传输数据的通知，以继续传送数据至所述加载装置；The processor is also configured to receive a notification sent by the loading device that triggers the processor to continue to transmit data, so as to continue to transmit data to the loading device;
所述现场可编程门阵列，用于配置所述加载装置加载的数据。The field programmable gate array is used to configure the data loaded by the loading device.
在第一种可能的实现方式中，所述加载装置，具体用于判断所述缓存区存储的数据量是否小于所述缓存区的水线值L，如果是，则确认所述缓存区存储的数据量在预设范围内；所述缓存区的水线值L用于标识所述缓存区的存储空间的使用情况。In a first possible implementation manner, the loading device is specifically configured to determine whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, and if so, confirm that the amount of data stored in the buffer area The amount of data is within a preset range; the waterline value L of the cache area is used to identify the usage of the storage space of the cache area.
结合第三方面的第一种可能的实现方式，在第二种可能的实现方式中，所述加载装置，还用于根据所述缓存区存储的数据量大于或等于所述缓存区的水线值L的判断结果发送所述缓存区数据存储量将满指示给所述处理器，以指示所述处理器停止传送数据，并继续判断所述缓存区存储的数据量是否小于所述缓存区的水线值L；With reference to the first possible implementation of the third aspect, in a second possible implementation, the loading device is further configured to store data in the buffer greater than or equal to the waterline of the buffer The judgment result of the value L sends the data storage amount of the buffer area to be full to indicate to the processor, to instruct the processor to stop transmitting data, and continue to judge whether the amount of data stored in the buffer area is less than the amount of data stored in the buffer area Waterline value L;
所述处理器，还用于接收所述加载装置发送的所述缓存区数据存储量将满指示，以停止传送数据至所述加载装置。The processor is further configured to receive an indication from the loading device that the data storage capacity of the buffer area is about to be full, so as to stop transmitting data to the loading device.
结合第三发面、第一种可能的实现方式或者第二种可能的实现方式，在第三种可能的实现方式中，所述加载装置，具体用于发送所述缓存区数据存储量未满指示给所述处理器，以指示所述处理器继续传送数据；With reference to the third aspect, the first possible implementation, or the second possible implementation, in the third possible implementation, the loading device is specifically configured to send instructing the processor to instruct the processor to continue transferring data;
所述处理器，具体用于接收所述加载装置发送的所述缓存区数据存储量未满指示，以继续传送数据至所述加载装置。The processor is specifically configured to receive an indication from the loading device that the data storage capacity of the buffer is not full, so as to continue to transmit data to the loading device.
结合第三方面的第一种可能的实现方式，在第四种可能的实现方式中，所述处理器具体用于通过数据总线在n个周期T内传送数据至所述加载装置；With reference to the first possible implementation manner of the third aspect, in a fourth possible implementation manner, the processor is specifically configured to transmit data to the loading device within n cycles T through a data bus;
所述加载装置，具体用于获取所述处理器通过数据总线在n个周期T内传送的数据；所述n>0，所述T>0。The loading device is specifically used to obtain the data transmitted by the processor in n cycles T through the data bus; the n>0, and the T>0.
结合第四种可能的实现方式，在第五种可能的实现方式中，所述加载装置，具体用于通过加载线以t为周期，1bits/t为加载速度连续地加载数据至所述现场可编程门阵列，所述t大于0；With reference to the fourth possible implementation, in the fifth possible implementation, the loading device is specifically used to continuously load data to the field available via the loading line at a period of t and a loading speed of 1 bits/t. programming gate array, the t is greater than 0;
所述现场可编程门阵列，具体用于配置所述加载装置通过加载线以t为周期，1bits/t为加载速度连续加载的数据。The field programmable gate array is specifically used to configure the loading device to continuously load data with a period of t and a loading speed of 1 bits/t through the loading line.
结合第五种可能的实现方式，在第六种可能的实现方式中，所述缓存区存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，所述N为所述周期T内传送的数据量。In combination with the fifth possible implementation, in the sixth possible implementation, the maximum amount of data stored in the cache area is Hmax, then n needs to satisfy the inequality 0<N/T*nT-(n+1 ) T/t<Hmax; wherein, the N is the amount of data transmitted in the period T.
结合第六种可能的实现方式，在第七种可能的实现方式中，所述加载装置，具体用于判断n值是否满足预设条件，所述预设条件为0<N/T*nT-（n+1）T/t<L；With reference to the sixth possible implementation, in the seventh possible implementation, the loading device is specifically used to judge whether the value of n satisfies a preset condition, and the preset condition is 0<N/T*nT- (n+1)T/t<L;
如果是，则确定所述缓存区存储的数据量小于所述缓存区的水线值L；如果否，则确定所述缓存区存储的数据量大于或等于所述缓存区的水线值L。If yes, determine that the amount of data stored in the buffer is less than the waterline value L of the buffer; if not, determine that the amount of data stored in the buffer is greater than or equal to the waterline L of the buffer.
结合第七种可能的实现方式，在第八种可能的实现方式中，所述n还需满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足所述缓存区在下一n个周期T内获取的数据小于且等于所述Hleft，所述Hleft为所述缓存区存储的数据量的最大值为Hmax与所述缓存区的水线值L的差值。In combination with the seventh possible implementation, in the eighth possible implementation, the n also needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hleft, so as to satisfy the cache The data acquired by the area in the next n periods T is less than and equal to the Hleft, and the maximum value of the data stored by the Hleft in the buffer area is the difference between Hmax and the waterline value L of the buffer area.
结合第五种可能的实现方式，在第九种可能的实现方式中，所述缓存区的水线值L需满足不等式L>2T/t，以满足所述加载装置通过所述加载线以t为周期，1bits/t为加载速度连续地加载数据至所述现场可编程门阵列。With reference to the fifth possible implementation, in the ninth possible implementation, the waterline value L of the buffer area needs to satisfy the inequality L>2T/t, so that the loading device passes through the loading line at t is a period, and 1bits/t is a loading speed to continuously load data to the FPGA.
本发明实施例提供的现场可编程门阵列的加载方法、装置及系统，通过设置一缓存区，判断所述缓存区存储的数据量是否在预设范围内；如果是，则发送缓存区数据存储量未满指示给所述处理器，以指示所述处理器继续传送数据，以继续获取所述处理器通过所述数据总线传送的数据；如果否，则发送缓存区数据存储量将满指示给所述处理器，以指示所述处理器停止传送数据，并继续判断所述缓存区存储的数据量是否在预设范围内。不仅保证了加载数据的可靠性，不会冲掉数据，同时实现了快速加载，避免了加载空隙的现象发生。进一步地可以通过数据总线连续传输多个周期的数据，再发送一次指示信号触发所述处理器读取反馈信号，使得加载方法的配置更加灵活，加载装置的实现更加优化，提升了整个现场可编程门阵列的加载系统的加载性能。The field programmable gate array loading method, device and system provided by the embodiments of the present invention determine whether the amount of data stored in the buffer area is within a preset range by setting a buffer area; if so, send the buffer area data storage The amount is not full to indicate to the processor, to instruct the processor to continue to transmit data, to continue to obtain the data transmitted by the processor through the data bus; The processor is configured to instruct the processor to stop transmitting data, and continue to determine whether the amount of data stored in the buffer area is within a preset range. It not only guarantees the reliability of the loaded data and will not wash out the data, but also realizes fast loading and avoids the phenomenon of loading gaps. Furthermore, multiple periods of data can be continuously transmitted through the data bus, and an indication signal is sent again to trigger the processor to read the feedback signal, so that the configuration of the loading method is more flexible, the realization of the loading device is more optimized, and the entire field programmable Loading performance of gate array loading systems.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明实施例一提供的一种现场可编程门阵列的加载方法示意图；FIG. 1 is a schematic diagram of a method for loading a field programmable gate array provided by Embodiment 1 of the present invention;
图2为本发明实施例二提供的一种现场可编程门阵列的加载装置结构示意图；FIG. 2 is a schematic structural diagram of a loading device for a field programmable gate array provided by Embodiment 2 of the present invention;
图3为本发明实施例二提供的另一种现场可编程门阵列的加载装置结构示意图；FIG. 3 is a structural schematic diagram of another field programmable gate array loading device provided by Embodiment 2 of the present invention;
图4为本发明实施例三提供的一种现场可编程门阵列的加载系统结构示意图。FIG. 4 is a schematic structural diagram of a loading system for a field programmable gate array provided by Embodiment 3 of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
下面通过具体实施例，分别进行详细的说明。In the following, specific examples will be used to describe in detail respectively.
请参阅图1，图1为本发明实施例一提供的一种现场可编程门阵列的加载方法示意图。本实施例从一加载装置的角度叙述本实施例提供的现场可编程门阵列的加载方法。如图1所示，本实施例提供的现场可编程门阵列的加载方法包括以下步骤：Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a method for loading a field programmable gate array according to Embodiment 1 of the present invention. This embodiment describes the method for loading a field programmable gate array provided by this embodiment from the perspective of a loading device. As shown in Figure 1, the loading method of the field programmable gate array provided by this embodiment includes the following steps:
S110、获取处理器传送过来的数据；S110. Obtain the data transmitted by the processor;
S120、判断缓存区存储的数据量是否在预设范围内；S120. Determine whether the amount of data stored in the buffer area is within a preset range;
如果是，则执行步骤S130；如果否，则继续判断缓存区存储的数据量是否在预设范围内；If yes, then execute step S130; if no, then continue to judge whether the amount of data stored in the cache area is within a preset range;
S130、将数据存储至缓存区，并且通知处理器继续传输数据；S130. Store the data in the cache area, and notify the processor to continue transmitting the data;
S140、将缓存区中的数据加载至现场可编程门阵列。S140. Load the data in the buffer area to the field programmable gate array.
其中，只要缓存区中存在数据，则步骤S140的执行一直进行，没有间断。在初始化后第一次将数据存储至缓存区中后，步骤S140在本方法的实施中，没有执行顺序的区分，即连续地加载数据至现场可编程门阵列。Wherein, as long as there is data in the buffer area, the execution of step S140 will continue without interruption. After the data is stored in the cache area for the first time after initialization, step S140 is implemented in the method without distinction of execution sequence, that is, to continuously load data into the FPGA.
本实施例提供的现场可编程门阵列的加载方法，通过设置一缓存区，判断缓存区存储的数据量是否在预设范围内；如果是，则发送通知给处理器，触发处理器继续传送数据，以保证缓存区中一直有数据存储，可连续地向现场可编程门阵列加载数据，避免了加载空隙的现象发生，实现了给现场可编程门阵列快速加载数据的方法。The field programmable gate array loading method provided by this embodiment, by setting a buffer area, judges whether the amount of data stored in the buffer area is within a preset range; if yes, then sends a notification to the processor, triggering the processor to continue transmitting data , so as to ensure that there is always data stored in the buffer area, data can be continuously loaded to the field programmable gate array, the phenomenon of loading gaps is avoided, and a method for quickly loading data to the field programmable gate array is realized.
作为一种可选的实施方式，基于图1所示的步骤S120，可以具体包括：判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果是，则确认缓存区存储的数据量在预设范围内；所述缓存区的水线值L用于标识所述缓存区的存储空间的使用情况。As an optional implementation, based on step S120 shown in FIG. 1 , it may specifically include: judging whether the amount of data stored in the buffer is less than the waterline value L of the buffer, and if so, confirming the amount of data stored in the buffer The amount of data is within a preset range; the waterline value L of the cache area is used to identify the usage of the storage space of the cache area.
通过设置缓存区的水线值L作为判断标准，简单又可靠地实现了判断缓存区存储的数据量是否在预设范围内的方法，易实施。By setting the waterline value L of the buffer area as a judgment standard, the method of judging whether the amount of data stored in the buffer area is within a preset range is implemented simply and reliably, and is easy to implement.
作为一种可选的实施方式，若所述缓存区存储的数据量大于或等于所述缓存区的水线值L，即缓存区存储的数据量不在预设范围内，本实施例提供的现场可编程门阵列的加载方法还包括：发送缓存区数据存储量将满指示给处理器，以指示处理器停止传送数据。As an optional implementation, if the amount of data stored in the buffer area is greater than or equal to the waterline value L of the buffer area, that is, the amount of data stored in the buffer area is not within the preset range, the site provided by this embodiment The loading method of the programmable gate array further includes: sending an indication that the data storage capacity of the buffer area is about to be full to the processor, so as to instruct the processor to stop transmitting data.
本实施例通过判断缓存区存储的数据量是否在预设范围内，即是否小于缓存区的水线值L，如果否，则发送缓存区数据存储量将满指示给处理器，以指示处理器停止传送数据，并继续判断缓存区存储的数据量是否在预设范围内或者是否小于缓存区的水线值L。不仅实现了数据加载的可靠性，不会冲掉数据，同时提高了加载速度。In this embodiment, by judging whether the amount of data stored in the buffer area is within a preset range, that is, whether it is less than the waterline value L of the buffer area, if not, then sending an indication that the amount of data stored in the buffer area will be full to the processor to instruct the processor Stop transmitting data, and continue to judge whether the amount of data stored in the buffer is within a preset range or whether it is smaller than the waterline value L of the buffer. Not only the reliability of data loading is realized, the data will not be washed out, but the loading speed is also improved.
作为一种可选的实施方式，参考步骤S130，执行该步骤，即通知处理器继续传输数据具体可以是：发送缓存区数据存储量未满指示给处理器，以指示处理器继续传送数据。As an optional implementation manner, referring to step S130, performing this step, that is, notifying the processor to continue to transmit data may specifically be: sending an indication that the data storage capacity of the buffer area is not full to the processor, so as to instruct the processor to continue to transmit data.
作为一种可选的实施方式，参考步骤S110，执行该步骤，即获取处理器传送过来的数据具体可以是：获取处理器通过数据总线在n个周期T内传送的数据，n>0，T>0。As an optional implementation, refer to step S110, and execute this step, that is, to obtain the data transmitted by the processor may specifically be: to obtain the data transmitted by the processor through the data bus in n cycles T, n>0, T >0.
本实施例提供的现场可编程门阵列的加载方法可以通过数据总线连续传输多个周期的数据后，再发送一次指示信号触发处理器读取反馈信号，使得加载方法的配置更加灵活，加载装置的实现更加优化，提升了整个现场可编程门阵列的加载系统的加载性能。The loading method of the field programmable gate array provided by this embodiment can continuously transmit multiple periods of data through the data bus, and then send an indication signal to trigger the processor to read the feedback signal, so that the configuration of the loading method is more flexible, and the loading device can be configured more flexibly. The implementation is more optimized, and the loading performance of the entire field programmable gate array loading system is improved.
作为一种可选的实施方式，参考步骤S140，执行该步骤，即将缓存区中的数据加载至现场可编程门阵列具体可以是：将缓存区中的数据通过加载线以t为周期，1bits/t为加载速度加载至现场可编程门阵列，t大于0。As an optional implementation manner, referring to step S140, performing this step, that is, loading the data in the buffer area to the field programmable gate array may specifically be: passing the data in the buffer area through the loading line with a cycle of t, 1bits/ t is loading speed to the field programmable gate array, and t is greater than 0.
本实施例提供的现场可编程门阵列的加载方法不仅满足了现场可编程门阵列的数据加载的传输规则，即以1bits/t为加载速度加载至现场可编程门阵列，还提高了加载速度，提升了整个现场可编程门阵列的加载系统的加载性能。The loading method of the FPGA provided by this embodiment not only satisfies the transmission rules of the data loading of the FPGA, that is, loading to the FPGA at a loading speed of 1 bits/t, but also improves the loading speed, The loading performance of the loading system of the entire field programmable gate array is improved.
作为一种可选的实施方式，缓存区存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，N为周期T内传送的数据量。As an optional implementation, the maximum amount of data stored in the cache area is Hmax, then n needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hmax; where N is the period The amount of data transferred in T.
本实施例提供的现场可编程门阵列的加载方法，即要满足连续性地加载数据至现场可编程门阵列，也要满足连续性加载数据的同时，每次在n个周期内向缓存区存储的数据量不小于缓存区存储的数据量的最大值Hmax。The loading method of the field programmable gate array provided by this embodiment is to meet the requirements of continuously loading data to the field programmable gate array, and at the same time of continuously loading data, the data stored in the buffer area within n cycles each time The amount of data is not less than the maximum value Hmax of the amount of data stored in the cache area.
作为一种可选的实施方式，参考步骤S120，即判断缓存区存储的数据量是否小于所述缓存区的水线值L具体可以是：判断n值是否满足预设条件，预设条件为0<N/T*nT-（n+1）T/t<L；如果是，则确定缓存区存储的数据量小于所述缓存区的水线值L；如果否，则确定缓存区存储的数据量大于或等于所述缓存区的水线值L。As an optional implementation, refer to step S120, that is, judging whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area may specifically be: judging whether the value of n satisfies a preset condition, and the preset condition is 0 <N/T*nT-(n+1)T/t<L; if yes, determine that the amount of data stored in the buffer is less than the watermark value L of the buffer; if not, determine the data stored in the buffer The amount is greater than or equal to the waterline value L of the buffer.
本实施例提供的现场可编程门阵列的加载方法，通过判断n值是否满足预设条件，判断所述缓存区存储的数据量是否小于所述缓存区的水线值L，方便简单，实现了缓存区的高存储性能，使得缓存区的存储性能更加稳定，进一步提高了数据的加载性能。The loading method of the field programmable gate array provided by this embodiment is convenient and simple, and realizes The high storage performance of the cache area makes the storage performance of the cache area more stable and further improves the data loading performance.
作为一种可选的实施方式，n满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足缓存区在下一n个周期T内获取的数据小于且等于Hleft，其中，Hleft为所述缓存区存储的数据量的最大值为Hmax与所述缓存区的水线值L的差值。As an optional implementation, n satisfies the inequality 0<N/T*nT-(n+1)T/t<Hleft, so that the data acquired by the cache in the next n period T is less than and equal to Hleft, Wherein, Hleft is the maximum value of the amount of data stored in the buffer area, which is the difference between Hmax and the waterline value L of the buffer area.
本实施例提供的现场可编程门阵列的加载方法，不仅需要满足当前这次在n个周期内向缓存区存储的数据量不小于缓存区的水线值L，进一步地满足下一次在n个周期内T内传送的数据小于且等于Hleft，即Hleft标识了还没有存储数据的存储空间的容纳范围。The field programmable gate array loading method provided by this embodiment not only needs to meet the requirement that the amount of data stored in the buffer area in the current n cycles is not less than the watermark value L of the buffer area, and further satisfies the requirement that the amount of data stored in the buffer area in the next n cycles The data transmitted within T is less than and equal to Hleft, that is, Hleft identifies the accommodation range of the storage space that has not yet stored data.
作为一种可选的实施方式，缓存区的水线值L需满足不等式L>2T/t，以满足缓存区通过加载线以t为周期，1bits/t为加载速度连续地加载数据至现场可编程门阵列。As an optional implementation, the waterline value L of the buffer area needs to satisfy the inequality L>2T/t, so that the buffer area can pass the loading line with t as the period and 1bits/t as the loading speed to continuously load data to the site. programming gate array.
请参阅图2，图2为本发明实施例二提供的一种现场可编程门阵列的加载装置结构示意图。如图2所示，本实施例提供的现场可编程门阵列的加载装置300包括：获取单元310、判断单元320、缓存区330和发送单元340。Please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of a loading device for a field programmable gate array provided by Embodiment 2 of the present invention. As shown in FIG. 2 , the FPGA loading device 300 provided in this embodiment includes: an acquiring unit 310 , a judging unit 320 , a buffer area 330 and a sending unit 340 .
其中，获取单元310，用于获取处理器传送过来的数据。Wherein, the acquiring unit 310 is configured to acquire the data sent by the processor.
判断单元320，用于判断缓存区330存储的数据量是否在预设范围内。The judging unit 320 is configured to judge whether the amount of data stored in the buffer area 330 is within a preset range.
缓存区330，用于根据判断单元320判断为是的结果存储数据。The buffer area 330 is configured to store data according to the result of the judging unit 320 judging yes.
发送单元340，用于根据判断单元320判断为是的结果发送通知至处理器，以通知处理器继续传送数据。The sending unit 340 is configured to send a notification to the processor according to a result determined to be yes by the judging unit 320, so as to notify the processor to continue transmitting data.
发送单元340，还用于将缓存区330中的数据加载至现场可编程门阵列。The sending unit 340 is further configured to load the data in the buffer area 330 to the field programmable gate array.
本实施例提供的现场可编程门阵列的加载装置300，通过内部设置一缓存区330，判断缓存区330存储的数据量是否在预设范围内；如果是，则发送通知给处理器，触发处理器继续传送数据，以保证缓存区330中一直有数据存储，可连续地向现场可编程门阵列加载数据，避免了加载空隙的现象发生，实现了给现场可编程门阵列快速加载数据的方法。The loading device 300 of the field programmable gate array provided by this embodiment judges whether the amount of data stored in the buffer area 330 is within a preset range by setting a buffer area 330 inside; if so, then sends a notification to the processor to trigger processing The device continues to transmit data to ensure that there is always data stored in the buffer area 330, and data can be continuously loaded to the FPGA, avoiding the phenomenon of loading gaps, and realizing a method for quickly loading data to the FPGA.
作为一种可选的实施方式，判断单元，具体用于判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果是，则确认缓存区存储的数据量是在预设范围内；所述缓存区的水线值L用于标识所述缓存区的存储空间的使用情况。As an optional implementation manner, the judging unit is specifically configured to judge whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, and if so, confirm that the amount of data stored in the buffer area is within a preset range Inside; the waterline value L of the cache area is used to identify the usage of the storage space of the cache area.
通过设置缓存区的水线值L作为判断标准，简单又可靠地实现了判断缓存区存储的数据量是否在预设范围内的方法，易实施。By setting the waterline value L of the buffer area as a judgment standard, the method of judging whether the amount of data stored in the buffer area is within a preset range is implemented simply and reliably, and is easy to implement.
作为一种可选的实施方式，发送单元，还用于根据判断单元判断为否的结果，发送缓存区数据存储量将满指示给处理器，以指示处理器停止传送数据。As an optional implementation manner, the sending unit is further configured to send an indication that the data storage capacity of the buffer area will be full to the processor according to a result of the judging unit judging No, so as to instruct the processor to stop transmitting data.
判断单元，还用于根据判断单元判断为否的结果，循环判断缓存区存储的数据量是否小于所述缓存区的水线值L。The judging unit is further configured to cyclically judge whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area according to the result of the judging unit judging No.
本实施例通过判断单元判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果否，则通过发送单元发送缓存区数据存储量将满指示给处理器，以指示处理器停止传送数据，并继续通过判断单元判断缓存区存储的数据量是否小于所述缓存区的水线值L。不仅实现了数据加载的可靠性，不会冲掉数据，同时提高了加载速度。In this embodiment, the judging unit judges whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, and if not, the sending unit sends an indication that the amount of data stored in the buffer area will be full to the processor to instruct the processor to stop The data is transmitted, and the judging unit continues to judge whether the amount of data stored in the buffer is smaller than the waterline value L of the buffer. Not only the reliability of data loading is realized, the data will not be washed out, but the loading speed is also improved.
作为一种可选的实施方式，发送单元，具体用于根据判断单元判断为是的结果发送缓存区数据存储量未满指示给处理器，以指示处理器继续传送数据。As an optional implementation manner, the sending unit is specifically configured to send an indication that the data storage capacity of the buffer area is not full to the processor according to a result of the judging unit judging yes, so as to instruct the processor to continue to transmit data.
作为一种可选的实施方式，获取单元，具体用于获取处理器通过数据总线在n个周期T内传送的数据，n>0，T>0。As an optional implementation manner, the acquiring unit is specifically configured to acquire data transmitted by the processor in n cycles T through the data bus, n>0, T>0.
本实施例通过获取单元获取数据总线连续传输多个周期的数据后，再通过发送单元发送一次指示信号触发处理器读取反馈信号，使得加载方法的配置更加灵活，加载装置的实现更加优化，提升了整个现场可编程门阵列的加载系统的加载性能。In this embodiment, after the acquisition unit acquires the data of the data bus for multiple periods of continuous transmission, the sending unit sends an indication signal to trigger the processor to read the feedback signal, so that the configuration of the loading method is more flexible, and the implementation of the loading device is more optimized and improved. The loading performance of the loading system of the entire field programmable gate array is improved.
作为一种可选的实施方式，发送单元，具体用于将缓存区中的数据通过加载线以t为周期，1bits/t为加载速度加载至现场可编程门阵列，t大于0。As an optional implementation manner, the sending unit is specifically configured to load the data in the buffer area to the field programmable gate array at a period of t and a loading speed of 1 bits/t through the loading line, and t is greater than 0.
本实施例提供的现场可编程门阵列的加载装置不仅满足了现场可编程门阵列的数据加载的传输规则，即以1bits/t为加载速度加载至现场可编程门阵列，还提高了加载速度，提升了整个现场可编程门阵列的加载系统的加载性能。The loading device of the FPGA provided by this embodiment not only satisfies the transmission rule of the data loading of the FPGA, that is, loads to the FPGA at a loading speed of 1 bits/t, but also improves the loading speed, The loading performance of the loading system of the entire field programmable gate array is improved.
作为一种可选的实施方式，缓存区存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，N为周期T内传送的数据量。As an optional implementation, the maximum amount of data stored in the cache area is Hmax, then n needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hmax; where N is the period The amount of data transferred in T.
本实施例提供的现场可编程门阵列的加载装置，即要满足连续性地加载数据至现场可编程门阵列，也要满足连续性加载数据的同时，每次在n个周期内向缓存区存储的数据量不小于缓存区存储的数据量的最大值Hmax。The field programmable gate array loading device provided in this embodiment, that is, to meet the requirements of continuously loading data to the field programmable gate array, and also to meet the requirements of continuous loading of data, at the same time, the data stored in the buffer area within n cycles each time The amount of data is not less than the maximum value Hmax of the amount of data stored in the cache area.
作为一种可选的实施方式，判断单元，具体用于判断n值是否满足预设条件，预设条件为0<N/T*nT-（n+1）T/t<L；如果是，则确定缓存区存储的数据量小于所述缓存区的水线值L；如果否，则确定缓存区存储的数据量大于或等于所述缓存区的水线值L。As an optional implementation manner, the judging unit is specifically used to judge whether the n value satisfies a preset condition, and the preset condition is 0<N/T*nT-(n+1)T/t<L; if yes, Then determine that the amount of data stored in the buffer is less than the waterline value L of the buffer; if not, determine that the amount of data stored in the buffer is greater than or equal to the waterline L of the buffer.
本实施例提供的现场可编程门阵列的加载装置，进一步通过判断单元判断n值是否满足预设条件，判断所述缓存区存储的数据量是否小于所述缓存区的水线值L，方便简单，实现了缓存区的高存储性能，使得缓存区的存储性能更加稳定，进一步提高了数据的加载性能。The loading device of the field programmable gate array provided by this embodiment further judges whether the value of n satisfies the preset condition through the judging unit, and judges whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, which is convenient and simple , realizing the high storage performance of the cache area, making the storage performance of the cache area more stable, and further improving the data loading performance.
作为一种可选的实施方式，n还需满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足缓存区在下一n个周期T内获取的数据小于且等于Hleft，Hleft为所述缓存区存储的数据量的最大值为Hmax与所述缓存区的水线值L的差值。As an optional implementation, n also needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hleft, so that the data acquired by the cache in the next n period T is less than and equal to Hleft, the maximum value of the amount of data stored by Hleft in the buffer area is the difference between Hmax and the waterline value L of the buffer area.
本实施例提供的现场可编程门阵列的加载装置，不仅需要满足当前这次在n个周期内向缓存区存储的数据量不小于缓存区的水线值L，进一步地满足下一次在n个周期内T内传送的数据小于且等于Hleft，即Hleft标识了还没有存储数据的存储空间的容纳范围。The field programmable gate array loading device provided by this embodiment not only needs to meet the requirement that the amount of data stored in the buffer area in the current n cycles is not less than the watermark value L of the buffer area, and further satisfies the next time in n cycles. The data transmitted within T is less than and equal to Hleft, that is, Hleft identifies the accommodation range of the storage space that has not yet stored data.
作为一种可选的实施方式，缓存区的水线值L需满足不等式L>2T/t，以满足缓存区通过加载线以t为周期，1bits/t为加载速度连续地加载数据至现场可编程门阵列。As an optional implementation, the waterline value L of the buffer area needs to satisfy the inequality L>2T/t, so that the buffer area can pass the loading line with t as the period and 1bits/t as the loading speed to continuously load data to the site. programming gate array.
请参阅图3，图3为本发明实施例二提供的另一种现场可编程门阵列的加载装置结构示意图。如图3所示，本实施例提供的现场可编程门阵列的加载装置400包括：输入装置410、输出装置420、处理装置430（处理装置430的数量可以为一个或多个，图4中以一个处理装置为例）和存储装置440。Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of another loading device for a field programmable gate array provided by Embodiment 2 of the present invention. As shown in FIG. 3 , the loading device 400 of the field programmable gate array provided by this embodiment includes: an input device 410, an output device 420, and a processing device 430 (the number of the processing device 430 may be one or more, and in FIG. A processing device as an example) and storage device 440.
在本发明的一些实施例中，输入装置410、输出装置420、处理装置430和存储装置440可通过总线或其它方式连接，其中，图4中以通过总线连接为例。In some embodiments of the present invention, the input device 410 , the output device 420 , the processing device 430 and the storage device 440 may be connected via a bus or in other ways, wherein connection via a bus is taken as an example in FIG. 4 .
其中，输入装置410获取处理器传送过来的数据。Wherein, the input device 410 obtains the data sent by the processor.
处理装置430执行如下步骤：判断存储装置440存储的数据量是否在预设范围内，如果是，则控制存储装置440将数据存储至存储装置440，并且控制输出装置420通知处理器继续传输数据；以及控制输出装置420将存储装置440中的数据加载至现场可编程门阵列。The processing device 430 performs the following steps: judging whether the amount of data stored in the storage device 440 is within a preset range, if yes, controlling the storage device 440 to store the data in the storage device 440, and controlling the output device 420 to notify the processor to continue transmitting data; And control the output device 420 to load the data in the storage device 440 to the FPGA.
输出装置440，用于发送通知，以通知处理器继续传输数据，以及用于将存储装置440中的数据加载至现场可编程门阵列。The output device 440 is used for sending a notification to inform the processor to continue to transmit data, and for loading the data in the storage device 440 to the FPGA.
本实施例提供的现场可编程门阵列的加载装置400，通过内部设置一存储装置440，判断存储装置440存储的数据量是否在预设范围内；如果是，则发送通知给处理器，触发处理器继续传送数据，以保证存储装置440中一直有数据存储，可连续地向现场可编程门阵列加载数据，避免了加载空隙的现象发生，实现了给现场可编程门阵列快速加载数据的方法。The loading device 400 of the field programmable gate array provided by this embodiment, by internally setting a storage device 440, judges whether the amount of data stored in the storage device 440 is within a preset range; if so, then sends a notification to the processor to trigger processing The device continues to transmit data to ensure that there is always data stored in the storage device 440, and data can be continuously loaded to the FPGA, avoiding the phenomenon of loading gaps, and realizing a method for quickly loading data to the FPGA.
作为一种可选的实施方式，处理装置判断存储装置存储的数据量是否在预设范围内具体可以是：判断存储装置存储的数据量是否小于存储装置的水线值L，如果是，则确认存储装置存储的数据量在预设范围内；所述存储装置的水线值L用于标识存储装置的存储空间的使用情况。As an optional implementation, the processing device may specifically determine whether the amount of data stored in the storage device is within a preset range: determine whether the amount of data stored in the storage device is less than the watermark value L of the storage device, and if so, confirm The amount of data stored by the storage device is within a preset range; the waterline value L of the storage device is used to identify the usage of the storage space of the storage device.
通过设置存储装置的水线值L作为判断标准，简单又可靠地实现了判断存储装置存储的数据量是否在预设范围内的方法，易实施。By setting the waterline value L of the storage device as the judgment standard, the method for judging whether the amount of data stored in the storage device is within a preset range is implemented simply and reliably, and is easy to implement.
作为一种可选的实施方式，若存储装置中存储的数据量大于或等于所述缓存区的水线值L，则处理装置控制输出装置发送存储装置数据存储量将满指示给处理器，以指示处理器停止传送数据。As an optional implementation manner, if the amount of data stored in the storage device is greater than or equal to the waterline value L of the buffer area, the processing device controls the output device to send an indication that the data storage capacity of the storage device will be full to the processor, so that Instructs the processor to stop transferring data.
本实施例通过处理装置判断存储装置存储的数据量大于或等于所述缓存区的水线值L，则通过输出装置发送存储装置数据存储量将满指示给处理器，以指示处理器停止传送数据，并继续通过处理装置判断存储装置存储的数据量是否小于所述缓存区的水线值L。不仅实现了数据加载的可靠性，不会冲掉数据，同时提高了加载速度。In this embodiment, the processing device judges that the amount of data stored in the storage device is greater than or equal to the waterline value L of the buffer area, and then the output device sends an indication that the data storage capacity of the storage device is about to be full to the processor, so as to instruct the processor to stop transmitting data , and continue to use the processing device to judge whether the amount of data stored in the storage device is smaller than the waterline value L of the buffer area. Not only the reliability of data loading is realized, the data will not be washed out, but the loading speed is also improved.
作为一种可选的实施方式，处理装置控制输出装置通知处理器继续传输数据具体可以是控制输出装置发送存储装置数据存储量未满指示给处理器，以指示处理器继续传送数据。As an optional implementation manner, the processing device controlling the output device to notify the processor to continue to transmit data may specifically control the output device to send an indication that the data storage capacity of the storage device is not full to the processor, so as to instruct the processor to continue to transmit data.
作为一种可选的实施方式，输入装置获取处理器传送过来的数据具体可以是获取处理器通过数据总线在n个周期T内传送的数据，n>0，T>0。As an optional implementation manner, the input device acquires the data transmitted by the processor, specifically, acquires the data transmitted by the processor in n cycles T through the data bus, where n>0 and T>0.
本实施例通过输入装置获取数据总线连续传输多个周期的数据后，再通过输出装置发送一次指示信号触发处理器读取反馈信号，使得加载方法的配置更加灵活，加载装置的实现更加优化，提升了整个现场可编程门阵列的加载系统的加载性能。In this embodiment, the input device obtains the data bus for multiple cycles of continuous transmission of data, and then sends an indication signal through the output device to trigger the processor to read the feedback signal, so that the configuration of the loading method is more flexible, and the implementation of the loading device is more optimized. The loading performance of the loading system of the entire field programmable gate array is improved.
作为一种可选的实施方式，处理装置控制输出装置将存储装置中的数据加载至现场可编程门阵列具体可以是：处理装置控制输出装置将存储装置中的数据通过加载线以t为周期，1bits/t为加载速度加载至现场可编程门阵列，t大于0。As an optional implementation manner, the processing device controlling the output device to load the data in the storage device to the field programmable gate array may specifically be: the processing device controls the output device to pass the data in the storage device through the loading line at a period of t, 1bits/t is the loading speed for loading to the field programmable gate array, and t is greater than 0.
本实施例提供的现场可编程门阵列的加载装置不仅满足了现场可编程门阵列的数据加载的传输规则，即以1bits/t为加载速度加载至现场可编程门阵列，还提高了加载速度，提升了整个现场可编程门阵列的加载系统的加载性能。The loading device of the FPGA provided by this embodiment not only satisfies the transmission rule of the data loading of the FPGA, that is, loads to the FPGA at a loading speed of 1 bits/t, but also improves the loading speed, The loading performance of the loading system of the entire field programmable gate array is improved.
作为一种可选的实施方式，存储装置存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，N为周期T内传送的数据量。As an optional implementation, the maximum amount of data stored in the storage device is Hmax, then n needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hmax; where N is the period The amount of data transferred in T.
本实施例提供的现场可编程门阵列的加载装置，即要满足连续性地加载数据至现场可编程门阵列，也要满足连续性加载数据的同时，每次在n个周期内向存储装置存储的数据量不小于存储装置存储的数据量的最大值Hmax。The loading device for the field programmable gate array provided by this embodiment needs to meet the requirements of continuously loading data to the field programmable gate array, and also needs to meet the requirement of continuously loading data, and at the same time, store the data stored in the storage device within n cycles each time. The amount of data is not less than the maximum value Hmax of the amount of data stored in the storage device.
作为一种可选的实施方式，处理装置判断存储装置存储的数据量是否小于所述缓存区的水线值L具体可以是：处理装置判断n值是否满足预设条件，预设条件为0<N/T*nT-（n+1）T/t<L；As an optional implementation manner, the processing device judging whether the amount of data stored in the storage device is smaller than the waterline value L of the buffer area may specifically be: the processing device judges whether the value of n satisfies a preset condition, and the preset condition is 0< N/T*nT-(n+1)T/t<L;
如果是，则确定存储装置存储的数据量小于存储装置的水线值L；如果否，则确定存储装置存储的数据量大于或等于存储装置的水线值L。If yes, determine that the amount of data stored by the storage device is less than the waterline value L of the storage device; if not, determine that the amount of data stored by the storage device is greater than or equal to the waterline value L of the storage device.
本实施例提供的现场可编程门阵列的加载装置，进一步通过处理装置判断n值是否满足预设条件，判断存储装置存储的数据量是否小于存储装置的水线值L，方便简单，实现了存储装置的高存储性能，使得存储装置的存储性能更加稳定，进一步提高了数据的加载性能。The loading device of the field programmable gate array provided by this embodiment further judges whether the value of n satisfies the preset condition through the processing device, and judges whether the amount of data stored by the storage device is less than the waterline value L of the storage device, which is convenient and simple, and realizes storage The high storage performance of the device makes the storage performance of the storage device more stable and further improves the data loading performance.
作为一种可选的实施方式，n还需满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足存储装置在下一n个周期T内获取的数据小于且等于Hleft，Hleft为存储装置存储的数据量的最大值为Hmax与存储装置的水线值L的差值。As an optional implementation, n also needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hleft, so that the data acquired by the storage device in the next n period T is less than and equal to Hleft, where Hleft is the maximum value of the amount of data stored by the storage device is the difference between Hmax and the waterline value L of the storage device.
本实施例提供的现场可编程门阵列的加载装置，不仅需要满足当前这次在n个周期内向缓存区存储的数据量不小于缓存区的水线值L，进一步地满足下一次在n个周期内T内传送的数据小于且等于Hleft，即Hleft标识了还没有存储数据的存储空间的容纳范围。The field programmable gate array loading device provided by this embodiment not only needs to meet the requirement that the amount of data stored in the buffer area in the current n cycles is not less than the watermark value L of the buffer area, and further satisfies the next time in n cycles. The data transmitted within T is less than and equal to Hleft, that is, Hleft identifies the accommodation range of the storage space that has not yet stored data.
作为一种可选的实施方式，存储装置的水线值L需满足不等式L>2T/t，以满足存储装置通过加载线以t为周期，1bits/t为加载速度连续地加载数据至现场可编程门阵列。As an optional implementation, the waterline value L of the storage device needs to satisfy the inequality L>2T/t, so that the storage device can continuously load data to the site through the loading line with a period of t and a loading speed of 1 bits/t. programming gate array.
请参阅图4，图4为本发明实施例三提供的一种现场可编程门阵列的加载系统结构示意图。如图4所示，本实施例提供的现场可编程门阵列的加载系统500包括：处理器510、加载装置520和现场可编程门阵列530，加载装置520包括缓存区521。Please refer to FIG. 4 . FIG. 4 is a schematic structural diagram of a loading system for a field programmable gate array provided by Embodiment 3 of the present invention. As shown in FIG. 4 , the FPGA loading system 500 provided in this embodiment includes: a processor 510 , a loading device 520 and a FPGA 530 , and the loading device 520 includes a buffer area 521 .
其中，处理器510，用于传送数据至加载装置520。Wherein, the processor 510 is configured to transmit data to the loading device 520 .
加载装置520，用于获取处理器510传送过来的数据，判断缓存区521存储的数据量是否在预设范围内，如果是，将数据存储至缓存区521，并且通知处理器510继续传输数据；以及用于将缓存区521中的数据加载至现场可编程门阵列530。The loading device 520 is used to obtain the data transmitted by the processor 510, determine whether the amount of data stored in the buffer area 521 is within a preset range, if so, store the data in the buffer area 521, and notify the processor 510 to continue transmitting data; And for loading the data in the buffer area 521 to the FPGA 530 .
处理器510，还用于接收加载装置520发送的触发处理器510继续传输数据的通知，以继续传送数据至加载装置520。The processor 510 is further configured to receive a notification from the loading device 520 that triggers the processor 510 to continue to transmit data, so as to continue to transmit the data to the loading device 520 .
现场可编程门阵列530，用于配置加载装置520加载的数据。The field programmable gate array 530 is used to configure the data loaded by the loading device 520 .
本实施例提供的现场可编程门阵列的加载系统500，通过内部设置加载装置520，判断设置在加载装置520中的缓存区521存储的数据量是否在预设范围内；如果是，则发送通知给处理器510，触发处理器510继续传送数据，以保证缓存区521中一直有数据存储，可连续地向现场可编程门阵列加载数据，避免了加载空隙的现象发生，实现了给现场可编程门阵列快速加载数据的方法。The loading system 500 of the field programmable gate array provided by this embodiment, by setting the loading device 520 inside, judges whether the amount of data stored in the buffer area 521 in the loading device 520 is within the preset range; if yes, a notification is sent To the processor 510, trigger the processor 510 to continue to transmit data, to ensure that there is always data storage in the buffer area 521, and can continuously load data to the field programmable gate array, avoiding the phenomenon of loading gaps, and realizing the field programmable A method for quickly loading data into a gate array.
作为一种可选的实施方式，加载装置，具体用于判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果是，则确认缓存区存储的数据量在预设范围内；所述缓存区的水线值L用于标识缓存区的存储空间的使用情况。As an optional implementation, the loading device is specifically used to determine whether the amount of data stored in the buffer is less than the waterline value L of the buffer, and if so, confirm that the amount of data stored in the buffer is within a preset range ; The waterline value L of the cache area is used to identify the usage of the storage space of the cache area.
通过设置缓存区的水线值L作为判断标准，简单又可靠地实现了判断缓存区存储的数据量是否在预设范围内的方法，易实施。By setting the waterline value L of the buffer area as a judgment standard, the method of judging whether the amount of data stored in the buffer area is within a preset range is implemented simply and reliably, and is easy to implement.
作为一种可选的实施方式，加载装置，还用于根据缓存区存储的数据量大于或等于所述缓存区的水线值L的判断结果发送缓存区数据存储量将满指示给处理器，以指示处理器停止传送数据，并继续判断缓存区存储的数据量是否小于缓存区的水线值L；As an optional implementation manner, the loading device is further configured to send an indication that the amount of data stored in the buffer area is about to be full to the processor according to the judgment result that the amount of data stored in the buffer area is greater than or equal to the waterline value L of the buffer area, To instruct the processor to stop transmitting data, and continue to judge whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area;
处理器，还用于接收加载装置发送的缓存区数据存储量将满指示，以停止传送数据至加载装置。The processor is further configured to receive an indication from the loading device that the data storage capacity of the buffer area is about to be full, so as to stop transmitting data to the loading device.
本实施例通过加载装置判断缓存区存储的数据量是否小于所述缓存区的水线值L，如果否，则发送缓存区数据存储量将满指示给处理器，以指示处理器停止传送数据，并继续判断缓存区存储的数据量是否小于所述缓存区的水线值L。不仅实现了数据加载的可靠性，不会冲掉数据，同时提高了加载速度。In this embodiment, the loading device judges whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, and if not, sends an indication that the amount of data stored in the buffer area will be full to the processor, to instruct the processor to stop transmitting data, And continue to judge whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area. Not only the reliability of data loading is realized, the data will not be washed out, but the loading speed is also improved.
作为一种可选的实施方式，加载装置，具体用于发送缓存区数据存储量未满指示给处理器，以指示处理器继续传送数据。As an optional implementation manner, the loading device is specifically configured to send an indication that the amount of data stored in the buffer area is not full to the processor, so as to instruct the processor to continue transferring data.
处理器，具体用于接收加载装置发送的缓存区数据存储量未满指示，以继续传送数据至加载装置。The processor is specifically configured to receive an indication from the loading device that the data storage capacity of the buffer is not full, so as to continue to transmit data to the loading device.
作为一种可选的实施方式，处理器具体用于通过数据总线在n个周期T内传送数据至加载装置。As an optional implementation manner, the processor is specifically configured to transmit data to the loading device within n cycles T through the data bus.
加载装置，具体用于获取处理器通过数据总线在n个周期T内传送的数据；n>0，T>0。The loading device is specifically used to obtain the data transmitted by the processor in n cycles T through the data bus; n>0, T>0.
本实施例通过加载装置获取数据总线连续传输多个周期的数据后，再发送一次指示信号触发处理器读取反馈信号，使得加载方法的配置更加灵活，加载装置的实现更加优化，提升了整个现场可编程门阵列的加载系统的加载性能。In this embodiment, after the loading device acquires the data of multiple cycles of continuous transmission by the data bus, an indication signal is sent again to trigger the processor to read the feedback signal, so that the configuration of the loading method is more flexible, the realization of the loading device is more optimized, and the entire site is improved. Loading performance of the loading system for programmable gate arrays.
作为一种可选的实施方式，加载装置，具体用于通过加载线以t为周期，1bits/t为加载速度连续地加载数据至现场可编程门阵列，t大于0。As an optional implementation manner, the loading device is specifically configured to continuously load data to the field programmable gate array through the loading line with a period of t and a loading speed of 1 bits/t, and t is greater than 0.
现场可编程门阵列，具体用于配置加载装置通过加载线以t为周期，1bits/t为加载速度连续加载的数据。The field programmable gate array is specifically used to configure the data loaded continuously by the loading device through the loading line with a period of t and a loading speed of 1bits/t.
本实施例提供的现场可编程门阵列的加载系统不仅满足了加载数据至现场可编程门阵列的传输规则，即以1bits/t为加载速度加载至现场可编程门阵列，还提高了加载速度，提升了整个现场可编程门阵列的加载系统的加载性能。The field programmable gate array loading system provided by this embodiment not only meets the transmission rules for loading data to the field programmable gate array, that is, loads to the field programmable gate array at a loading speed of 1 bits/t, but also improves the loading speed, The loading performance of the loading system of the entire field programmable gate array is improved.
作为一种可选的实施方式，缓存区存储的数据量的最大值为Hmax，则n需满足不等式0<N/T*nT-（n+1）T/t<Hmax；其中，N为周期T内传送的数据量。As an optional implementation, the maximum amount of data stored in the cache area is Hmax, then n needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hmax; where N is the period The amount of data transferred in T.
本实施例提供的现场可编程门阵列的加载系统，即要满足连续性地加载数据至现场可编程门阵列，也要满足连续性加载数据的同时，每次在n个周期内向缓存区存储的数据量不小于缓存区存储的数据量的最大值Hmax。The field programmable gate array loading system provided by this embodiment needs to meet the requirements of continuously loading data to the field programmable gate array, and at the same time of continuously loading data, the data stored in the buffer area within n cycles each time The amount of data is not less than the maximum value Hmax of the amount of data stored in the cache area.
作为一种可选的实施方式，加载装置，具体用于判断n值是否满足预设条件，预设条件为0<N/T*nT-（n+1）T/t<L；As an optional implementation, the loading device is specifically used to judge whether the n value satisfies a preset condition, and the preset condition is 0<N/T*nT-(n+1)T/t<L;
如果是，则确定缓存区存储的数据量小于所述缓存区的水线值L；如果否，则确定缓存区存储的数据量大于或等于所述缓存区的水线值L。If yes, it is determined that the amount of data stored in the buffer is smaller than the waterline value L of the buffer; if not, it is determined that the amount of data stored in the buffer is greater than or equal to the waterline L of the buffer.
本实施例提供的现场可编程门阵列的加载系统，通过加载装置判断n值是否满足预设条件，判断所述缓存区存储的数据量是否小于所述缓存区的水线值L，方便简单，实现了缓存区的高存储性能，使得缓存区的存储性能更加稳定，进一步提高了数据的加载性能。The loading system of the field programmable gate array provided by this embodiment judges whether the value of n satisfies the preset condition through the loading device, and judges whether the amount of data stored in the buffer area is less than the waterline value L of the buffer area, which is convenient and simple. The high storage performance of the cache area is realized, the storage performance of the cache area is more stable, and the data loading performance is further improved.
作为一种可选的实施方式，n还需满足不等式0<N/T*nT-（n+1）T/t<Hleft，以满足缓存区在下一n个周期T内获取的数据小于且等于Hleft，Hleft为所述缓存区存储的数据量的最大值为Hmax与所述缓存区的水线值L的差值。As an optional implementation, n also needs to satisfy the inequality 0<N/T*nT-(n+1)T/t<Hleft, so that the data acquired by the cache in the next n period T is less than and equal to Hleft, the maximum value of the amount of data stored by Hleft in the buffer area is the difference between Hmax and the waterline value L of the buffer area.
本实施例提供的现场可编程门阵列的加载系统，不仅需要满足当前这次在n个周期内向缓存区存储的数据量不小于缓存区的水线值L，进一步地满足下一次在n个周期内T内传送的数据小于且等于Hleft，即Hleft标识了还没有存储数据的存储空间的容纳范围。The field programmable gate array loading system provided by this embodiment not only needs to meet the requirement that the amount of data stored in the buffer area in the current n cycles is not less than the watermark value L of the buffer area, but also needs to further satisfy the requirements for the next time in n cycles. The data transmitted within T is less than and equal to Hleft, that is, Hleft identifies the accommodation range of the storage space that has not yet stored data.
作为一种可选的实施方式，缓存区的水线值L需满足不等式L>2T/t，以满足加载装置通过加载线以t为周期，1bits/t为加载速度连续地加载数据至现场可编程门阵列。As an optional implementation, the waterline value L of the buffer area needs to satisfy the inequality L>2T/t, so that the loading device can continuously load data to the site through the loading line at a period of t and a loading speed of 1bits/t. programming gate array.
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，的存储介质可为磁碟、光盘、只读存储记忆体（Read-Only Memory，ROM）或随机存取存储器（Random Access Memory，简称RAM）等。Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented through computer programs to instruct related hardware, and the programs can be stored in a computer-readable storage medium. , may include the flow of the embodiments of the above-mentioned methods. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM for short).
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| CN201210388905.1ACN102929663B (en) | 2012-10-15 | 2012-10-15 | The loading method of a kind of field programmable gate array, Apparatus and system |
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